IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`––––––––––
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`––––––––––
`
`REALTEK SEMICONDUCTOR CORP.,
`and
`TCL INDUSTRIES HOLDINGS CO., INC.
`
`Petitioner,
`v.
`
`ATI TECHNOLOGIES ULC
`Patent Owner.
`_________________________
`
`Case No. IPR2023-00922
`
`U.S. Patent No. 8,760,4541
`
`_________________________
`
`PETITIONER’S REPLY TO PATENT OWNER’S
`RESPONSE TO PETITION
`
`1 Joinder with IPR2024-00366
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`I.
`II.
`
`B.
`
`C.
`
`D.
`
`INTRODUCTION ........................................................................................... 1
`CLAIM CONSTRUCTION ............................................................................ 1
`A.
`“Unified shader” .................................................................................... 1
`B.
`“Operative to” ........................................................................................ 1
`C.
`“Various Degrees of Completion” ........................................................ 2
`D.
`ATI’s Improper “Consideration” And “Determination” Limitations ... 3
`III. GROUND 1: THE LINDHOLM REFERENCES RENDER CLAIMS 1-11
`OBVIOUS ........................................................................................................ 6
`A.
`ATI Fails to Show Conception of the “Complete and Operative
`Invention” Under Federal Circuit Precedent ......................................... 6
`Dr. Mangione-Smith Offers No Opinion As to Conception of Many
`Limitations That ATI Argues Are Required by the Challenged Claims
` ............................................................................................................... 9
`Claims 1, 3, 4, 5-10: “Considering” Available Space and
`“Determining” .....................................................................................11
`Claim 11: Performing Operations “At Various Degrees of
`Completion Based on Switching Between Instructions” ....................12
`“In Response To” (Claim 2) ................................................................13
`E.
`Claim 6: Memory Separate From the “Store” ....................................14
`F.
`“Control Signal” (Claims 7 and 10) and “Arbiter” (Claim 10)...........15
`G.
`IV. GROUND 2: AMANATIDES AND KOHN RENDER CLAIMS 1-11
`OBVIOUS ......................................................................................................15
`A.
`Executing Operations Based on Available Space (Claims 5-10) And
`Performing Operations “Until” Storage is Available (Claims 1, 3, 4)15
`Claim 11: Performing Operations “At Various Degrees of
`Completion Based on Switching Between Instructions” ....................16
`Claims 2 and 5: “Selected Data” ........................................................18
`Claims 7 and 10: “Selection Circuit” Is Within the Alleged “Unified
`Shader” ................................................................................................18
`Claims 7 and 10: “Control Signal” .....................................................19
`“Selection Circuit” (Claims 7 and 10) and “Arbiter” (Claim 10) .......19
`
`B.
`
`C.
`D.
`
`E.
`F.
`
`i
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`V.
`
`VI.
`
`B.
`
`C.
`D.
`
`GROUND 3: SELZER AND FISKE RENDER CLAIMS 1-11
`OBVIOUS ......................................................................................................21
`A.
`Executing Operations Based on Available Space (Claims 5-10) And
`Performing Operations “Until” Storage is Available
`(Claims 1, 3, 4) ....................................................................................21
`Claim 11: Performing Operations “At Various Degrees of
`Completion Based on Switching Between Instructions” ....................24
`Claim 2: “In Response To” ................................................................24
`Claims 2, 5-7, 10, 11: “Sequencer,” “Instruction Store,” “Circuitry,”
`“Selection Circuit,” and “Arbiter” ......................................................24
`Claims 2, 5, 11: “Sequencer” and “Instruction Store” Maintain
`Instructions ..........................................................................................25
`“Control Signal” (claims 7 and 10) and “Arbiter” (claim 10) ............25
`F.
`G. Motivation to Combine Selzer and Fiske ............................................26
`SECONDARY CONSIDERATIONS ...........................................................27
`
`E.
`
`ii
`
`

`

`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`ATI Tech. ULC v. Iancu,
`920 F.3d 1362 (Fed. Cir. 2019) ........................................................................ 7, 9
`Brand v. Miller,
`487 F.3d 862 (Fed. Cir. 2007) .............................................................................. 6
`Burroughs Wellcome Co. v. Barr Labs., Inc.,
`40 F.3d 1223 (Fed. Cir. 1994) .............................................................................. 6
`Dawson v. Dawson,
`710 F.3d 1347 (Fed. Cir. 2013) ............................................................................ 6
`In re GPAC, Inc.,
`57 F.3d 1573 (Fed. Cir. 1995) ............................................................................ 29
`In re Imes,
`778 F.3d 1250 (Fed. Cir. 2015) ............................................................................ 1
`Info-Hold, Inc. v. Applied Media Tech. Corp.,
`783 F.3d 1262 (Fed. Cir. 2015) ............................................................................ 1
`Milwaukee Elec. Tool Corp. v. Snap-On Inc.,
`271 F. Supp. 3d 990 (E.D. Wis. 2017) ................................................................. 7
`Ormco Corp. v. Align Tech., Inc.,
`463 F.3d 1299 (Fed. Cir. 2006) .......................................................................... 29
`Pfaff v. Wells Elecs, Inc.,
`525 U.S. 55 (1998) ................................................................................................ 7
`Textron Innovations, Inc. v. American Eurocopter Corp.,
`498 Fed. Appx. 23 (Fed. Cir. 2012) .................................................................... 18
`
`iii
`
`

`

`1013
`1014
`
`1015
`
`1016
`1017
`
`PETITIONER'S EXHIBIT LIST
`Exhibit # Reference Name
`1001
`U.S. Patent 8,760,454 to Morein et al.
`1002
`Prosecution History of U.S. Patent 8,760,454
`1003
`Declaration of Hanspeter Pfister, Ph.D.
`1004
`Curriculum Vitae of Hanspeter Pfister, Ph.D.
`1005
`Lindholm 685
`1006
`Lindholm 913
`1007
`Amanatides
`1008
`Kohn
`1009
`Selzer [Library of Congress]
`1010
`Fiske
`1011
`IEEE – Fiske
`1012
`Declaration of Gordon MacPherson re Authentication of Fiske (May
`11, 2023)
`IEEE – Kohn
`Declaration of Gordon MacPherson re Authentication of Kohn (May
`11, 2023)
`Initial Determination on Violation of Section 337, Certain Consumer
`Electronics and Display Devices With Graphics Processing and
`Graphics Processing Units Therein, 337-TA-932 (October 9, 2015)
`Selzer [University of California, Berkeley, Library]
`Redacted Deposition Transcript of Andrew E. Gruber, taken March
`17, 2015, in ITC Case No. 337-TA-932
`Declaration of Hanspeter Pfister, Ph.D.
`Deposition Transcript of William Mangione-Smith (5/10/2024)
`https://en.wikipedia.org/wiki/DirectX
`https://en.wikipedia.org/wiki/Unified_shader_model
`https://en.wikipedia.org/wiki/GeForce_8_series
`https://www.hardwarezone.com.sg/feature-nvidia-geforce-8800-gtx-
`gts-g80-worlds-first-dx10-gpu/embracing-unified-shader-
`architecture
`https://en.wikipedia.org/wiki/Radeon_HD_2000_series
`
`1018
`1019
`1020
`1021
`1022
`1023
`
`1024
`
`iv
`
`

`

`I.
`
`II.
`
`INTRODUCTION
`Claims 1-11 of U.S. Patent No. 8,760,454 are unpatentable.
`
`CLAIM CONSTRUCTION
`Unless expressly addressed herein, claim terms should be given their plain
`
`and ordinary meaning.
`
`“Unified shader”
`A.
`Petitioner agrees with the Board that “unified shader” means a shader that is
`
`configured to perform both vertex and pixel operations.
`
`“Operative to”
`B.
`Claims 2-7 recite the term “operative to” in connection with instructions
`
`(claims 2, 5), processing unit and shared resources (claims 3, 4), circuitry (claim 6),
`
`and selection circuit (claim 7). “Operative to” or “operable to” is typically construed
`
`to mean “capable of.” In re Imes, 778 F.3d 1250, 1253-54 (Fed. Cir. 2015); Info-
`
`Hold, Inc. v. Applied Media Tech. Corp., 783 F.3d 1262, 1265, 1268 (Fed. Cir.
`
`2015). The ’454 specification likewise describes the claimed unified shader and its
`
`components as being “capable of” and “able to.” EX1001, 2:58-61 (“the present
`
`invention is directed to a unified shader that is capable of ...”), 6:29-33 (same), 6:36-
`
`41 (unified shader “capable of”), 5:21-36 (unified shader “of the present invention
`
`is able to…”). Accordingly, “operative to” means “capable of.”
`
`1
`
`

`

`“Various Degrees of Completion”
`C.
`Claim 11 recites that the claimed processor unit performs vertex and pixel
`
`operations “at various degrees of completion based on switching between
`
`instructions in the instruction store.” ATI adds the requirement of switching
`
`between “unfinished vertex operations and pixel operations” without support or
`
`analysis. POR 32-33. ATI cites Dr. Mangione-Smith’s declaration ¶234, but the
`
`declaration only repeats the claim language. ATI also cites Dr. Pfister’s deposition
`
`testimony, but this was in response to a hypothetical in which there are only two
`
`operations. Id. Dr. Pfister reasoned that to satisfy the claim requirement of multiple
`
`switches, with only two operations, the first operation must be “unfinished.”
`
`EX1018 ¶22. But claim 11 requires switching between “vertex manipulation
`
`operations [plural] and pixel manipulation operations [plural] at various degrees of
`
`completion,” and is not limited to—nor covers—switching between a total of two
`
`operations.
`
`The plain and ordinary meaning of “various degrees of completion” would
`
`include operations that are about to start, in process (“unfinished”), or completed.
`
`EX1018, ¶¶21-22. Nothing in the ’454 patent manifests a clear disavowal of the full
`
`scope of this plain and ordinary meaning. The term requires no construction and is
`
`not limited to “unfinished” operations.
`
`2
`
`

`

`D.
`
`ATI’s Improper “Consideration” And “Determination”
`Limitations
`ATI and its expert argue that claims 1, 3, 4, and 5-10 “require consideration
`
`of the amount of available space.” See POR 29, 32, 40, 54; EX2121, ¶¶308-313,
`
`EX1019, 85:11-86:17. ATI further argues that the unified shader must “determine
`
`which data type to execute” based on such “consideration.” Id. ATI is wrong.2
`
`First, the claims do not require any such “consideration” or “determination”
`
`actions. EX1018, ¶¶3-9. Dr. Mangione-Smith could not point to any term that
`
`should be construed to require “consideration” or “determination” steps. EX1019,
`
`85:11-86:17. Claim 1 requires only that vertex and pixel operations are performed
`
`“unless the general purpose register block does not have enough available space…”
`
`As Dr. Mangione-Smith agreed, everything in claim 1 after “unless” is conditional
`
`and not required when determining invalidity. EX1019, 90:3-10. See also, Ex Parte
`
`Schulhauser, 2016 WL 6277792 (PTAB Apr. 28, 2016) (precedential). Regardless,
`
`nothing after the “unless” recites anything more than continuing pixel operations
`
`“until” more space becomes available.
`
`Claims 3, 4 and 5-10 also have no “consideration” or “determination”
`
`requirements. In claim 3, the processor need only perform pixel operations until
`
`enough shared resources become available to perform vertex operations. Claim 4
`
`2 ATI does not argue these additional limitations for claim 11.
`
`3
`
`

`

`is the inverse. Claim 5 requires the execution of pixel and vertex calculation
`
`operations on “selected data maintained in a store depending upon an amount of
`
`space available in the store.” No “evaluation” or “consideration” of storage space is
`
`required, and moreover, the selection of “selected data … depending on an amount
`
`of space available” occurs before the sequencer “causes” the processor unit to
`
`execute operations.
`
`Moreover,
`
`the
`
`’454 patent
`
`teaches
`
`that any “consideration” and
`
`“determination” steps are not carried out by the claimed unified shader. The claims
`
`are directed solely to a unified shader. EX1019, 25:17-19, EX1018 ¶4. Figure 5 is
`
`a “block diagram of the unified shader”:
`
`4
`
`

`

`Figure 4A shows where the unified shader fits into the “graphics processor
`
`architecture”:
`
`ATI and its expert agree that it is the arbiter that “considers” the amount of
`
`available space and then “determines” what type of vertex or pixel data to place into
`
`the general purpose register block based on its own “arbitration scheme.” EX1001,
`
`4:18-28, 5:32-52; EX1018, ¶4; POR 7-8; EX1019, 76:6-16. The unified shader
`
`simply operates “based on information passed from the multiplexer” via the arbiter.
`
`Id., 5:23-27; EX1018, ¶4. It would be improper to import an arbiter limitation into
`
`claims 1, 3, 4, and 5, which are directed solely to the unified shader.
`
`5
`
`

`

`III. GROUND 1: THE LINDHOLM REFERENCES RENDER CLAIMS 1-
`11 OBVIOUS
`A.
`ATI Fails to Show Conception of the “Complete and Operative
`Invention” Under Federal Circuit Precedent
`The Board acknowledged that the dynamic memory aspects of the R400
`
`design may not have worked properly or been embodied into an operable product
`
`until the R600 (if at all). ID 33. Nevertheless, the Board concluded that even if “the
`
`dynamic memory aspects of the R400 design did not work properly,” the evidence
`
`showed “an idea that was definite and permanent enough that one skilled in the art
`
`could understand the invention” during the early stages of R400 development. Id.
`
`But conception also requires “a complete and operative invention, as it is
`
`hereafter to be applied in practice.” Burroughs Wellcome Co. v. Barr Labs., Inc., 40
`
`F.3d 1223, 1228 (Fed. Cir. 1994). Conception is “complete and operative” when
`
`“only ordinary skill would be necessary to reduce the invention to practice, without
`
`extensive research or experimentation,” and “courts require corroborating evidence
`
`of a contemporaneous disclosure that would enable one skilled in the art to make the
`
`invention.” Id. (emphasis added). Uncertainty revealed by “the subsequent course
`
`of experimentation, especially experimental failures,” may demonstrate that
`
`conception is not “complete and operative.” Id. at 1229. Accord, Dawson v.
`
`Dawson, 710 F.3d 1347, 1356 (Fed. Cir. 2013); Brand v. Miller, 487 F.3d 862 (Fed.
`
`Cir. 2007). A “complete” conception is shown “by instances making clear that it did
`
`6
`
`

`

`so work,” whereas failed attempts to reduce the invention to practice show a lack of
`
`a complete conception. Pfaff v. Wells Elecs, Inc., 525 U.S. 55, 66, n. 12 (1998). See,
`
`e.g., The Regents of the University of California v. The Broad Institute, Inc.,
`
`Interference No. 106,115, Decision on Priority (PTAB Feb. 28, 2022) (experimental
`
`failures and a five-month period of research and experimentation showed the
`
`inventor did not yet possess a complete invention); Milwaukee Elec. Tool Corp. v.
`
`Snap-On Inc., 271 F. Supp. 3d 990, 1019 (E.D. Wis. 2017) (experimental failures
`
`showed a lack of a “complete and operative” conception).
`
`Petitioner cited evidence from the co-inventor, Mr. Gruber, that the “dynamic
`
`register file allocation” was never tested or found to work during the development
`
`of the R400, did not function properly when reduced to silicon for the later Xenos
`
`or R600 chip in 2005/2006, and in fact, may have never worked. Paper 8, 6-8;
`
`EX1017, 25, 103-107, 115-116, 167. Even in the R600, Mr. Gruber testified that
`
`the division of the register file may have only been a fixed value for vertices and
`
`pixels. Id. Moreover, no chip was ever built based on the R400 or R500, and there
`
`were “substantial changes” between the R500 and R600, including “substantial
`
`changes” to the sequencer. EX1017 7-9. The Xenos chip did not ship until 2005
`
`and the R600 in 2007.
`
`Patent Owner bears the burden of proof to show prior conception and
`
`diligence. ATI Tech. ULC v. Iancu, 920 F.3d 1362, 1369 (Fed. Cir. 2019). But ATI
`
`7
`
`

`

`has done nothing to prove that any conception prior to June 2003 was a “complete
`
`and operative invention” that could be reduced to practice without extensive
`
`research or experimentation. ATI never addresses the above testimony of Mr.
`
`Gruber and never cites any evidence that the “dynamic” memory allocation or
`
`priority ever actually worked. POR 17-29. Rather, ATI argues that “over one
`
`hundred project managers/designers diligently worked to implement and test the
`
`R400” from at least 2001 until 2003. Id. 25, EX2001 ¶196. And yet, as Mr. Gruber
`
`testified, the “dynamic register file allocation” never worked. The R400 Sequencer
`
`Specification itself identifies as an “Open Issue” the “[n]eed to do some testing …
`
`on the register file allocation method (dynamic VS static)” in Versions 1.6 thru 2.11,
`
`the last of which bears an “Originate Date” of July 9, 2003, the last version of the
`
`sequencer specification. EX2119, 375-1318. This corroborates that the issue was
`
`never resolved in the R400.
`
`When more than 100 engineers work on a development project from 2001 to
`
`2005 or later, and still can’t get a claimed feature to work, this demonstrates an
`
`inability of a POSITA to reduce a claimed invention to practice “without extensive
`
`research or experimentation”—even if the issue is fixed subsequently. Dr.
`
`Mangione-Smith offers no opinion regarding actual reduction to practice, much less
`
`that the dynamic register file allocation or prioritization of vertices/pixels based on
`
`available memory or workload actually worked—at any time. EX2001 ¶¶ 71-302.
`
`8
`
`

`

`The attached Declarations from Wolfe, Watson, and Lefebre (EX2002, 2003, 2004)
`
`were directed to the ’053 patent and do not address the feature. And in ATI, the
`
`Federal Circuit
`
`In ATI, the Federal Circuit only held that there was diligence followed by
`
`constructive reduction to practice. ATI, 920 F.3d at 1366, 1369. The Federal Circuit
`
`did not address actual reduction to practice, nor did it address conception, which was
`
`not disputed on appeal. Thus, it also never reached the question of whether ATI had
`
`a “complete and operative” conception of the dynamic memory/priority limitations
`
`claimed in the ’454 Patent.
`
`Accordingly, ATI has failed to show a complete and operative conception of
`
`the ’454 Patent claims prior to June 2003.
`
`B.
`
`Dr. Mangione-Smith Offers No Opinion As to Conception of
`Many Limitations That ATI Argues Are Required by the
`Challenged Claims
`As discussed throughout this Reply, ATI attempts to add limitations to avoid
`
`the prior art. See, e.g., Sections II.C-D., III.E-F. However, ATI cites no evidence—
`
`and its expert does not opine—that these requirements were conceived prior to June
`
`2003:
`
` Claims 1, 3, 4, 5: ATI’s added “consideration” and “determining”
`
`requirements, supra II.D.. But cf. EX2001 ¶85 (no identification of any
`
`component or process of the “unified shader” during conception that
`
`9
`
`

`

`“considered” the amount of available space and then “determined” the type of
`
`data to execute, only that the unified shader performs operations until space
`
`becomes available).
`
` Claim 2: ATI adds a limitation that “receiving selected data from a data
`
`storage” is what “causes execution of instructions,” as opposed to instructions
`
`or a control signal. POR 33. But cf. EX2001 ¶¶112-117.
`
` Claims 2 and 5: ATI argues that “selected data” requires the unified shader
`
`to be “selecting data from a data store” and then “transmitting that data to the
`
`processor.” POR 44. But cf. EX2001 ¶¶105-117, 148-154.
`
` Claims 7 and 10: For conception, Dr. Mangione-Smith opines the “control
`
`signal” is just control packets with state pointer information. EX2001 ¶¶161-
`
`162, 176-177. But ATI contends the claims require “electrical signals used to
`
`control internal or external devices or processes” and that “packets” are not
`
`control signals. POR 35, 50.
`
` Claim 11: ATI argues that the unified shader must be able to switch back and
`
`forth between “unfinished” vertex/pixel operations. POR 10, 32-33. But cf.
`
`EX2001 ¶¶189-194 (not applying requirement for conception).
`
`If the Board finds any of these added limitations are required, then ATI has
`
`failed to show prior conception for this additional reason.
`
`10
`
`

`

`C.
`
`Claims 1, 3, 4, 5-10: “Considering” Available Space and
`“Determining”
`As discussed supra Section II.D., ATI improperly imports limitations into
`
`claims 1, 3, 4, and 5-10: “consideration” or “evaluation” of available space and
`
`“determination” of what to execute based on that “evaluation.” POR 29-32. The
`
`claims do not require such limitations. Nevertheless, the Lindholm references would
`
`render these limitations obvious.
`
`Lindholm discloses prioritization of vertex or pixel operations depending on
`
`available storage space. Pet. 30-33. Lindholm discloses selection based on the
`
`availability of source data, which includes the stored “incoming” vertex data, which
`
`renders obvious that an evaluation must take place in order to select what source data
`
`to store/maintain.3 Further, Lindholm discloses using a Resource Scoreboard that
`
`tracks the status of source registers (“storage space”) scheduled to be written during
`
`processing (i.e., destination registers). EX1005, 8:58-65. The Resource Scoreboard
`
`uses the location of each program instruction’s required source data to track whether
`
`that data is available, as well as computational resources. Id. at 8:58-60; 9:2-4,
`
`16:53-54, 17:45-46. The scheduler uses this information from the Resource
`
`3 Dr. Mangione-Smith agreed “maintain” means nothing more than “store.”
`
`EX1019, 98:7-17.
`
`11
`
`

`

`Scoreboard to determine which program instructions have their source data available
`
`and can be scheduled for execution. See, e.g., EX1003 at 14:20-30.
`
`Finally, ATI adds another limitation that the unified shader must be
`
`“performing only pixel operations until there is once again room for new vertex
`
`data.” POR 32. There is no such requirement. Dr. Mangione-Smith agreed that
`
`vertex operations could continue simultaneously with pixel operations even when
`
`there was no space available for new incoming vertex data. EX1019, 96:17-97:13.
`
`D.
`
`Claim 11: Performing Operations “At Various Degrees of
`Completion Based on Switching Between Instructions”
`As discussed supra Section II.C., claim 11 is not limited to “unfinished”
`
`operations. Nevertheless, this is disclosed in Lindholm.
`
`ATI does not dispute that Lindholm discloses multithreaded processing units
`
`that simultaneously process vertex and pixel data. EX1005, 6:11-14, 38-49;
`
`EX1006, 7:19-42. Lindholm’s multithreaded processors can switch between vertex
`
`and pixel operations by selecting different threads for execution. EX1005, 11:4-14;
`
`EX1003, ¶¶107-119; EX1018, ¶¶23-27. This includes switching instructions at
`
`various degrees of completion. For example, a POSITA would understand that Figs.
`
`7A and B show sequential or simultaneous execution of different program
`
`instructions (“Execute First Program Instructions” 720 and 765, “Execute Second
`
`Program Instructions” 725 and 770) where the threads are allocated to different
`
`sample (data) types, so that operations on the first sample type (e.g., vertex data)
`
`12
`
`

`

`occur sequentially or simultaneously with operations on the second sample type
`
`(e.g., pixel data), where either or both threads may be “unfinished.” EX1018 ¶¶28-
`
`30.
`
`“In Response To” (Claim 2)
`E.
`The Lindholm references satisfy the limitations of claim 2. Pet. 22-30. ATI
`
`contends, “Claim 2 requires a unified shader processor that executes certain pixel or
`
`vertex thread instructions ‘in response to’ receiving selected data from a data
`
`storage.” POR 33. No such requirement exists. “[G]enerate a pixel color in
`
`13
`
`

`

`response to selected data” merely means the generated pixel color will be a product
`
`of the selected data that is processed. Regardless, the ’454 patent describes how the
`
`sequencer indicates the next instruction to execute using a signal (not receipt of
`
`selected data). EX1001, 5:6-15. A POSITA would understand operations to
`
`commence based on the program or thread being run (receipt of instructions) and not
`
`caused by receiving data. EX1018, ¶38. See also EX1019, 112:15-20.
`
`ATI also contends “the space allocated in Register File 350 is for data during
`
`thread processing, not for data that is to be processed.” POR 30. No such limitation
`
`or distinction exists in the claim. EX1018, ¶43.
`
`Claim 6: Memory Separate From the “Store”
`F.
`Nothing in claim 6 requires the recited memory to be separate from the “store”
`
`recited in claim 5. The claim’s plain language includes any memory, including the
`
`already recited “store.” Dr. Mangione-Smith did not opine on whether the “store”
`
`and memory must be separate. EX1019, 122:9-125:11. Regardless, Lindholm (’685)
`
`discloses that sequencer can communicate with buffers 215, 220, Texture Cache 230,
`
`and/or local memory 140 (where instruction dispatcher 440 fetches the data), any of
`
`which would satisfy the claimed “memory” under ATI’s incorrect interpretation.
`
`EX1018, ¶52.
`
`14
`
`

`

`“Control Signal” (Claims 7 and 10) and “Arbiter” (Claim 10)
`G.
`Lindholm discloses an arbiter that provides a control signal. Pet. 37-38;
`
`EX1003, ¶¶122-123. “Thread entries,” “state data,” and “priority” are each control
`
`signals (e.g., set voltage to establish a “1” or “0”). EX1018, ¶¶58-60. Even under
`
`ATI’s dictionary definition, the voltages used to transmit “thread entries,” “state
`
`data,” or “priority” would be an “electrical signal” that can control processes. Id.
`
`IV. GROUND 2: AMANATIDES AND KOHN RENDER CLAIMS 1-11
`OBVIOUS
`A.
`Executing Operations Based on Available Space (Claims 5-10)
`And Performing Operations “Until” Storage is Available (Claims
`1, 3, 4)
`Amanatides and Kohn each satisfy claims 1 and 3-5. Pet. 53-57, 61. ATI
`
`bases its arguments on non-existent claim requirements that the unified shader must
`
`(1) “consider” or “evaluate” available space, and (2) “determine” what to execute
`
`based on that “consideration.” POR 36-43. See Section II.D (functions not required
`
`by claims, and moreover, performed by arbiter outside unified shader).
`
`Regardless, Amanatides discloses load balancing based on available space,
`
`as summarized by the Board:
`
`15
`
`

`

`ID 56-58; EX1018, ¶¶70-88. Amanatides selects vertex data only if space is
`
`available and after all RMs (pixel data) are processed. Ex. 1007, 159-160. ATI’s
`
`“consideration” and “determination” steps at least obvious. Amanatides provides
`
`flexible load balancing, where GM and RM packets can be processed out of order
`
`based on a decision of available storage space with respect to the FIFOs. EX1007,
`
`157; EX1018, ¶¶80-85.
`
`ATI’s only other argument—that the Petition did not expressly allege “what
`
`is the ‘store’” in claim 5—is wrong. POR 42. The Petition expressly identifies
`
`“DRAM, VRAM, and on-chip data cache (‘store’).” Pet. 59.
`
`B.
`
`Claim 11: Performing Operations “At Various Degrees of
`Completion Based on Switching Between Instructions”
`ATI’s arguments in Section V.B.2. of its POR are irrelevant, as explained
`
`supra Section II.C. Regardless, a POSITA would understand that pipelined
`
`16
`
`

`

`processors, such as the i860 processor described by Kohn, use pipelining to overlap
`
`execution of instructions, not of data as ATI wrongly claims. EX1018, ¶91. Kohn
`
`explains: ““The RISC core contains a pipeline consisting of four stages: fetch,
`
`decode, execute, and write.” EX1008, 17. Instructions are fetched from the
`
`instruction store, decoded into signals for the ALUs, and executed in the ALUs.
`
`EX1018, ¶91. The resulting data is written to registers. Id. The instructions move
`
`along the pipeline at various degrees of completion, not the data.
`
`Kohn discloses that the floating point and integer processor units both have
`
`multiple stages. EX1008 22-23. As different operations are selected to be loaded
`
`into the pipeline, they may be at different stages of execution. EX1018, ¶¶91-92.
`
`For example, Kohn describes performing operations in parallel, in a “dual-operation
`
`mode,” where both floating-point and scalar operations could “take advantage of the
`
`pipelining capability.” Id. A POSITA would understand, based on the combination
`
`of Amanatides and Kohn, that the functional units within each i860 processor could
`
`not only be performing vertex operations and pixel operations simultaneously, but
`
`at various degrees of completion, based on switching between instructions in the
`
`instruction cache. EX1018, ¶92.
`
`ATI’s attack on the motivation to combine Amanatides and Kohn has been
`
`addressed by Dr. Pfister. EX1003, ¶¶156-157. Dr. Pfister explained the motivation
`
`is provided, in part, by the common usage of the Intel i860 processor. Id.
`
`17
`
`

`

`Claims 2 and 5: “Selected Data”
`C.
`Claims 2 and 5 recite “selected data” from or maintained in a general purpose
`
`register block or store. However, the claims are silent on how, when, or by what
`
`component or process the data is selected. EX1018, ¶97. Other than maintaining
`
`and executing operations on the selected data, there are no requirements for any
`
`specific component to “select” the data. Id. The claims also have no limitations
`
`requiring the “transmission” of the selected data to the processor unit. The processor
`
`unit may, as would be understood by a POSITA, access or retrieve the selected data.
`
`Id., ¶97. ATI’s attempt to add “selecting” and “transmitting” limitations is
`
`unsupported. POR 44-46.
`
`D.
`
`Claims 7 and 10: “Selection Circuit” Is Within the Alleged
`“Unified Shader”
`ATI argues that the bus and FIFOs, which the Petition identifies as part of the
`
`selection circuit, are not within the alleged unified shader. POR 47. However,
`
`multiple components can be a single claimed unit. See Textron Innovations, Inc. v.
`
`American Eurocopter Corp., 498 Fed. Appx. 23, 30 (Fed. Cir. 2012). The Petition
`
`clearly identifies the bus and FIFOs as part of the claimed selection circuit, a recited
`
`component for the claimed unified shader, regardless of whether they are separate
`
`components from the G/R (i860) processor. POR 47; Pet., 59.
`
`18
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`

`

`Claims 7 and 10: “Control Signal”
`E.
`Amanatides and Kohn disclose an arbiter providing a control signal. Pet. 58-
`
`59; EX1003, ¶¶194-195.
`
`ATI disputes that Amanatides discloses providing priority information with
`
`the GM and RM packets because a “preset priority scheme” would be a waste of
`
`resources. POR 49-50. However, Amanatides expressly discloses that “low priority
`
`packets cannot get onto the bus if high priority packets are waiting.” EX1007, 158-
`
`159. A POSITA would recognize that low/high priority information must be passed
`
`to identify the packet status. EX1003, ¶¶194-196; EX1018 ¶¶116-118, 131-134.
`
`Thus, at a minimum, it is obvious that priority information must be part of the
`
`packets. Id. Further, nothing in Amanatides or Kohn suggests that these priorities
`
`are a “preset priority scheme.” Amanatides discloses a flexible graphics system, and
`
`making priorities “preset” is the opposite of being flexible. EX1018, ¶117.
`
`Second, ATI argues that priority data is not a “control signal.” As discussed
`
`supra Section IV.E, priority information can be a control signal. EX1018, ¶118.
`
`“Selection Circuit” (Claims 7 and 10) and “Arbiter” (Claim 10)
`F.
`At least the bus and FIFOs disclosed by Amanatides satisfy the claimed
`
`selection circuit. Pet. 58-59. ATI argues that the bus and FIFOs cannot satisfy the
`
`claimed “selection circuit” because they are merely transmission lines and memory.
`
`POR 51. However, a POSITA understands that FIFOs are not “merely memory”
`
`19
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`

`

`but typically include Memory/Registers, Read/Write Pointers, Control Logic (for
`
`managing pointers, determining when the FIFO is full or empty, and controlling the
`
`read and write operations based on status signals), and Status Flags (for identifying
`
`space issues). EX1018, ¶¶123-124. Similarly, a POSITA would know that a
`
`communication bus is not “merely transmission lines.” Buses operate based on
`
`specific protocols, which define the rules for data transfers and manage how devices
`
`on the bus request access to the data lines, how conflicts are resolved, and how data
`
`integrity is maintained during transmission. Id. ¶125. A POSITA would understand
`
`that the bus and FIFOs render the