`
`Transcript of Hanspeter Pfister,
`Ph.D.
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`Date: February 16, 2024
`Case: Realtek Semiconductor Corp. -v- ATI Technologies ULC (PTAB)
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`Planet Depos
`Phone: 888.433.3767
`Email: transcripts@planetdepos.com
`www.planetdepos.com
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`WORLDWIDE COURT REPORTING & LITIGATION TECHNOLOGY
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`ATI Ex. 2123
`IPR2023-00922
`Page 1 of 71
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`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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`EXAMINATION OF HANSPETER PFISTER, Ph.D. PAGE
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` By Mr. Dokhanchy 5
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` By Mr. Johnson 132
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` Exhibits - none marked in the deposition
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` UNITED STATES PATENT AND TRADEMARK OFFICE
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` BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`REALTEK SEMICONDUCTOR CORP.,
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` Petitioner,
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`v.
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`ATI TECHNOLOGIES ULC,
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` Patent Owner.
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`Case No. IPR2023-00922
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` Videotaped deposition of Hanspeter Pfister, Ph.D.
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` Boston, Massachusetts
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` February 16, 2024
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` 9:01 a.m.
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`Job No.: 524719
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`Pages: 1 - 135
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`Reported By: Alan H. Brock, RDR, CRR
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` MINTZ, LEVIN, COHN, FERRIS, GLOVSKY &
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` POPEO, P.C.
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` REZA DOKHANCHY, ESQ.
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` 3580 Carmel Mountain Road, No. 300
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` San Diego, California 92130
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` 858.314.1500
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` rdokhanchy@mintz.com
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`ALSO PRESENT:
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` Michael Safee, Videographer
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` February 16, 2024 9:01 a.m.
` P R O C E E D I N G S
` THE VIDEOGRAPHER: Here begins Media No. 1
`in the videotaped deposition of Dr. Hanspeter Pfister,
`in the matter of Realtek Semiconductor Corp. v. ATI
`Technologies ULC (PTAB), in the United States Patent
`and Trademark Office, Case No. IPR2023-00922. Today's
`date is February 16th, 2024. The time on the video
`monitor is 9:02 a.m.
` The videographer today is Michael Safee,
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`representing Planet Depos. This video deposition is
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`taking place at Orrick, Herrington & Sutcliffe LLP,
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`222 Berkeley Street, Suite 2000, Boston, Massachusetts
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`02116.
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` Would counsel please voice-identify
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`themselves and state whom they represent.
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` MR. DOKHANCHY: Reza Dokhanchy, of Mintz
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`Levin, on behalf of AMD/ATI.
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` MR. JOHNSON: Jeffrey Johnson, Baker
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`Botts, on behalf of the Realtek defendants.
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` THE VIDEOGRAPHER: The court reporter
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`today is --
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` MR. JOHNSON: I'm sorry, Realtek
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`petitioners.
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` THE VIDEOGRAPHER: The court reporter
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`PLANET DEPOS
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` A P P E A R A N C E S
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`ON BEHALF OF PETITIONER:
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` BAKER BOTTS L.L.P.
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` JEFFREY JOHNSON, ESQ.
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` 910 Louisiana Street
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` Houston, Texas 77002
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` 713.229.1234
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` jeffrey.johnson@bakerbotts.com
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`ON BEHALF OF PATENT OWNER:
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`ATI Ex. 2123
`IPR2023-00922
`Page 2 of 71
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`

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`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
`5
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`today is Alan Brock, representing Planet Depos. The
`witness will now be sworn.
` HANSPETER PFISTER, PH.D.,
`being first duly sworn or affirmed to testify to the
`truth, the whole truth, and nothing but the truth, was
`examined and testified as follows:
` EXAMINATION
`BY MR. DOKHANCHY:
` Q. Good morning, Dr. Pfister.
` A. Good morning.
` Q. I'm going to hand you copies of Exhibit 1001,
`which is the '454 patent, and 1003. And Exhibit 1003
`is your declaration in this matter; is that correct?
` A. Yes, that's correct.
` Q. If you could go to Paragraph 169 of your
`report, please: It begins on Page 81. This is where
`you begin your analysis in Ground 2 of the '454
`patent, claim 2; is that right?
` A. This is with regards to particular prior art,
`and it seems to be the combination of Amantides and
`Kohn.
` Q. Okay. And in this section that starts at
`Paragraph 167, you're addressing the claimed unified
`shader of the '454 patent; right?
` A. That's correct, with regards to Amantides and
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`And so the i860 processor is basically the processor
`in the Amantides system. So it does more, you know,
`than just G/R processing.
` Q. The thing you're calling the G/R unit, that's
`a processor; right?
` MR. JOHNSON: Objection, form.
` A. Well, I call it a unit because I think that's
`the term that Amantides uses. But if you could hand
`me the Amantides reference, I can check that.
` Q. Sure. I'm going to hand you Exhibit 1007,
`which is the Amantides reference.
` And I can point you to a particular place
`if that would be helpful.
` A. I found it. So in Amantides, Page 7 --
`sorry, Page -- well, which page should I use? I guess
`I use the Bates Page 7?
` Q. We can use 157. That's fine.
` A. Page 157, on the bottom of the left column,
`he describes these G/R units as the processors, or the
`processor. So he uses the word "processor." You were
`correct.
` Q. So looking at Figure 3, there are multiple
`G/R units. Those are, as we just saw, processors.
`Each G/R unit is a processor; right?
` A. That is correct.
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`Kohn.
` Q. And we see on the next page, 158, around the
`middle of the page it says, "After exploring several
` Q. Okay. And if you continue onto the next
`DSP microprocessors, we decided on the Intel i860";
`page, in Paragraph 169, your allegation is that
`right?
`Amantides termed the unified shader unit the G/R unit.
` A. Yes, that is correct.
`Do you see that?
` A. Yes, correct.
` Q. And so the authors are stating that the Intel
`i860 is the processor selected as the G/R processor;
` Q. And so your allegation is that the Amantides
`right?
`reference discloses a unified shader in the form of
` A. Let me quickly check. I want to make sure
`the G/R unit; right?
`that we are still using the -- or Amantides is still
` A. Yes, the G/R unit or units, plural.
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`using the term "processor" in the same way. If you
` Q. You didn't say units plural in your report.
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`don't mind, I'll quickly read that paragraph above.
` A. That's correct. I would say it's either the
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`singular or it's the collection of.
` Q. Yes.
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` A. I think it's a little ambiguous, just in the
` Q. In your report you said singular; correct?
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`sense that Amantides doesn't actually say that the
` A. That is correct. I used the singular in the
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`Intel i860 is just the G/R processor. The reason I
`report, but I may have, you know, missed that
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`mention this is because, as I said earlier, in the
`particular point. But I think either one is fine.
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`system diagram in Figure 4 the i860 appears as, you
` Q. And your -- withdrawn. The Amantides
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`know, the only processor within the graphics
`reference states that the G/R unit is implemented as
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`processing unit, except for the host. So it
`an Intel i860 processor; right?
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`presumably will also have to do some other things.
` A. That is correct.
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`And that's the only reason I bring this up.
` Q. So the G/R --
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` A. So just to be clear: You know, I'm referring
` Q. Okay. So looking at Figure 4, are you saying
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`now to Figure 4 on Page 83 of my declaration, and
`that the G/R unit is coextensive with the i860, larger
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`Figure 4 shows the actual system diagram of Amantides.
`than the i860, or smaller than the i860, or something
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`PLANET DEPOS
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`ATI Ex. 2123
`IPR2023-00922
`Page 3 of 71
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`

`

`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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`else?
` MR. JOHNSON: Objection, form.
` A. I don't know what you mean by "larger than,"
`"smaller than," whatever terms you used.
` Q. Sure. So looking at Figure 4, what
`components would you consider parts of the G/R unit?
` A. Well, the G/R unit is clearly the i860,
`within the i860, because that's the, you know,
`one-to-one mapping to the previous diagram.
` Q. Okay. So that's what I meant by "smaller
`than": within.
` What else, if anything, is in the i860
`besides the G/R processor?
` A. Well, I wouldn't say, you know, "is within."
`I'm not sure what you mean by that term.
` Q. Well, that's the word you used. So I'm using
`your word.
` A. Oh, sorry. I said the G/R unit, you know, is
`basically within the i860. I mean, the i860 is -- is
`the G/R unit. It may also function as, you know, sort
`of --
` You know, it's a subtle distinction,
`because the G/R unit actually can also do some other
`processing. I was talking myself a little bit into a
`corner here, because I'm thinking, besides the
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` Q. Sure. I'm just looking at the claim
`language. We can talk about your mapping in a second.
`But my question simply is, "claim 2 requires a
`sequencer that maintains instructions; correct?
` A. Yes.
` Q. And Paragraph 178 is where you discuss your
`allegations of why Amantides and Kohn disclose the
`claimed sequencer; is that correct?
` MR. JOHNSON: Objection, form.
` Q. I can just direct you to the first sentence.
` A. Yeah, I see the paragraph. What I'm actually
`saying is that both Amantides and Kohn disclose the
`claimed sequencer.
` Q. Okay. And in terms of what you identify, you
`say at the bottom -- the end of Paragraph 178, "The
`on-chip cache together with the memory unit comprise
`the claimed sequencer and sequencer circuitry of the
`'454 patent." Correct?
` A. So I think in order to understand this, we
`need to look at Kohn, because Kohn actually is
`referenced here, if I'm not mistaken, Exhibit 1008.
` Q. Well, let's just start with what you wrote.
`You wrote, "The on-chip cache together with the memory
`unit comprise the claimed sequencer and sequencer
`circuitry of the '454 patent." Did I read that
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`geometry and the rendering processing, there is some
`correctly?
` A. You read that correctly.
`other processing happening. But that could be all
`part -- I mean, that is actually in Amantides all part
` Q. So let's talk about what you cite here. So
`of the G/R unit.
`you cite -- in this paragraph first you say,
` So, you know, let's step back. I'm going
`"Amantides at 157 to 158." Do you see that?
` A. Sorry, say that again. I'm sorry.
`to change -- basically, in my declaration, as I said,
`I think, the G/R unit is the i860.
` Q. I'm looking at the first citation in
` Actually, if you don't mind, I'll quickly
`Paragraph 178.
` A. Oh, yeah.
`check my declaration. I want to make sure I have that
`statement in here before I say I say that.
` Q. That's Amantides at Page 157 to 158; correct?
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` A. That's the citation. That's not all we just
` Yeah, actually, I do say that.
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`talked about, just to be clear.
` Q. Okay.
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` A. So I say in Paragraph 172 on Page 892, "The
` Q. That's fine. I just want to -- we're going
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`claimed processor unit can be interpreted as each
`to go now look at that citation.
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` A. Okay, yeah.
`G/R," and then in parentheses, you know, the i860
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`processor.
` Q. And then you have a quote saying, "As well,
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`program space needs to be larger," dot dot dot. Let's
` Q. And let's talk about claim 2 of the '454
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`go to that quote. Okay?
`patent. If you can open that up, please, or you may
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` A. Okay.
`just remember it. But there is a sequencer claimed in
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` Q. That's on Page 158 of Amantides. If you
`the i860 -- excuse me. Withdrawn. Claim 2 requires a
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`could go there, please. So this is one of your
`sequencer that maintains instructions. Do you see
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`citations for why Amantides discloses the sequencer,
`that?
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` A. So claim 2 has several subclaims. I think
`which, as we just talked about, needs to maintain
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`we -- in my declaration I labeled them with A, B, C.
`instructions. Correct?
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` A. The sequencer needs to maintain instructions,
`So I think you're referring to the third or the C?
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`ATI Ex. 2123
`IPR2023-00922
`Page 4 of 71
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`

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`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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`correct.
` Q. So where in this citation that you quoted,
`Page 158 -- where do you see a disclosure of storing
`instructions?
` A. I'm actually trying to find it on 157-158.
` Q. So the quote that you cited is about Line 8
`on 158. It starts "As well."
` A. Oh, yeah. Yeah, I think the relevant piece
`of that quote, or of that, you know, section in
`Amantides is that sentence at the end in my
`declaration, Paragraph 178, where I'm quoting. And in
`the sentence the quote says, "To get back to speed, we
`wanted the processor to have an on-chip cache." So
`that's what I'm referring to as the on-chip cache in
`Amantides.
` Q. Where does that say that what you're calling
`the sequencer stores instructions?
` A. If we look at Amantides, Page 158 -- also
`where my quote starts in my declaration: "As well,
`program space needs to be larger," et cetera.
`"Program space would be understood by a POSITA to mean
`memory for programs," and it's very clear that that
`includes instructions. So it would be clear to a
`POSITA that that program space which is stored in the
`on-chip cache is part of that cache, meaning the
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`in the DRAM.
` Q. Does Amantides say one way or another whether
`the DRAM stores instructions?
` MR. JOHNSON: Objection, form.
` A. So, you know, you're directing me to this one
`paragraph in Amantides. And so to answer your
`question truthfully, I would have to look at, I think,
`the rest of the reference. You know, I don't recall.
`And I'd be happy to look through it if you like.
` Q. Yeah, why don't do you that. It's only
`discussed, I think, on that page, but you can feel
`free to correct me and look for the word "DRAM"
`throughout or whatever you want to look for.
` But my question is: Does Amantides say
`whether or not the DRAM stores instructions?
` MR. JOHNSON: Objection, form.
` A. So I think actually even within that
`paragraph that you directed me to, you know, if you
`read this carefully, Amantides points out that,
`"Program space needs to be larger as each processor
`does more work." Right? So he's pointing out the
`fact that, as we're combining the G/R into this one
`processor, it needs to do more work, and that means it
`also needs more program space. And then he talks
`about using DRAM.
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` So I think it's clear from just inferring
`instructions are stored in that cache.
`this that he assumes that the program space will also
` Q. Okay. And it says originally, before
`be stored in the DRAM, since he points out that it can
`considering the on-chip cache, there was a possibility
`be large -- right? And a cache, as I mentioned
`of storing program space in SRAM or DRAM; is that
`before, is typically a temporary storage and is
`right?
`typically on or, you know -- I would say, yeah,
` A. Well, what Amantides actually points out is
`typically not large enough to hold all of the program
`that he or they wanted to eliminate the need for SRAM
`space.
`and DRAM. So I guess you could say an alternative
` So I think it's reasonable to say that,
`design would have been to store the instructions in
`yes, Amantides does say that the program space is
`SRAM and DRAM, but that's not --
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`stored in the DRAM, because that's large.
` I'm sorry, in SRAM, sorry. I misquoted, I
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`think. What he actually says or they say is that "we
` Q. And you see in claim 2 there's a separate
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`wanted to eliminate the need for SRAM, and use DRAM
`requirement from the sequencer, and that is a general
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`instead."
`purpose register block for maintaining data? Do you
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` And now I lost your question. I'm sorry.
`see that?
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` A. Yes, the claim says that a sequencer is
` Q. Well, my question is: Does the DRAM in
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`Amantides store instructions?
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`further down that, you know, that depicts a
` A. It may also store instructions, simply
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`calculation of operations on the selected data
`because, you know, a cache is, if you will, kind of a
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`maintained in the general purpose register block, is
`temporary storage and typically limited in space. So,
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`part of that, yes.
`you know, it may not hold the whole program. And so
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`it is possible.
` Q. And could you actually look at the previous
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` But Amantides does actually not disclose
`page at the bottom. It says "a unified shader,
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`that. I think for a POSITA it would seem reasonable
`comprising a general purpose register block for
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`to say that it's possible that there are instructions
`maintaining data"; right?
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`ATI Ex. 2123
`IPR2023-00922
`Page 5 of 71
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`

`

`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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` A. I think the claim doesn't really specify
`that. Also, you know, you're mixing the claim and
`Amantides; right? So could you please repeat the
`question? Because you talked about the claim language
`and then you mentioned DRAM, so I got a little
`confused.
` Q. Yeah. So assuming that the DRAM maintains
`instructions --
` A. Yes.
` Q. -- in your view, that would satisfy the
`requirement for a sequencer to maintain instructions;
`correct?
` A. It doesn't say maintaining instructions. I'm
`sorry.
` Oh, sorry, the sequencer maintaining
`instructions? You're switching from the register?
` Q. I'm taking a little bit more piece by piece,
`because it seemed like you were getting a little
`confused.
` So assuming that the DRAM stores
`instructions, your view is that it can then be a
`sequencer that maintains instructions; correct?
` MR. JOHNSON: Objection, form.
` A. So, you know, I want to reiterate what my
`opinion is in my declaration, that the sequencer in
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` A. Yes, that is correct.
` Q. And so that's a separate component from the
`sequencer, which is for maintaining instructions;
`right?
` MR. JOHNSON: Objection, form.
` A. The claim actually doesn't say "separate."
`It says there's a general purpose register block for
`maintaining data. "Data" is a very general term. It
`could include instructions.
` Q. Okay. So your read of the '454 patent is
`that instructions can be considered to be data; is
`that right?
` MR. JOHNSON: Objection, form.
` A. I didn't say that. I just pointed out that
`in claim 2 -- you know, you have to go claim by claim,
`and you directed me to claim 2. So in claim 2 there
`is a sentence that says "a general purpose register
`block for maintaining data." And so it doesn't say
`what that data is in claim 2. So I think it's
`undetermined, and it may include instructions.
` Q. Okay. So when you were looking in the
`Amantides reference for data and instructions, were
`you using the interpretation that "instructions" can
`satisfy the requirement for data?
` A. I looked at each claim in turn, as you can
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`tell from my declaration. So I cannot answer this
`question, because it really depends on the claim and
`actually even on the part of the claim. And I
`think --
` Yeah, if we can talk about the specific
`claim, I'd be happy to answer that.
` Q. My question was about claim 2.
` A. Okay.
` Q. So in claim 2, if one were to identify
`maintaining instructions, would that satisfy the
`requirement for maintaining data?
` MR. JOHNSON: Objection, form.
` A. I'm sorry, I didn't understand the question.
`When you say -- what did you mean --
` Q. Sure. So we just talked about how your
`opinion is that the DRAM stores instructions; right?
` A. Possibly.
` MR. JOHNSON: Objection, form.
` A. Possibly.
` Q. Let's assume that it does. Okay? Let's say
`the DRAM does store instructions. Are you with me?
` A. I'm assuming that, okay.
` Q. Does that satisfy the claim requirement for a
`general purpose register block maintaining data?
` MR. JOHNSON: Objection, form.
`
`Amantides is the on-chip cache together with the
`memory management unit -- right? -- for claim 2. And
`so for claim 2 my opinion is that the on-chip cache is
`the one that maintains the instructions.
` Q. Okay. By virtue of maintaining instructions,
`does the on-chip cache also maintain data, as claimed
`in claim 2 of the '454 patent?
` MR. JOHNSON: Objection, form.
` A. Well, the claim doesn't actually say
`"maintain data." The sequencer only --
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` Q. No, no, stop. "General purpose register
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`block for maintaining data."
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` A. Oh, I'm sorry. You're going back there.
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`Sorry.
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` Q. You said the on-chip cache stores
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`instructions; right?
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` A. No, I said the on-chip cache fulfills -- yes,
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`it does store instructions, correct.
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` Q. Okay. By storing instructions, does the
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`on-chip cache also store data?
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` MR. JOHNSON: Objection, form.
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` A. I'm actually quoting Kohn here. So I would
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`have to look at Kohn --
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` Q. We're talking about Amantides, your opinion
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`in Paragraph 178 is Amantides. You say, "The on-chip
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`ATI Ex. 2123
`IPR2023-00922
`Page 6 of 71
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`

`

`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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`cache stores instructions." Right?
` A. Well, to be clear, the paragraph starts by
`saying, "Amantides and Kohn." So I'm talking about
`both references.
` Q. Okay.
` A. And actually, the sentence we're talking
`about quotes Kohn, which I'm assuming is Exhibit 1008.
` Q. Right. Kohn -- the memory management unit is
`what you're talking about -- right? -- in Kohn, 1008?
` A. I'm not sure. I would have to look at the
`reference. If you would hand it to me, I can take a
`look.
` Q. Let's just talk about the on-chip cache.
`Which reference are you relying on for that?
` A. You know, the on-chip cache is mentioned in
`Amantides, but it's also mentioned in Kohn. And since
`you're starting to ask me questions about data and
`instructions, I think we will find more details in
`Kohn.
` Q. Okay, well, let's start with the previous
`sentence: "Amantides features an on-chip cache for
`storing program instructions." Right? That's your
`opinion?
` A. Yes, because it says --
` Q. I don't need an explanation.
`
`6 (21 to 24)
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`23
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`Jeff.
` Q. Dr. Pfister, I'm not asking about other
`components. I'm talking about the on-chip cache that
`your opinion states stores instructions. Okay?
` A. Yes.
` Q. Are you clear?
` A. Yes.
` Q. Does the on-chip cache therefore also
`maintain data as required by claim 2, yes or no?
` MR. JOHNSON: Objection, form.
` A. I don't know. I have to look at, you know,
`more details in Kohn to really answer that question,
`because I'm assuming Kohn will describe it at some
`point, what the on-chip cache actually stores.
` Q. Okay. Can you tell me, looking at claim 2,
`whether instructions are data? Yes or no?
` MR. JOHNSON: Objection, form.
` A. I'm not sure what you mean by that question,
`whether instructions are data.
` Q. Let's say I have an instruction.
` A. Yeah.
` Q. Give me an example of an instruction?
` A. "At."
` Q. At what?
` A. Okay, at register 1 with register 2 and store
`
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`the results in register C instruction.
` A. Okay, yes.
` Q. Okay, that's the instruction.
` Q. That's your opinion.
` A. Yeah.
` A. Yes.
` Q. Is that data in claim 2?
` Q. That on-chip cache --
` A. Maybe among other things.
` MR. JOHNSON: Objection, form.
` A. No, probably not, because it says in the
` Q. Okay. Because the on-chip cache stores
`claim that the calculations, i.e., if you will, the,
`instructions, does it also satisfy the requirement for
`you know, operations, the instructions, are on the
`maintaining data in claim 2?
`selected data maintained in the general purpose
` MR. JOHNSON: Objection, form.
`register block. So I think the claim actually means
` A. Well, there are several other register blocks
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`different data actually -- you know, vertex and pixel
`in Amantides --
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`data, or other types of data, that would be used for
` Q. I'm not asking about other register blocks.
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`the calculations.
` MR. JOHNSON: Y'all have got to stop
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` Q. When claim 2 says "data," it means something
`talking over one another. You let him finish his
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`other than instructions; correct?
`sentences --
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` A. Yeah, I think, looking at the claim language,
` MR. DOKHANCHY: I'll ask my questions
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`that's a good interpretation. It says, you know, the
`however I want.
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`data is basically used for the operations, and data is
` MR. JOHNSON: If you interrupt him again.
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`stored as a response to the, you know, operations. So
`I'll just keep stopping you. Let him finish his
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`there seems to be in that claim a distinction, and --
`answers.
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` You know, but it doesn't actually say what
` MR. DOKHANCHY: He needs to answer the
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`data is. So there's still a slight ambiguity. I
`actual question.
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`don't think it necessarily precludes it. But reading
` MR. JOHNSON: That's fine. But let him
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`the claim, I think you could assume that, yes, there
`finish, and then you can ask another question.
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`is a difference between -- that data is not
` MR. DOKHANCHY: I'll do it however I want,
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`ATI Ex. 2123
`IPR2023-00922
`Page 7 of 71
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`

`

`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
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`instructions necessarily.
` Q. All right, let's go to claim element 2[a],
`which is starting at Paragraph 170 of your report,
`Page 82.
` A. Sorry, we're going to my report?
` Q. Yes, back to your report, Page 82, Paragraph
`170.
` A. Yes.
` Q. This is regarding the, as it says in the
`heading, the general purpose register block element of
`claim 2 for the Amantides and/or Kohn references;
`right?
` A. Yes.
` Q. One of the requirements of the general
`purpose register block is that it maintains data --
`correct? -- in claim 2?
` A. Yes.
` Q. And you say -- well, first let me ask: What
`are the items or -- what is the item or what are the
`items that you claim are the general purpose register
`block in Amantides?
` A. So in this section -- sorry, I lost the
`beginning. Here. In this section in my declaration
`starting at Paragraph 170, I identify several units.
`One is the DRAM, one is the input FIFO associated with
`26
`each processor. And then there's also mention of an
` Q. So the data that you're pointing to under
`on-chip cache. And I'm referring again to Kohn
`that theory is textures and geometric models; is that
`here -- again, assuming that Exhibit 1008 is Kohn --
`right?
` A. That's one example.
`showing the data cache.
` So presumably the data cache in Kohn or
` Q. Okay. What else is there?
` A. I would have to look at Amantides, what else
`the on-chip cache in Amantides is this -- another
`they mention.
`memory that comprises together the general purpose
`register block.
` Q. Sure. Why don't you look at that and tell me
`what types of data you contend are stored in DRAM.
` Q. Do you allege that the bus that you mention
` A. By the way, did I mention -- if you don't
`on Page 83 -- is that part of the general purpose
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`mind, I'm not going to answer your question, but I
`register block?
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`would like to point out: I missed maybe something
` A. No. I think -- well....
`12
`earlier. I'm just realizing now. It also mentions
` I don't think so. I think the bus is
`13
`VRAM, which could also be considered part of the
`basically used to move packets around. So, in other
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`register block.
`words, it's not used for storage.
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` However, you know, it depends on the
` Q. We'll get back to that question.
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` A. I just wanted to correct myself.
`actual implementation of the bus. I have certainly
`17
`seen some types of buses that include some local
` Q. Let me get your allegations correctly. So
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`storage. So there might actually be some registers,
`your belief is that the components that could make up
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`potentially, associated with the bus.
`the register block are the DRAM, potentially the bus,
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` So it's a little unclear where the bus
`the input FIFO, the VRAM, and the on-chip cache of
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`starts and where the FIFO ends, so to speak, if you
`Amantides and possibly Kohn; is that right?
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` A. Correct, and possibly other registers that
`know what I mean.
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`are not mentioned here. But those are the ones that
` Q. Okay. So let's talk about the DRAM. You
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`he mentions, yes, correct.
`said earlier potentially the DRAM stores instructions;
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`right?
` A. Yes, I said that.
` Q. And now we're talking about storing data.
`Where does Amantides say that the DRAM stores data?
` A. So in the section I quote here in Paragraph
`170 in my declaration, Amantides says, "The new design
`would require more memory for each processor. A lot
`of memory is needed as textures and geometric models
`are space intensive." So then he goes on talking
`about DRAM. So that's part of the data that Amantides
`mentions that is stored in the DRAM.
` Q. Well, the part you skipped is about program
`space, which you said is instructions; right?
` A. Yes.
` Q. So what it's talking about there is, as we
`discussed earlier, potentially storing instructions in
`DRAM; right?
` A. Yes.
` Q. Where does it say anything about storing data
`in DRAM?
` A. In the sentence before. So it says, "A lot
`of memory is needed as textures and geometric models,
`if they are stored locally, are space intensive." So
`that's the data. And then he continues "as well," and
`then instructions. So it's both.
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`ATI Ex. 2123
`IPR2023-00922
`Page 8 of 71
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`

`

`Transcript of Hanspeter Pfister, Ph.D.
`Conducted on February 16, 2024
`29
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`8 (29 to 32)
`
`31
` So the geometry messages include geometry,
`which is graphics primitives; I would say probably
`also includes what he calls earlier graphical models.
` Yeah, that's what I'm reading here.
` Q. Is a geometry message an instruction?
` MR. JOHNSON: Objection, form.
` A. Are you referring to a particular passage in
`my declaration or in Amantides or in a claim? What
`are you referring to?
` Q. So claim 2 requires instructions; right?
` A. Yes.
` Q. Is a -- withdrawn. Is a geometry message an
`instruction in the meaning of claim 2?
` MR. JOHNSON: Objection, form.
` A. So a message, you know, is not the same thing
`as an instruction. A message actually has a
`particular format. It may include instructions, but
`it certainly has other things with it. So just by
`that observation alone, I would say no, messages,
`geometry messages, are not instructions.
` Q. And you said it may include instructions.
`Are you abl