III III a IIOI OlD IIO 1101 100 1101 OlD 110 mil uui lull lulu II OI IIi
`
`US 20060277355A1
`
`(19) United States
`12) Patent Application Publication (10) (cid:9)
`(43) Pub. Date: (cid:9)
`en(cid:127)uer.y et al. (cid:9)
`
`2006/0277355
` uea^.].EOUb
`
`
`(54) CAPACITY-EXPANDING MEMORY DEVICE
`
`(76) Inventors: Mark Ellsberry, Santa Clara, CA (US);
`Paul Sweere, Irvine, CA (US); Michael
`Sansur, Costa Mesa, CA (US); Grant
`Stockton, Fountain Valley, CA (US)
`
`Correspondence Address:
`LOZA & LOZA
`6285 EAST SPRING STREET, # 327N
`LONG BEACH, CA 90808 (US)
`
`(21) Appl. No.: (cid:9)
`
`11/142,989
`
`(22)
`
`Filed: (cid:9)
`
`Jun. 1, 2005
`
`Publication Classification
`
`(51) Int. Cl.
`G06F 13/00 (cid:9)
`
`(2006.01)
`
`(2006.01)
`G06F 12/06 (cid:9)
`(52) (cid:9) U.S. Cl . (cid:9)
`................................................. 711/5; 711/154
`
`(57) (cid:9)
`
`ABSTRACT
`
`The invention relates to a device, system, and method for
`expanding the memory capacity of a memory module. A
`control unit and memory bank switch are mounted on a
`memory module to selectively control write and/or read
`operations to/from memory devices communicatively
`coupled to the memory bank switch. By selectively routing
`data to and from the memory devices, a plurality of memory
`devices may appear as a single memory device to the
`operating system. That is, the invention expands the addres-
`sable memory banks on a module by making two smaller-
`capacity memory devices emulate a single higher-capacity
`memory device.
`
`, 100
`
`i/o
`104 Controller
`
`Processing
`Unit
`
`102 (cid:9)
`
`110 Memory
`
`106
`
`108
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 1
`
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 1 of 18
`
`US 2006/0277355 Al
`
`220
`Re istered Address, CMD, Clocks
`
`/200
`
`nk3 (cid:9)
`
`Bank2
`
`Bank3 (cid:9)
`
`216
`
`Bank 1
`
`H12
`
`228 218 (cid:9)
`DDR DRAMÜ (cid:9) Bank 0
`Bank 1 (cid:9)
`2
`214
`226
`g22
`m m (cid:9)
`
`Qs
` o p
`ort B
`
`234
`
`o Q Q
`o o °
`(cid:9) 2 a 236
`o o m o o
`Port A
`Port B
`
`o 0 0 (cid:9)
`
`Switch ASIC
`
`208
`
`206
`
`PLL
`
`238
`
`232
`
`a
`
`219 0
`
`fit21
`
`00
`0
`C^
`
` Control Bus Clocks
`
`230 a
`
`DIMM Interface
`
`Fig. 2
`
`210
`
`Con rol
`ASI
`
`Ana
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 2
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 2 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`302
`
`SYSTEM (cid:9)
`ADDRESS/CMD (cid:9)
`
`> D Q (cid:9)
`
`/ 300
`
`BANK A
`"ADDRESS/
`CMD (cid:9)
`
`220
`
`BANK B
`ADDRESS/
`CMD
`
`ADDRESS/CMD
`DECODE (cid:9)
`
`304
`
`DDR 1 /DDR2# I (cid:9)
`DRAM_ TYPE <: > (cid:9)
`CTRL/DATA#
`
`I (cid:9)
`
`CONFIG
`DECODE 306
`
`BANK SWITCH (cid:9)
`STATE MACHINE 308 (cid:9)
`
`CONTROL BLOCK
`
`BANK SWITCH
`CON
`210
`
`CK/CK
`
`PLL
`
`I (cid:9)
`
`DC-DC
`
`Fig. 3
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 3
`
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 3 of 18
`
`US 2006/0277355 Al
`
`D Q (7:0)/
`DQS <
`
`230 (cid:9)
`
`402
`
`EAD
`
`DQ
`WRITE
`
`404
`
`EAD
`
`D QIN
`
`WRITE
`
`READ/WRITE
`LOGIC (cid:9)
`
`406
`
`CONFIG
`DECODE (cid:9)
`
`OCD STATE
`MACHINE (cid:9)
`
`408
`
`410
`
`CONTROL BLOCK
`
`/400
`
`DQ (7:0)/DQS
`PORT A
`
`234
`
`P DQ (7:0)/DQS
`
`PORT B
`
`236
`
`DDRI /DDR2#
`DRAM _TYPE <:>
`CTRL/DATA#
`
`BANK SWITCH
`CONTROL
`
`DC-DC (cid:9)
`
`PLL (cid:9)
`
`CK/CK#
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 4
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 4 of 18
`
`US 2006/0277355 Al
`
`504
`
`DDR2 DDR2 DDR2 'DDR2 DDR2
`FBGA FBGA FBGA FBGA FBGA
`512
`512
`512
`512
`
`Th 512
`DDR2 DDR2 DDR2 DDR2 DDR2
`512 FBGA
`FBGA
`FBGA
`FBGA
`FBGA
`512
`512
`512
`512
`512
`
`1 B
`
`1500
`
`DDR2 DDR2 DDR2 DDR2
`FBGA FBGA FBGA FBGA
`512
`512
`512
`512
`
`514
`
`PLL
`
`DDR2 DDR2 DDR2 DDR2
`FBGA FBGA FBGA FBGA
`512
`512
`512
`512
`
`510
`
`s.
`
`(cid:127)
`
`100
`
`110 Memory
`
`106
`
`108
`
`vo
`104 Controller
`
`J
`
`J Processing
`Unit
`10`21 (cid:9)
`
`Fig. 1
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 5
`
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 5 of 18
`
`US 2006/0277355 Al
`
`DDR2 DDR2 DDR2 DDR2 DDR2
`CSP
`CsP
`CsP
`CSP
`CSP
`512
`512
`512
`512
`512
`
`DDR2 DDR2 DDR2 DDR2 DDR2
`CsP
`CSP
`CsP
`CSP
`CsP
`512
`512
`512
`512
`512
`
`3
`3
`(cid:127) .oaaaoaaoiiooaioaaiaaiiia(cid:127),
`
`/ 600
`
`PLL
`
`DDR2 DDR2 DDR2 DDR2
`CsP
`CsP
`CsP
`CsP
`512
`512
`512
`512
`
`DDR2 DDR2 DDR2 DDR2
`CSP
`CsP
`CsP
`CSP
`512
`512
`512
`512
`
`.M.
`
`01
`
`Fig. 6
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 6
`
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 6 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`Configuration
`
`Primary Address
`Space
`
`RC Mode
`INVERT
`
`Mode
`
`DDR 1,2 X 256M
`(x4)
`
`BA Oh - 3h
`Row 0000h - 1 FFFh
`Column 000h - FFFh
`
`X
`
`COLUMN
`
`PHY
`Bank
`Select
`
`COL
`A(1 2)
`
`DDR 1,2 X 256M
`(x8)
`
`BA Oh - 3h
`Row 0000h - 1 FFFh
`Column 000h - 7FFh
`
`X
`
`COLUMN
`
`COL
`A(11)
`
`DDR 1,2 X 512M
`(x4)
`
`BA Oh - 3h
`Row 0000h - 3FFFh
`Column 000h - FFFh
`
`X
`
`ROW
`
`ROW
`A(13)
`
`Secondary Address
`Space
`
`BA Oh-3h
`Row 0000h-1 FFFh
`Column 000h-7FFh
`
`BA Oh - 3h
`Row 0000h-1 FFFh
`Column 800h-FFFh
`
`BA Oh - 3h
`Row 0000h-1 FFFh
`Column 000h-3FFh
`
`BA Oh - 3h
`Row 0000h-1 FFFh
`Column 400h-7FFh
`
`BA Oh - 3h
`Row 0000h-1 FFFh
`Column 000h-FFFh
`
`BA Oh - 3h
`Row 2000h-3FFFh
`Column 000h-FFFh
`
`Fig. 7A
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 7
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 7 of 18
`
`US 2006/0277355 Al
`
`a (cid:9)
`
`b
`
`n n n Cf
`
`DDR 1,2 X 512M
`(x8)
`
`BA Oh - 3h
`Row 0000h -3FFFh
`Column 000h - 7FFh
`
`X
`
`ROW
`
`ROW
`A(13)
`
`DDR 1,2 X 1 G
`(x4)
`
`BA Oh - 2h
`Row 0000h - 7FFFh
`Column 000h -FFFh
`
`DISABLE
`
`ROW
`
`ROW
`
`A(14)
`
`BA Oh -2h
`Row 0000h - 3FFFh
`Column 000h -1 FFFh
`
`ENABLE
`
`COLUMN
`
`COL
`A(13)
`
`BA Oh-3h
`Row 0000h-1 FFFh
`Column 000h-7FFh
`
`BA Oh - 3h
`Row 2000h-3FFFh
`Column 000h-7FFh
`
`BA Oh - 3h
`Row 0000h-3FFFh
`Column OOOh-FFFh
`
`BA Oh - 2h
`Row 4000h-7FFFh
`Column 000h-FFFh
`
`BA Oh -2h
`Row 0000h-3FFFh
`Column 000h-FFFh
`
`BA Oh - 3h
`Row 0000h-3FFFh
`Column 1 000h-1 FFFh
`
`^l (cid:9)
`
`1 (cid:9)
`
`k (cid:9)
`
`I (cid:9)
`
`m (cid:9)
`
`n
`
`Fig. 7B
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 8
`
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 8 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`h (cid:9)
`
`i
`
`BA Oh - 3h
`Row 0000h - 7FFFh
`Column 000h - 7FFh
`
`BA Oh - 3h
`Row 0000h - 3FFFh
`Column 000h - FFFh
`
`BA Oh - 3h
`Row 0000h - 3FFFh
`Column 000h - 7FFh
`
`DDR 1,2 X 1G
`
`(x8)
`
`DDR 11,2 X 256M
`(x4)
`
`n n n n (cid:9)
`BA Oh - 3h
`BA Oh - 3h
`BA Oh - 3h
`
`DISABLE
`
`ROW
`
`ROW
`A(14)
`
`ENABLE
`
`COLUMN
`
`COL
`A(12)
`
`X
`
`ROW
`
`ROW
`A(13)
`
`n
`
`Row 0000h-3FFFh
`Column 000h-7FFh
`
`Row4000h-7FFFh
`Column 000h-7FFh
`
`Row 0000h-3FFFh
`Column OOOh-7FFh
`
`BA Oh (cid:9) 3h
`Row 0000h-3FFFh
`Column 800h-FFFh
`
`BA Oh - 3h
`BA Oh - 3h
`
`Row 0000h-1 FFFh
`Column 000h-7FFh
`
`Row 2000h-3FFFh
`Column 000h-7FFh
`
`q (cid:9)
`
`r
`
`s
`
`t
`
`u
`
`Fig. 7C
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 9
`
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 9 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`r
`
`p (cid:9)
`
`(S)
`
`T
`
`DDR II, 2 X 256M
`(x8)
`
`BA Oh - 3h
`Row 0000h -3FFFh
`Column 000h - 3FFh
`
`X
`
`ROW
`
`ROW
`A(13)
`
`DDR 11,2 X 512M
`(x4)
`
`BA Oh - 7h
`Row 0000h - 3FFFh
`Column 000h - 7FFh
`
`X
`
`BANK
`
`BANK
`A(2)
`
`DDR 11 ,2 X 512M
`(x8)
`
`BA Oh - 7h
`Row 0000h - 3FFFh
`Column 000h - 3FFh
`
`X
`
`BANK
`
`BANK
`A(2)
`
`(c'
`
`Fig. 7D
`
`BA Oh - 3h
`Row 0000h-1 FFFh
`Column 000h-3FFh
`
`BA Oh - 3h
`Row 2000h-3FFFh
`Column 000h-3FFh
`
`BA Oh - 3h
`Row 0000h-3FFFh
`Column 000h-7FFh
`
`BA 4h -7h
`Row 0000h-3FFFh
`Column 000h-7FFh
`
`BA Oh-3h
`Row 0000h-3FFFh
`Column 000h-3FFh
`
`BA 4h -7h
`Row 0000h-3FFFh
`Column 000h-3FFh
`
`F
`
``V
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 10
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 10 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`nB (cid:9)
`
`(c) (cid:9)
`
`nD (cid:9)
`
`(E) (cid:9)
`
`nF (cid:9)
`
`n
`
`DDR 11,2 X 1G
`(x4)
`
`BA Oh - 7h
`Row 0000h - 7FFFh
`Column 000h - 7FFh
`
`X
`
`ROW
`
`DDR II, 2 X 1 G
`(x8)
`
`BA Oh - 7h
`Row 0000h - 7FFFh
`Column 000h - 3FFh
`
`X
`
`ROW
`
`ROW
`A(14)
`
`ROW
`A(1 4)
`
`BA Oh - 7h
`Row 0000h - 7FFFh
`Column 000h - FFFh
`
`DISABLE
`
`COLUMN
`
`COL
`A(12)
`
`BA Oh - 7h
`Row 0000h-3FFFh
`Column 000h-7FFh
`
`BA Oh - 7h
`Row 4000h-7FFFh
`Column 000h-7FFh
`
`BA Oh - 7h
`Row 0000h-3FFFh
`Column 000h-3FFh
`
`BA Oh - 7h
`Row 4000h-7FFFh
`Column 000h-3FFh
`
`BA Oh - 7h
`Row 0000h-7FFFh
`Column 000h-7FFh
`BA Oh - 7h
`Row 0000h-7FFFh
`Column 800h-FFFh
`
`Qj)
`
`U
`
`U (cid:9)
`Fig. 7E
`
`L (cid:9)
`
`M (cid:9)
`
`N
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 11
`
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 11 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`O (cid:9)
`
`n (cid:9)
`
`DDR 11,2 X 2G
`(x4)
`
`n n
`
`M
`
`n
`
`DDR 11,2 X 2G
`(x8)
`
`BA Oh - 7h
`Row 0000h - FFFFh
`Column 000h - 7FFh
`
`ENABLE
`
`ROW
`
`ROW
`A(15)
`
`BA Oh - 7h
`Row 0000h - 7FFFh
`Column 000h - 7FFh
`
`DISABLE
`
`COLUMN
`
`COL
`A(1 1)
`
`BA Oh - 7h
`Row 0000h - FFFFh
`Column 000h - 3FFh
`
`ENABLE
`
`ROW
`
`ROW
`A(15)
`
`Fig. 7F
`
`BA Oh - 7h
`Row 0000h-7FFFh
`Column 000h-7FFh
`
`BA Oh - 7h
`Row 8000h-FFFFh
`Column 000h-7FFh
`
`BA Oh - 7h
`Row 0000h-7FFFh
`Column 000h-3FFh
`BA Oh - 7h
`Row 00OOh-7FFFh
`Column 400h-7FFh
`
`BA Oh - 7h
`Row 0000h-7FFFh
`Column 000h-3FFh
`
`BA Oh - 7h
`Row 8000h-FFFFh
`Column 000h-3FFh
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 12
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 12 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`Command Mode Addr
`
`MRS
`EMRS
`REFRESH
`SELF REFRESH
`ENTRY
`SELF REFRESH
`EXIT
`
`SINGLE BANK
`PRECHARGE
`
`ALL BANK
`PRECHARGE
`
`ACTIVATE
`
`X
`X
`X
`
`X
`
`X
`
`Col
`
`Row!
`Bank
`
`X
`
`Col
`Row/
`Bank
`
`WRITE
`
`X
`
`WRITE WITH
`AUTO
`PRECHARGE
`
`READ
`
`READ WITH
`AUTO
`PRECHARGE
`
`Row/
`Bank
`
`Col
`
`X
`
`Row/
`Bank
`
`Col
`
`X
`X
`X
`
`x
`
`x
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`X
`
`X
`
`X
`
`X
`
`DDR A
`
`DDR B
`
`P
`Bank
`
`X
`X
`X
`
`Command Addr Command Addr
`MRS
`MRS
`1
`1
`2
`EMRS
`2
`EMRS
`X
`REFRESH
`X
`REFRESH
`SLF REFRESH
`SLF REFRESH
`X
`ENTRY
`ENTRY
`SLF REFRESH
`X SLF REFRESH
`EXIT
`EXIT
`X
`SB PRECHG
`SB PRECHG
`SB PRECHG
`NOP
`A
`B
`NOP
`SB PRECHG
`
`X
`X
`
`X
`X
`X
`
`X
`X
`
`x
`X
`X
`
`X
`
`X
`A
`B
`A
`B
`
`A
`B
`X
`A
`B
`
`A
`B
`X
`
`AB PRECHG
`
`ACTIVATE
`ACTIVATE
`NOP
`WRITE
`NOP
`WRITEAP
`NOP
`WRITEAP
`READ
`NOP
`READAP
`NOP
`READAP
`
`X
`
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`
`AB PRECHG
`
`ACTIVATE
`NOP
`ACTIVATE
`NOP
`WRITE
`NOP
`WRITEAP
`WRITEAP
`NOP
`READ
`NOP
`READAP
`READAP
`
`X
`
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`X
`
`L
`
`b (cid:9)
`
`c (cid:9)
`
`d (cid:9)
`
`e
`(cid:127) i ^
`
`f (cid:9)
`
`g (cid:9)
`
`h
`
`v
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 13
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 13 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`8
`
`q (cid:9)
`
`c (cid:9)
`
`d (cid:9)
`
`e
`
`f
`
`BURST TERM Row/
`Bank
`
`Col
`
`X
`X
`
`X
`
`X
`
`NOP
`DEVICE
`DESELECT
`POWER
`DOWN
`ENTRY
`POWER
`DOWN
`EXIT
`
`X
`
`X
`
`X
`X
`
`X
`
`X
`
`A
`B
`X
`
`X
`X
`
`X
`
`X
`
`BURST_TERM
`NOP
`BURST TERM
`or NOP
`based upon
`last write bank
`NOP
`DEVICE
`DESELECT
`PWR
`DOWN
`ENTRY
`PWR
`DOWN
`EXIT
`
`X
`X
`X
`
`X
`
`X
`X
`
`X
`
`IT
`
`NOP
`BURST TERM
`BURST TERM
`or NOP
`based upon
`last write bank
`NOP
`DEVICE
`DESELECT
`PWR
`DOWN
`ENTRY
`PWR
`DOWN
`EXIT
`
`X
`X
`X
`
`X
`
`X
`X
`
`X
`
`NOTES: 1. if cl mode. = subtract; cl = cl - 1 to DDRs
`2. ads squelch-based on ODS setting, rtt squelch-based
`on REEF setting, ocd squelch-default, dqs_n enable,
`rdqs disable, out squelch - enable
`3. A command consists of RAS_n, CAS_n, CS, WE_n, and A(1 0).
`
`(cid:127) ii
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 14
`
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 14 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`EMR I OE IRDQSI DQS_n ICOD PROGRAMI Rtt Posted CAS ni Rtt IODSIDLL
`
`0
`
`El ODS Squelched Value
`100% if ODS Pin = 0
`60% if ODS Pin = 1
`
`1
`
`E6 E2
`
`Squelched Value
`75 Ohms if Rank = 1
`1
`0 150 Ohms if Rank = 2
`
`0 (cid:9)
`
`.1 (cid:9)
`
`E9 E8 E71 OCD Squelched Value
`
`I 1 1 1 I OCD Default
`
`El 0 DQS n Squelched Value
`
`0
`
`Enabled
`
`I E 1 1 1 RDQS Squelched Value
`I (cid:9)
`Disabled
`0
`
`I El 21 OE Squelched Value
`I (cid:9)
`0
`Enabled
`
`Note: All other Bits passed thru as received from the Host
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 15
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 15 of 18
`
`US 2006/0277355 Al
`
`ECLK
`CSOA
`
`DQA(3:0) (cid:9)
`DQSOA
`
`T
`
`1016
`H (cid:9)
`.A
`
`ASIC - D
`Q(3:0)
`DQ(3:0)
`
`ASIC (cid:9)
`DQSO
`
`DQSO
`
`ASIC (cid:9)
`DQ(7:4) (cid:9)
`ASIC (cid:9)
`DQS1 (cid:9)
`
`DQA(7:4)
`DQS1A
`
`DQ(7:4) (cid:9)
`
`DQS1
`
`SWITCH
`ASIC
`
`NCLK
`
`1004
`
`iN s:
`
`t ^
`
`ASIC
`PIPE
`
`AC
`CSO
`CS1
`
`ACA
`CSOA
`CS1A
`Control Unit
`ASIC
`
`ACA
`
`CSOA
`
`1002
`ACB
`
`Parity
`Error
`Mode (cid:9)
`
`ACB
`CSOB CSOB
`CS1 B
`
`NCLK
`
`Error
`
`Fig. 10
`
`I (cid:9)
`I (cid:9)
`1012
`DQ AC CS CK
`DQS N/2 DDR
`
`DQ AC CS CK
`DQS NO DDR
`
`1010
`
`1006
`
`DQ AC CS CK
`DQS N/2 DDR
`
`DQ AC CS CK
`DQS N/2 DDR
`
`11:
`
`PCLK (cid:9)
`
`PLL (cid:9)
`
`NCLK
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 16
`
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication (cid:9) Dec. 7, 2006 (cid:9) Sheet 16 of 18 (cid:9)
`
`US 2006/0277355 Al
`
`ECLK
`CSOA
`ACA
`
`I
`
`ECLK
`CS1AA
`ACAA
`
`D6^A(3:0)
`DQSOA
`
`
`DQSO
`
`4 DQ AC CS CK 4 DQ AC CS CK
`DQS N/2 DDR
`DQS N/2 DDR
`
`DQ( 3:O)
`DQ(3:0)
`ASIC
`DQSO
`1112
`ASIC
`DQ(7:4) DQ(7:4) DQA(7:4) 4 DQ AC CS CK 4 DQ AC CS CK
`DQS N/2 DDR
`DQS N/2 DDR
`ASIC
`D6ZS1A
`DQS1
`DQS1
`
`ECLK
`CS1 BB
`ACBB
`
`NCLK
`
`I
`
`ECLK
`CSOB (cid:9)
`SWITCH
`ACB
`ASIC
`DQB(3:0) 4 DQ AC CS CK 4 DQ AC CS CK
`DQS N/2 DDR
`DQSOB
`DQS N/2 DDR
`
`1108
`
`1110
`
`DQ AC CS CK
`DQS N/2 DDR
`
`4
`
`DQ AC CS CK
`DQS N/2 DDR
`
`1106
`
`DQB(7:4) 4
`DQS1 B
`ASIC PIPE
`AC AC (cid:9)
`ACA ACA
`CSOA
`CSO CSO (cid:9)
`CS1A CSOA
`CS1 (cid:9)
`CS1
`Control Unit A
`NCLK
`1 104
`Parity Parity (cid:9) ASIC (cid:9)
`ACB
`ACB (cid:9)
`CSOB
`Error Error (cid:9)
`CS1 B CSOB
`Mode Mode (cid:9)
`
`ACAA
`
`AC
`ACA
`AC (cid:9)
`CSOA
`CSO CSO (cid:9)
`CS1A CS1AA
`CS1 CS1 (cid:9)
`Control Unit B
`NCLK
`1 102
`Parity (cid:9) ASIC (cid:9)
`ACB
`ACBB
`CSOB
`Mode Error (cid:9)
`CS1 B
`Mode (cid:9)
`
`CS1 BB
`
`PCLK
`
`PLL
`
`NCLK
`
`Fig. (cid:9)
`
`I I
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 17
`
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 17 of 18
`
`US 2006/0277355 Al
`
`ECLK
` CSOA
`
`
`
`ASIC (cid:9)
`DQ(3:0)
`ASIC (cid:9)
`DQSO
`
`D
`Q(3:0)
`
`DQSO
`
`ASIC (cid:9)
`DQ(7:4)
`DQ(7:4) DQS1
`
`DQA(3:0) (cid:9)
`DQSOA (cid:9)
`
`DQA(7:4)
`DQS 1 A
`
`8 DQ AC CS CK (cid:9)
`DQS N/2 DDR
`
`1206
`
`1210
`
`SWITCH
`ASIC (cid:9)
`
`I
` CSOB
`
`I ACB
`
`DQB(3:0)
`DQSUB
`DQB(7:4)
`DQS1 B
`
`ASIC
`PIPE
`
`ACA
`
`ACA
`CSOA
`CS1A CSOA
`1202
`Control Unit
`ASIC
`ACB
`
`NCLK
`
`1204
`
`AC
`CSO
`
`NCLK
`
`AC (cid:9)
`CSO (cid:9)
`CSl (cid:9)
`
`Parity Parity (cid:9)
`Error
`Error (cid:9)
`Mode (cid:9)
`Mnrii
`
`ACB
`CSOB
`CS1 B
`
`CSOB
`
`Fig. 12
`
`I
`I (cid:9)
`DQ AC CS OK 1208
`
`DQS N/2 DDR__J
`
`PCLK (cid:9)
`
`PLL (cid:9)
`
`NCLK
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 18
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`Patent Application Publication Dec. 7, 2006 Sheet 18 of 18
`
`US 2006/0277355 Al
`
`ECLK
`CSOA
`ACA
`
`ECLK
`CS1A
`ACA
`
`DQ
`DQS AC
`
`AC
`
` RK LJ DQS
`
`ASIC
`DQ(3:0)
`ASIC
`DQSO
`
`DQ(3:0) DQA(3:0)
`DQSOA
`
`DQSO
`
`ASIC
`DQ(7:4)
`DQ(7:4) DQS1
`
`DQA(7:4)
`DQS 1 A
`
`SWITCH (cid:9)
`ASIC (cid:9)
`
`I CSOB
`
`ACB
`
`1310
`
`ECLK
`CS1 B
`ACB
`
`I [1306
`
`
`
`K DDR
`
`DQB(3:0) 8 DQ AC CS CK 8 DQ AC CS CK
`DQS N/2 DDR 1308
`DQSOB DQS N/2 DDR (cid:9)
`
`DQB(7:4)
`DQS1 B
`
`ASIC
`PIPE
`
`NCLK
`
`130
`
`AC
`CSO CSO
`CSl CS1
`
`NCLK
`
`ACA
`ACA
`CSOA CSOA
`CS1A ICS1A
`Control Unit
`1302
`ASIC
`ACB
`ACB
`CSOB CSOB
`CS1B CS1B
`
`Fig. 13
`
`Parity Parity
`Error (cid:9)
`Error
`Mode Mode
`
`PCLK (cid:9)
`
`PLL (cid:9)
`
`NCLK
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 19
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`US 2006/0277355 Al
`
`Dec. 7, 2006
`
`CAPACITY-EXPANDING MEMORY DEVICE
`
`FIELD OF THE INVENTION
`
`[0001] Various embodiments of the invention pertain to
`memory devices. At least one embodiment of the invention
`pertains to a controller and architecture that permits trans-
`parent bank switching of memory devices.
`
`DESCRIPTION OF RELATED ART
`
`[0002] Memory devices have widespread use in electronic
`products. Many computing devices enable memory expan-
`sion by including one or more slots in which to couple a
`memory module. One type of commonly used memory
`module is the dual inline memory module (DIMM). Typi-
`cally, memory modules include a small circuit board with
`contact pads along one edge to couple to a slot on another
`circuit board, such as a computer motherboard. In some
`cases, the contact pads are placed on two surfaces of the
`small circuit board along an edge of the small circuit board.
`In some implementations, the number and size of the contact
`pads may be defined by various bus or communication
`standards. In other implementations, the physical space
`available for such contact pads and/or electrical traces or
`buses may determine the number and size of the contact
`pads.
`
`[0003] Memory devices are typically mounted on one or
`two surfaces of the small circuit board of the memory
`module. Dynamic random access memory (DRAM) chips
`are often used in memory module applications. The memory
`devices are communicatively coupled to the contact pads
`such that data may be sent to a memory module and stored
`in the memory devices. Various electrical paths are used to
`transfer data, specify a memory address, and control the flow
`of the data to and from the memory devices.
`
`[0004] To access locations in memory devices, such as
`DRAM, a memory location is typically specified by the
`system over an address bus. This address is decoded to
`access the correct memory device. Some memory systems
`map memory addresses into a column and row. Row address
`and column address signals are time-multiplexed to permit
`a greater number of memory locations to be addressed
`without increasing the number of address lines.
`
`[0005] As electronic devices become more sophisticated,
`the need for greater storage or memory increases. Since
`many electronic applications are restricted by industry stan-
`dards and physical limitations prevent increasing a bus size
`(i.e., adding more contact pads and/or electrical paths to a
`memory module and/or system memory controller is often
`prohibitive) the maximum size of the addressable memory
`on a memory module may be limited. Thus, increasing the
`memory capacity of a memory module would require a
`larger bus size. This is often undesirable and impractical for
`backward compatibility of existing devices and established
`industry standards.
`
`[0006] U.S. Pat. No. 6,526,473 describes a scheme to
`speed up the writing and reading cycles to memory devices.
`A control signal is used to connect only selected memory
`modules to a data bus at one time during a data transfer cycle
`in which data is input and output. By connecting only the
`addressed memory module(s) to the data bus, the load
`capacitance on the data bus is minimized. While this scheme
`
`provides ways to speed up writing to and reading from
`memory devices, it does not enable expanding the total
`memory capacity of a system beyond the limits of the data
`bus used.
`
`[0007] U.S. Pat. No. 6,070,217 describes a scheme to
`maximize the memory capacity of a memory module while
`minimizing the capacitive loading of the data bus. Switches
`are placed between the bus interface and memory devices to
`activate or deactivate the line to the memory devices. When
`deactivated, the switches present high impedance thereby
`reducing the loading on the data bus. When a switch is
`activated, only the corresponding memory device is acti-
`vated and adds a minimal capacitance to the data bus. While
`this patent presents a solution to bus loading, it does not
`enable expanding the total memory capacity of a system
`beyond the limits of the data bus used.
`
`[0008] U.S. Pat. No. 6,414,868 describes a memory
`expansion module including an upper and a lower memory
`bank and a control unit that selects between the upper and
`lower memory banks based on an external bank select
`signal. That is, two memory banks are added to the memory
`module and the controller selects which memory bank to
`access based on an externally generated signal (i.e., high-
`order address bit). This scheme is undesirable as it is
`incompatible with modern memory devices (e.g., DDR and
`DDR2 SDRAM) and industry standards.
`
`[0009] U.S. Patent Publication 2004/0000708 describes a
`stacked chip scale-packaged memory module that conserves
`board space while reducing bus impedance. A high-speed
`switching system, field effect transistor (FET) switches, is
`employed to select a data line associated with each level of
`a stacked memory module to reduce the loading effect on the
`data lines in memory access. The problem with this scheme
`is that while FET switches have a fast propagation delay,
`their switch time is too slow and imprecise to reliably
`comply with industry standards, such as the Joint Electron
`Device Engineering Council (JEDEC) standards, used in
`many memory applications.
`
`SUMMARY OF THE INVENTION
`
`[0010] The invention relates to a device, system, and
`method for expanding the memory capacity of a memory
`module. A control unit and memory bank switch are
`mounted on a memory module or, alternately, on a system
`motherboard to selectively control write and read operations
`to/from memory devices communicatively coupled to the
`memory bank switch. By selectively activating or deacti-
`vating the memory devices in real-time, separate smaller-
`capacity memory devices may emulate a single larger-
`capacity memory device. That is, the invention expands the
`addressable memory capacity on a module by making two
`smaller-capacity memory devices emulate a single higher-
`capacity memory device. A state machine is used to send
`Read/Write commands to the intended memory bank while
`sending no-operation commands to the other memory bank.
`This permits maintaining multiple memory banks commu-
`nicatively coupled to the data bus without device activation
`and termination cycle delays.
`
`[0011] One embodiment of the invention provides a sys-
`tem having a processor, a bus communicatively coupled to
`the processor to carry data to and from the processor, and
`memory sockets coupled to the bus. A memory module is
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 20
`
`(cid:9)
`

`

`US 2006/0277355 Al
`
`Dec. 7, 2006
`
`2
`
`coupled to a memory socket, the memory module including
`a control unit to receive memory address information from
`the bus, and a memory bank switch communicatively
`coupled to the control unit and the bus. The control unit
`maps a received logical address to a physical address
`corresponding to the particular memory bank configuration
`employed. It also directs commands to the memory banks to
`indicate which memory bank should be operational and
`which one should be passive (do nothing). The memory
`bank switch is designed to receive data information from the
`bus and direct the data information to a plurality of physical
`memory banks according to control signals from the control
`unit that maps one logical memory bank to a plurality of
`physical memory banks. The memory module further
`includes a plurality of memory devices coupled to the
`plurality of physical memory banks, the plurality of memory
`devices appearing as a single memory device to the system
`processor. That is, the emulated single memory device has
`the capacity of the combined plurality of memory devices.
`
`[0012] The invention expands the memory capacity of a
`memory module by using a plurality of smaller-capacity
`memory devices that function as a single higher-capacity
`memory device. This is accomplished without the need to
`add more lines to the bus or any additional external signal.
`Moreover, the load on the bus is not increased because the
`memory bank switches present a single load to the bus, not
`the load of the individual memory devices coupled thereto.
`A control unit provides a state machine that controls the
`commands to a plurality of memory devices in multiple
`banks so as to read/write a single memory bank without the
`need to disconnect the other memory banks from the data
`bus.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0013] FIG. 1 illustrates a computing system that includes
`a capacity-expanding memory device according to one
`embodiment of the invention.
`
`[0014] FIG. 2 illustrates a block diagram of a capacity-
`expanding memory device according to one embodiment of
`the invention.
`
`[0015] FIG. 3 illustrates a block diagram of an address
`and command processing system for a capacity-expanding
`memory device according to one embodiment of the inven-
`tion.
`
`[0016] FIG. 4 illustrates a block diagram of a data pro-
`cessing system for a capacity-expanding memory device
`according to one embodiment of the invention.
`
`[0017] FIGS. 5 and 6 illustrate memory modules accord-
`ing to two different embodiments of the invention.
`
`[0018] FIGS. 7A-F illustrate an address mapping table, or
`bank switch state machine, that may be used by the control
`unit to map a received address (primary address space) to
`one of the memory banks (secondary address space) accord-
`ing to one embodiment of the invention.
`[0019] FIGS. 8A-B illustrate a command scheme for a
`control unit to operate multiple banks concurrently accord-
`ing to one embodiment of the invention.
`[0020] FIG. 9 illustrates a plurality of bits that are
`squelched from the original extended mode register set
`(EMRS) command according to one embodiment of the
`invention.
`
`[0021] FIGS. 10, 11, 12 and 13 illustrate different con-
`figurations of memory modules (e.g., DIMMs) that can be
`built using combinations of the control unit and bank switch
`according to various embodiments of the invention.
`
`DETAILED DESCRIPTION
`
`[0022] Methods and systems that implement the embodi-
`ments of the various features of the invention will now be
`described with reference to the drawings. The drawings and
`the associated descriptions are provided to illustrate embodi-
`ments of the invention and not to limit the scope of the
`invention. Reference in the specification to "one embodi-
`ment" or "an embodiment" is intended to indicate that a
`particular feature, structure, or characteristic described in
`connection with the embodiment is included in at least an
`embodiment of the invention. The appearances of the phrase
`"in one embodiment" or "an embodiment" in various places
`in the specification are not necessarily all referring to the
`same embodiment. Throughout the drawings, reference
`numbers are re-used to indicate correspondence between
`referenced elements. In addition, the first digit of each
`reference number indicates the figure in which the element
`first appears.
`
`[0023] In the following description, certain terminology is
`used to describe certain features of one or more embodi-
`ments of the invention. The term "memory device" refers to
`any device capable of storing information, including
`DRAM. The term "memory module" refers to any package
`in which one or more memory devices are mounted (e.g.,
`DIMM, SIMM, etc.).
`
`[0024] In the following description, specific details are
`given to provide a thorough understanding of the embodi-
`ments. However, it will be understood by one of ordinary
`skill in the art that the embodiments may be practiced
`without these specific detail. For example, circuits may be
`shown in block diagrams in order not to obscure the embodi-
`ments in unnecessary detail. In other instances, well-known
`circuits, structures and techniques may be shown in detail in
`order not to obscure the embodiments.
`
`[0025] Furthermore, embodiments may be implemented
`by hardware, software, firmware, middleware, microcode, or
`any combination thereof. When implemented in software,
`firmware, middleware or microcode, the program code or
`code segments to perform the necessary tasks may be stored
`in a machine-readable medium such as a storage medium or
`other storage(s). A processor may perform the necessary
`tasks. A code segment may represent a procedure, a function,
`a subprogram, a program, a routine, a subroutine, a module,
`a software package, a class, or any combination of instruc-
`tions, data structures, or program statements. A code seg-
`ment may be coupled to another code segment or a hardware
`circuit by passing and/or receiving information, data, argu-
`ments, parameters, or memory contents. Information, argu-
`ments, parameters, data, etc. may be passed, forwarded, or
`transmitted via any suitable means including memory shar-
`ing, message passing, token passing, network transmission,
`etc.
`
`[0026] One embodiment of the invention relates to a
`system that expands the memory capacity of a memory
`module without increasing the bus size. A controller and
`memory bank switch allow the use of separate smaller-
`capacity memory devices to emulate a single higher-capac-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 21
`
`(cid:9)
`

`

`US 2006/0277355 Al
`
`Dec. 7, 2006
`
`ity memory device to a host system. This effectively expands
`the number of addressable banks per memory module with-
`out the need for additional chip select lines on the main
`memory bus. For example, the invention expands the
`addressable memory banks on a module by making two
`smaller-capacity memory devices emulate a single higher-
`capacity memory device. In one implementation, the inven-
`tion permits two separate SDRAM DDR devices to appear
`as a single higher-capacity SDRAM DDR device to a source
`device (e.g., microprocessor, memory controller, etc.).
`
`[0027] FIG. 1 illustrates a computing system 100 that
`includes a capacity-expanding memory device according to
`one embodiment of the invention. The computing system
`100 may include a processing unit 102 coupled to an
`input/output (I/O) controller 104 to receive and/or send
`information. The processing unit 102 may also be coupled to
`a memory module 106 to retain or store information. The
`memory module 106 may include an embodiment of the
`capacity-expanding memory device 108
`that permits
`increasing the memory capacity without increasing the bus
`size or communication path 110 to and/or from the memory
`module 106. In one implementation of the invention, the bus
`size or communication path 110 to and/or from the memory
`module 106 is not modified to accommodate the capacity-
`expanding memory device 108. Thus, the capacity-expand-
`ing memory device 108 is compatible with existing system
`architectures and transparent to the rest of the system (e.g.,
`microprocessor, operating system, etc.). Moreover, the resis-
`tive and/or capacitive load on the bus 110 is not increased
`because the memory module 106 presents a single load to
`the bus 110, not the load of the individual memory devices
`coupled thereto.
`
`[0028] FIG. 2 illustrates a block diagram of a capacity-
`expanding memory system 200 according to one embodi-
`ment of the invention. In this embodiment of the invention,
`the capacity-expanding memory system 200 is communica-
`tively coupled to a DIMM interface 202. The DIMM inter-
`face 202 may be coupled to a memory socket and commu-
`nication bus over which data, memory addresses,
`commands, and control information are transmitted. The
`capacity-expanding feature of the invention is accomplished
`by a combination of a control unit 204 and one or more
`memory bank switches 206 & 208.
`
`[0029] The control unit 204 receives memory addresses
`and commands over the DIMM interface 202. In one
`embodiment of the invention, memory bank switches 206 &
`208 receive data information from the DIMM interface 202
`via data buses 230 & 232, respectively. The control unit 204
`is communicatively coupled to the dual memory bank
`switches 206 & 208 via a control bus 210 and indicates to
`the memory bank switches 206 & 208 how data from the
`DIMM interface 202 should be received and/or stored.
`
`[0030] According to one embodiment of the invention, the
`DIMM interface 202 provides a range of data bits simulta-
`neously (e.g., Data Group 0 through Data Group N). A first
`data group (i.e., Data Group 0) is received by a first memory
`bank switch 206 while a second data group (i.e., Data Group
`N) is received by a second memory bank switch 208. Each
`memory bank switch 206 & 208 is communicatively
`coupled to a plurality of memory banks that may have one
`or more memory devices (e.g., dynamic random access
`memory (DRAM)). Data may be read from or written to
`
`these memory devices using any known addressing scheme
`(e.g., mapping memory addresses into a column and row).
`For example, memory bank switch 206 includes Port A and
`Port B, coupled to data busses 234 & 236 respectively,
`through which it sends and receives data information to
`and/or from four memory banks (i.e., Bank 0, Bank 1, Bank
`2, and Bank 3). The four memory banks (i.e., Bank 0, Bank
`1, Bank 2, and Bank 3)