(19)
`
`Europäisches Patentamt
`
`European Patent Office
`
`Office européen des brevets
`
`Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give
`notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in
`a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art.
`99(1) European Patent Convention).
`
`Printed by Jouve, 75001 PARIS (FR)
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`EP 1 085 399 B1
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`2
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`Description
`
`[0001] The present invention relates to a method of
`controlling temperature in an electronic apparatus such
`as a computer device, more particularly, to a method of
`changing the operation of a central processing unit
`(CPU) based on an information signal identifying the
`status of a cooling device such as a cooling fan installed
`within the computer device.
`[0002]
`In general, a cooling fan is disposed within an
`enclosure of a computer system. The cooling fan is de-
`signed to generate air stream for taking out heat from a
`CPU and for blowing it out of the enclosure. The air
`stream serves to suppress the interior temperature of
`the enclosure from increasing. Employment of no cool-
`ing fan induces an excessive temperature increase with-
`in the enclosure, so that the CPU and other electronic
`components in the vicinity of the CPU may suffer from
`a defect or failure of operation.
`[0003]
`If the cooling fan fails to properly operate, the
`heat generated at the CPU cannot be released out of
`the enclosure enough. In this case, the operation of the
`CPU is preferably suppressed to reduce the generated
`heat so that the increase can be avoided in the interior
`temperature. The suppression can be achieved by a re-
`duced or thinned-out frequency of the clock signal sup-
`plied to the CPU, for example.
`[0004] When the operation of the CPU is to be sup-
`pressed, the CPU is expected to receive an interrupt re-
`quest IRQ for identifying defect or failure of the cooling
`fan. When the CPU receives the interrupt request IRQ,
`the CPU is designed to temporarily discontinue the cur-
`rent primary processing so as to realize establishment
`of a reduced or thinned-out frequency of the clock signal
`in an interruption processing. As a result of suppression
`of the operation in the CPU in this manner, an excessive
`increase can be prevented in the interior temperature of
`the enclosure.
`[0005] The interrupt request IRQ is usually supplied
`from a system controller such as a chipset, for example.
`The system controller is thus required to include a hard-
`ware or electronic component for generating an interrupt
`request IRQ. The circuit structure of the system control-
`ler inevitably gets complicated. In addition, reduction in
`size cannot be achieved in the system controller due to
`the hardware for generating an interrupt request IRQ.
`[0006] US-A-5 907 689 discloses a computer system
`comprising plural CPUs. A system management module
`is coupled to each of the CPUs. The system manage-
`ment module monitors the temperature and the fan
`speed. An interrupt signal is output from various ele-
`ments of the computer system, such as a keyboard and
`mouse interface controller and system management re-
`mote devices. This interrupt signal is transmitted to a
`system management central incorporated in the system
`management module. The system management central
`issues error signals in the event of a system error. The
`system management central
`isolates failed compo-
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`nents. The system management central also permits dy-
`namic switching to a spare component, if the spare is
`provided.
`[0007] US-A-5 930 110 discloses plural embodi-
`ments. In a fourth embodiment of this document, a sen-
`sor is incorporated in a CPU. The sensor measures tem-
`perature and may be arranged near the CPU. According
`to the measured temperature, a system control gate ar-
`ray generates an interrupt signal (system management
`interrupt). The CPU conducts processing for a clock
`speed change or suspending of the operation in re-
`sponse to the interrupt signal. In a fifth embodiment of
`this document, a fan is adopted to cool a heat generating
`portion such as a CPU and a CPU board. The drive con-
`troller turns on or off the fan. The drive controller controls
`the operation of the fan based on the temperature meas-
`ured by temperature sensors. The fan, the drive control-
`ler and the temperature sensors are incorporated in an
`expansion unit (deskstation).
`[0008] An embodiment of the present invention may
`provide a temperature controller circuit capable of man-
`aging the interior temperature of an electronic apparatus
`with a simpler circuit structure, and a method therefor.
`[0009] According to the present invention, there is
`provided a temperature controller circuit, comprising:
`
`a central processing unit; and
`an interrupt request generating unit generating an
`interrupt request signal, characterised in that
`the interrupt request generating unit generates the
`interrupt request signal based on a temperature in-
`formation signal identifying a temperature and is de-
`signed to output the interrupt request signal to the
`central processing unit, and
`the temperature controller circuit further comprises
`an input unit designed to supply to the central
`processing unit a status information signal identify-
`ing status of a cooling device.
`
`[0010] Employment of the above-described tempera-
`ture controller circuit may serve to implement a method
`of controlling temperature in an electronic apparatus ac-
`cording to the present invention. The method compris-
`es:
`
`obtaining an interrupt request signal based on a
`temperature information signal for identifying a tem-
`perature;
`obtaining a status information signal for identifying
`status of a cooling device in response to reception
`of the interrupt request signal; and
`changing operation of
`the electronic apparatus
`based on the status information signal.
`
`[0011] With the above-described method, a central
`processing unit (CPU) is allowed to utilize the tempera-
`ture information signal, identifying the temperature, so
`as to commence an interruption processing for control-
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`LENNOX EXHIBIT 1006
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`ling the temperature. During the interruption processing,
`the CPU is designed to recognize the status of the cool-
`ing device in accordance with the status information sig-
`nal. Additional hardware is not required to accompany
`the CPU so as to solely generate an interrupt request
`signal based on the status of the cooling device. The
`circuit structure of the temperature controller circuit can
`be simplified.
`[0012]
`In general, in the case where the cooling de-
`vice is employed to control the temperature in the elec-
`tronic apparatus, a failure or defect of the cooling device
`can be ignored if the temperature is properly controlled,
`in other words, if the temperature stays below a prede-
`termined temperature. If an interrupt request signal is
`designed to be generated in response to the failure or
`defect of the cooling device as is conventionally known,
`the operation of the CPU is correspondingly interrupted
`irrespective of the proper temperature in the electronic
`apparatus. On the other hand, according to the present
`invention,
`the temperature information signal
`is de-
`signed to trigger the generation of the interrupt request
`signal, so that the CPU is reliably prevented from suf-
`fering from a frequent interruption during the operation
`as long as the temperature is properly controlled irre-
`spective of a failure or defect of the cooling device.
`[0013] A temperature detector or thermal sensor may
`be connected to the interrupt request generating unit so
`as to measure the actual temperature within the enclo-
`sure of the electronic apparatus. The thermal sensor
`serves to achieve a proper generation of the interrupt
`request signal in correspondence with variation in the
`actual temperature within the enclosure of the electronic
`apparatus. The control of the cooling device based on
`the thus generated interrupt request signal serves to
`avoid an excessive increase in the temperature within
`the enclosure of the electronic apparatus. The thermal
`sensor may be designed to directly measure the tem-
`perature of the CPU.
`[0014] For example, the input unit may comprise a
`general purpose input (GPI) circuit incorporated within
`a system controller (chipset) or a so-called ultra I/O (In-
`put/Output). The system controller and the ultra I/O are
`in general designed to support the operation of the CPU.
`The system controller may comprise a north bridge con-
`nected to the CPU through a system bus, and a south
`bridge connected to the north bridge through a PCI bus,
`for example.
`[0015] The cooling device may include a cooling fan
`designed to generate air stream for taking out heat from
`the CPU, for example. However, the cooling device is
`not limited to the cooling fan. The cooling device is only
`required to prevent an excessive increase in the tem-
`perature within the enclosure of the electronic apparatus
`by any means.
`[0016]
`In the aforementioned method, the operation
`of the CPU may be suppressed in response to reception
`of the status information signal identifying a failure or
`defect of the cooling device. The suppression in the op-
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`eration of the CPU serves to suppress heat generated
`at the CPU. Accordingly, an increase in the temperature
`within the enclosure can be suppressed. The sup-
`pressed operation of the CPU may also be achieved
`when the status information signal identifies a compul-
`sory termination of the operation of the cooling device
`due to an intentional reduction in energy consumption.
`[0017]
`In the aforementioned method, a thinned-out
`clock signal may be supplied to the central processing
`unit so as to suppress the operation of the central
`processing unit. Likewise, a clock signal of a lower clock
`frequency may be supplied to the central processing unit
`so as to suppress the operation of the central processing
`unit. Otherwise, a software managing the overall system
`such as an operating system (OS) may be suspended
`or shut down in suppressing the operation of the CPU.
`[0018] Furthermore, the aforementioned method may
`be realized by a computer software such as a BIOS (Ba-
`sic Input/Output System). The computer software may
`be installed to the computer system from a portable stor-
`age medium such as a magnetic disk, including an FD
`(floppy disk), an optical disk, including a CD (compact
`disk), or the like. Alternatively, the computer software
`may be installed to the computer system through a net-
`work such as the Internet.
`[0019] A preferred embodiment of the invention will
`now be described in conjunction with the accompanying
`drawings, wherein:
`
`Fig. 1 illustrates the overall appearance of a note-
`book type personal computer;
`Fig. 2 is a block diagram schematically illustrating
`the circuit structure of a motherboard;
`Fig. 3 is a block diagram schematically illustrating
`the structure of a south bridge;
`Fig. 4 is a flowchart illustrating an example of an
`interruption processing;
`Fig. 5 is a time chart illustrating the concept of a
`thinned-out clock signal;
`Fig. 6 is a flowchart illustrating another example of
`the interruption processing;
`Fig. 7 is a flowchart illustrating a further example of
`the interruption processing;
`Fig. 8 is a flowchart illustrating a still further example
`of the interruption processing; and
`Fig. 9 is a time chart schematically illustrating the
`advantage of a threshold temperature for a temper-
`ature rise which is higher than a threshold temper-
`ature for a temperature drop.
`
`[0020] Fig. 1 schematically illustrates a notebook type
`personal computer 10 as an electronic apparatus. The
`personal computer 10 comprises a main enclosure 11
`in which a central processing unit (CPU) and other elec-
`tronic components are incorporated, and a lid 12 con-
`nected to the main enclosure 11. A liquid crystal display
`(LCD) and the like is incorporated in the lid 12. The lid
`12 is allowed to swing, relative to the main enclosure
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`11, about the support axis. The swinging movement of
`the lid 12 is designed to cause the lid 12 to be super-
`posed on the main enclosure 11.
`[0021]
`Input devices such as a keyboard 13 and a
`pointing device 14 are mounted over the upper surface
`of the main enclosure 11. When application software is
`executed in the personal computer 10, an operator is
`expected to manipulate the keyboard 13 and/or the
`pointing device 14 so as to input required information
`and/or instructions. Processing and/or results of execu-
`tion of the application software may be displayed on the
`screen of the LCD incorporated in the lid 12.
`[0022] Fig. 2 schematically illustrates the circuit struc-
`ture of a printed circuit board unit such as a motherboard
`16 incorporated within the main enclosure 11. A CPU 17
`is mounted on the motherboard 16 for executing appli-
`cation software on an operating system (OS), for exam-
`ple. A surface mount technique may be employed to
`mount the CPU 17 on the motherboard 16. Alternatively,
`the CPU 17 may be received within a CPU slot fixedly
`mounted on the motherboard 16.
`[0023] A temperature detector or thermal sensor 18
`is embedded within a silicon body of the CPU 17 for de-
`tecting a temperature of the CPU 17. The temperature
`detector 18 is designed to generate a temperature in-
`formation signal identifying the temperature of the CPU
`17. In generation of the temperature information signal,
`the temperature detector 18 compares a measured ac-
`tual temperature with a predetermined threshold tem-
`perature. When the measured actual temperature ex-
`ceeds the predetermined threshold temperature, the
`temperature detector 18 is allowed to keep outputting a
`notification signal of a high level. When the measured
`actual
`temperature stays below the predetermined
`threshold temperature, however, the temperature de-
`tector 18 is allowed to keep outputting the notification
`signal of a low level. The predetermined threshold tem-
`perature may be determined based on a highest permis-
`sible temperature for guaranteeing a reliable operation
`of the CPU 17 and other electronic components in the
`vicinity of the CPU 17.
`[0024] A system controller such as a chipset 19 is con-
`nected to the CPU 17. The chipset 19 is designed to
`manage the overall system of the personal computer 10.
`The chipset 19 comprises, for example, a north bridge
`21 connected to the CPU through a system bus 20, and
`a south bridge 23 connected to the north bridge 21
`through a so-called PCI (Peripheral Component Inter-
`connect) bus 22.
`[0025] A system memory unit 24 is connected to the
`north bridge 21. The north bridge 21 serves to allow the
`CPU 17 to fetch programs of the OS and/or application
`software temporarily stored in the system memory unit
`24. Memory modules such as a synchronous dynamic
`random access memory (SDRAM) can be employed as
`the system memory unit 24. The memory modules may
`be received within corresponding DIMM (dual
`in-line
`memory module) connectors fixedly mounted on the
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`motherboard 16, for example.
`[0026] A clock signal-is supplied to the CPU 17 and
`the system memory unit 24, respectively. The clock sig-
`nal is generated at a clock generator unit or circuit 25.
`The operational speed of the CPU 17 can be determined
`by the frequency of the clock signal. The clock signal
`may be supplied to the north and south bridges 21, 23
`and other electronic components or elements, in addi-
`tion to the CPU 17 and the system memory unit 24. As
`a result, the north and south bridges 21, 23 and the other
`electronic components are designed to operate in syn-
`chronization with the operation of the CPU 17.
`[0027] A so-called IDE (Integrated Device Electron-
`ics) connector 26 is connected to the south bridge 23 so
`as to establish an IDE interface. For example, the IDE
`connector 26 allows for connection of a large-capacity
`storage device such as a hard disk drive (HDD) 27 as-
`sembled within the main enclosure 11. When the CPU
`17 executes an application software, for example, the
`south bridge 23 serves to transfer programs and/or data,
`read out of the HDD 27, to the system memory unit 24.
`[0028] A PCMCIA (Personal Computer Memory Card
`International Association) controller unit 28 and a mo-
`dem 29 are respectively connected to the PCI bus 22.
`A PC card slot is electrically connected to the PCMCIA
`controller unit 28. When a PC card is received in the PC
`card slot, as is conventionally known, a specific interface
`such as an IDE or SCSI interface can be established
`between the north bridge 21 and an exterior peripheral
`device such as a compact disk (CD) drive 31, including
`a CD-ROM or CD-R or CD-RW drive. In addition, a
`phone or communication line can be connected to the
`modem 29. The line may be wired or wireless. The mo-
`dem 29 serves to connect the CPU 17 to a network such
`as the Internet, an extranet, or the like.
`[0029] A cooling device such as a cooling fan 32 is
`incorporated within the main enclosure 11 for generating
`air stream. The generated air stream is expected to es-
`cape out of the main enclosure 11 after absorbing heat
`within the main enclosure 11. The cooling fan 32 is ex-
`pected to suppress an increase in the interior tempera-
`ture of the main enclosure 11. A fan controller unit or
`circuit 33 serves to control the operation or rotation of
`the cooling fan 32. The fan controller unit 33 is designed
`to output an alarm signal when it detects any defect or
`failure in the operation or rotation of the cooling fan 32.
`[0030] A so-called ultra I/O (input/output circuit or
`unit) 35 is connected to the south bridge 23 through a
`so-called ISA (Industry Standard Architecture) bus 34.
`A pin terminal for the keyboard 13, a so-called PS/2
`(Personal System/2) connector 36 for receiving a con-
`nector terminal of the pointing device 14, and a so-called
`FDD (Floppy Disk Drive) connector 38 for receiving a
`connector terminal of an FDD 37, are respectively con-
`nected to the ultra I/O 35. Moreover, a PS/2 connector
`for receiving a connector terminal of an additional exter-
`nal keyboard, or a PS/2 connector for receiving a con-
`nector terminal of an external mouse device, both not
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`shown, may likewise be connected to the ultra I/O 35.
`[0031] A so-called flash memory (EEPROM: electri-
`cally erasable and programmable ROM, for example)
`39 is connected to the ultra I/O 35 for storing a BIOS
`(Basic Input/Output System). The CPU 17 is designed
`to manage the input/output operation between the OS
`and the fundamental peripheral devices such as the
`LCD, the keyboard 13, the pointing device 14, the HDD
`27, and the like, in accordance with the BIOS read out
`from the flash memory 39.
`[0032] As shown in Fig. 3, the south bridge 23 com-
`prises an instruction signal generating circuit 41 de-
`signed to generate a fan instruction signal in accordance
`with instructions issued from the CPU 17. The fan in-
`struction signal may include a trigger information signal
`for identifying an instruction to start or terminate a rota-
`tion of the cooling fan 32, a numerical information signal
`for identifying the rotation speed to be set at the cooling
`fan 32, and the like. The fan controller unit 33 is de-
`signed to control the operation or rotation of the cooling
`fan 32 in accordance with the instruction and the number
`identified in the fan instruction signal.
`[0033] An instruction signal generating circuit 42 is
`likewise designed to generate a clock-gate instruction
`signal STPCLK# in accordance with instructions issued
`from the CPU 17. The clock-gate instruction signal STP-
`CLK# may include information for identifying whether or
`not the clock signal is thinned out, how many clocks are
`made inoperative when the clock signal is thinned out,
`and the like. A clock gate 43 of the CPU 17 is designed
`to realize a thinned-out or a throttled clock signal in ac-
`cordance with the information included in the received
`clock-gate instruction signal STPCLK#.
`[0034]
`If a normal clock signal, without being thinned
`out or throttled, is supplied to the CPU 17, the CPU 17
`is allowed to operate at the maximum operational speed
`which is inherent to the clock frequency of the clock sig-
`nal. For example, when the clock gate 43 receives the
`clock-gate instruction signal STPCLK# identifying the
`"10% thinned-out," the clock gate 43 is adapted to alter-
`nately realize supply of the clock signal for 90ns and
`interruption of the supply for 10ns. Accordingly, an ALU
`(arithmetical and logical unit) 44 is caused to alternately
`repeat the continuation and the discontinuation of the
`operation by the ratio of 9 to 1. The load to the ALU 44
`can be suppressed to 90% of the maximum load per-
`missible to the ALU 44. Such suppression in the load of
`the ALU 44 is expected to contribute to suppression of
`heat generated at the CPU 17. It should be noted that
`the thinned-out or throttled clock signal can be supplied
`to electronic components, including the ALU 44, which
`are designed to accept an intermittent operation, while
`the thinned-out clock signal cannot be supplied to elec-
`tronic components, such as a cache snoop circuit 45,
`which are required to keep operating.
`[0035] A clock frequency determination circuit 47 is
`designed to generate a clock frequency determination
`signal in accordance with instructions issued from the
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`CPU 17. The clock frequency determination signal may
`include information for identifying the clock frequency of
`the clock signal. The clock generator unit 25 is designed
`to output the clock signal at the clock frequency identi-
`fied in the received clock frequency determination sig-
`nal. The clock frequency can be switched over between
`the maximum or highest frequency allowing the CPU 17
`to operate at the maximum operational speed and a low
`frequency set lower than the maximum frequency. When
`the CPU 17 operates in response to the clock signal of
`the low frequency, it is expected that heat generated at
`the CPU 17 can be suppressed as compared with the
`case where the CPU 17 operates at the maximum op-
`erational speed.
`[0036] An interrupt request generating circuit 48 is de-
`signed to generate an interrupt request signal INTR
`when it detects a rise to the high level or a drop to the
`low level in the notification signal issued from the tem-
`perature detector 18. The interrupt request signal INTR
`is supplied to the CPU 17. When the CPU 17 receives
`the interrupt request signal INTR, the CPU 17 is forced
`to interrupt the current processing so as to thereafter
`execute an interruption processing assigned to the in-
`terrupt request signal INTR. In place of the interrupt re-
`quest signal INTR, a SMI# signal (System Management
`Interrupt signal) of a higher priority can be employed to
`trigger the execution of the interruption processing in the
`CPU 17.
`[0037] A GPI (General Purpose Input) circuit 49 com-
`prises a register, not shown, designed to hold a binary
`data, namely, a value "0" or a value "1" in accordance
`with the presence of the alarm signal supplied from the
`fan controller unit 33. The CPU 17 is allowed to fetch
`the binary data out of the register. The fetched binary
`data may comprise a status information signal identify-
`ing the status of the cooling fan 32.
`[0038] Now, when the personal computer 10 is booted
`up, the CPU 17 starts to operate based on the OS read
`out of the HDD 27 and the BIOS read out of the flash
`memory 39. The CPU 17 is designed to cause the in-
`struction signal generating circuit 41 of the south bridge
`23 to output the fan instruction signal. If the CPU 17 ex-
`ecutes an application software under a heavy load, a
`greater amount of heat may be generated by the oper-
`ating CPU 17. The heat may be transferred to air sur-
`rounding the CPU 17. A temperature rise results in the
`confined space of the main enclosure 11. Rotation of the
`cooling fan 32 serves to generate air circulation between
`the interior and exterior of the main enclosure 11. The
`interior temperature of the main enclosure 11 is thus
`avoided from increasing too far.
`[0039] During the operation of the CPU 17, the tem-
`perature detector 18 keeps monitoring the actual tem-
`perature of the CPU 17. Assume that the measured ac-
`tual temperature of the CPU 17 exceeds the predeter-
`mined threshold temperature in response to the in-
`creased heat at the CPU 17. When the measured actual
`temperature has exceeded the level of the predeter-
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`the notification signal
`mined threshold temperature,
`generated at the temperature detector 18 is changed
`over from the low level to the high level. The interrupt
`request generating circuit 48 of the south bridge 23 out-
`puts the interrupt request signal INTR to the CPU 17 in
`response to the rise from the low level to the high level
`in the notification signal.
`[0040] The CPU 17 is then caused to interrupt the cur-
`rent primary processing in response to the received in-
`terrupt request signal INTR. Thereafter, the CPU 17
`starts to execute the interruption processing in accord-
`ance with the BIOS read out of the flash memory 39.
`When the CPU 17 executes the interruption processing,
`as shown in Fig. 4, the CPU 17 is designed to first de-
`termine whether the interrupt request signal INTR is out-
`put in response to the temperature, rise exceeding the
`threshold temperature or the temperature drop falling
`below the threshold temperature, at step S1, for exam-
`ple. The determination of the CPU 17 can be achieved
`by counting reception of the interrupt request signals IN-
`TR, for example, since the CPU 17 is only allowed to
`alternately receive the interrupt request signals INTR for
`temperature rises and drops. Otherwise, the determina-
`tion of the CPU 17 may be achieved by referring to the
`measured temperature at the temperature detector 18
`in response to reception of the interrupt request signal
`INTR.
`[0041] When the temperature rise has been recog-
`nized, the CPU 17 refers to the binary data of the register
`in the GPI circuit 49 at step S2. If the cooling fan 32
`normally operates, the value "0" has been established
`in the register of the GPI circuit 49. The CPU 17 is thus
`designed to instruct generation of a clock signal, thinned
`out at a low rate, for achieving the moderate suppres-
`sion of load at the CPU 17, at step S3. The instruction
`signal generating circuit 42 of the south bridge 23 gen-
`erates the clock-gate instruction signal STPCLK# iden-
`tifying the "10% thinned-out" in accordance with the in-
`struction issued from the CPU 17, for example. The gen-
`erated clock-gate instruction signal STPCLK# is sup-
`plied to the clock gate 43.
`[0042] The clock gate 43 outputs the thinned out or
`throttled clock signal, as shown in Fig. 5, for example,
`in response to reception of the clock-gate instruction sig-
`nal STPCLK#. The clock for 10% of a cyclic period is
`made ineffective in the thinned-out clock signal. Accord-
`ingly, the ALU 44 is allowed to alternately achieve the
`continuation and discontinuation of the operation in re-
`sponse to the supply of the effective and ineffective
`clock included in the thinned-out clock signal. The load
`to the ALU 44 can be suppressed to 90% of the maxi-
`mum load permissible to the ALU 44. Although the CPU
`17 operates at a low operational speed, heat generated
`at the CPU 17 can be suppressed. The thinned-out clock
`signal serves, in combination with a cooling perform-
`ance achieved by the cooling fan 32, to prevent the in-
`terior temperature of the main enclosure 11 from in-
`creasing. The CPU 17 then completes the interruption
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`processing. The CPU 17 is thereafter allowed to start a
`continuation of the interrupted primary processing.
`[0043] Referring again to Fig. 4, the CPU 17 is de-
`signed to fetch the value "1" from the register of the GPI
`circuit 49, at step S2, if the alarm signal is output from
`the fan controller unit 33. As a result, the CPU 17 detects
`a failure in the operation of the cooling fan 32. Other-
`wise, if the cooling fan 32 is intended to stop rotating so
`as to achieve suppression in energy consumption, the
`value "1" can be established in the register of the GPI
`circuit 49.
`[0044] When a failure has been found in the operation
`of the cooling fan 32 in the aforementioned manner, the
`CPU 17 is designed to instruct generation of a clock sig-
`nal, thinned out at a high rate, for achieving the tight or
`strong suppression of load at the CPU 17, at step S4.
`The instruction signal generating circuit 42 of the south
`bridge 23 generates the clock-gate instruction signal
`STPCLK# identifying the "30% thinned-out" in accord-
`ance with the instruction issued from the CPU 17, for
`example. The generated clock-gate instruction signal
`STPCLK# is supplied to the clock gate 43.
`[0045] The clock gate 43 outputs the thinned out or
`throttled clock signal, as shown in Fig. 5, for example,
`in response to reception of the clock-gate instruction sig-
`nal STPCLK#. The clock for 30% of a cyclic period is
`made ineffective in the thinned-out clock signal. Accord-
`ingly, the ALU 44 is allowed to alternately achieve the
`continuation and discontinuation of the operation in re-
`sponse to the supply of the effective and ineffective
`clock included in the thinned-out clock signal. The load
`on the ALU 44 can remarkably be suppressed to 70%
`of the maximum load permissible on the ALU 44. Heat
`generated at the CPU 17 can be greatly suppressed as
`compared with the case achieved by the aforemen-
`tioned 10% thinned-out clock signal. Without a cooling
`performance achieved by the cooling fan 32,
`the
`thinned-out clock signal solely serves to prevent the in-
`terior temperature of the main enclosure 11 from in-
`creasing. The CPU 17 then completes the interruption
`processing. The CPU 17 is thereafter allowed to start a
`continuation of the interrupted primary processing.
`[0046] Next, assume that a cooling performance
`achieved by the cooling fan 32 and/or the thinned-out
`clock signal sufficiently reduces the interior temperature
`of the main enclosure 11 during the continuation of the
`interrupted primary processing. When the measured ac-
`tual temperature has dropped below the predetermined
`threshold temperature, the notification signal generated
`at the temperature detector 18 is changed over from the
`high level to the low level. The interrupt request gener-
`ating circuit 48 of the south bridge 23 outputs the inter-
`rupt request signal INTR to the CPU 17 in response to
`the drop from the high level to the low level in the noti-
`fication signal.
`[0047] The CPU 17 is then caused to interrupt the cur-
`rent primary processing in response to the received in-
`terrupt request signal INTR. Thereafter, the CPU 17
`
`LENNOX EXHIBIT 1006
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 6
`
`

`

`11
`
`EP 1 085 399 B1
`
`12
`
`starts to execute the interruption processing in accord-
`ance with the BIOS read out of the flash memory 39.
`Here, when the temperature drop is recognized at step
`S1, the CPU is designed to instruct cancellation of the
`thinned-out clock signal without referring to the binary
`data of the register in the GPI circuit 49 at step S5. The
`instruction signal generating circuit 42 of
`the south
`bridge 23 generates the clock-gate instruction signal
`STPCLK# identifying the "0% thinned out," namely, the
`clock without being thinned out, in accordance with the
`instruction issued from the CPU 17. The generated
`clock-gate instruction signal STPCLK# is supplied to the
`clock gate 43. The clock gate 43 accordingly terminates
`the output of the thinned-out clock signal and starts out-
`putting the normal continuous clock signal. The CPU 17
`then completes the interruption processing. The CPU
`17 is thereafter allowed to start a continuation of the in-
`terrupted primary processing. The ALU 44 is expected
`to bear the maximum load during operation.
`[0048]
`In place of
`the aforementioned thinned-out
`clock signal, the interruption processing may employ the
`change in the clock frequency of the clock signal sup-
`plied to the CPU 17. As shown in Fig. 6, when the tem-
`perature rise has been recognized in the aforemen-
`tioned manner at step T1, in the same manner as de-
`scribed above, the CPU 17 is designed to refer to the
`binary data of t