I 1111111111111111 11111 111111111111111 IIIII IIIII IIIII IIIII IIIIII IIII 11111111
`US007268581Bl
`
`(10)Patent No.:US 7,268,581 Bl
`
`c12) United States Patent
`
`Sep.11,2007
`(45)Date of Patent:
`
`Trimberger et al.
`
`(54)FPGA WITH TIME-MULTIPLEXED
`INTERCONNECT
`
`
`
`
`5,581,199 A 12/1996 Pierce et al.
`5,682,107 A * 10/1997 Tavana et al ................. 326/41
`
`
`
`
`
`
`
`
`
`6,084,429 A * 7/2000 Trimberger .................. 326/41
`
`
`
`6,829,756 Bl 12/2004 Trimberger
`(75)Inventors: Stephen M. Trimberger, San Jose, CA
`
`
`
`
`
`
`7,012,448 B2 * 3/2006 Parkes ......................... 326/41
`
`
`(US); Austin H. Lesea, Los Gatos, CA
`(US)
`
`* cited by examiner
`
`
`
`(73)Assignee: Xilinx, Inc., San Jose, CA (US)
`Primary Examiner-James Cho
`
`
`
`Assistant Examiner-Jason Crawford
`
`
`
`
`
`( *) Notice: Subject to any disclaimer, the term of this
`
`
`
`
`
`
`
`
`patent is extended or adjusted under 35
`
`Paradice, III, Esq.
`U.S.C. 154(b) by 140 days.
`
`(74) Attorney, Agent, or Firm-Walter D. Fields; William L.
`
`
`
`(21) Appl. No.: 11/111,229
`
`(57)
`
`ABSTRACT
`
`(22)Filed:A pr. 21, 2005
`
`A programmable logic device (PLD) includes a plurality of
`
`
`
`
`
`
`configu rable resources, a programmable interconnect having
`
`
`
`a plurality of signal lines for providing a number of dedi­
`(51)Int. Cl.
`cated sign al paths between any of the configurable
`G06F 7138 (2006.01)
`
`
`resources, and a subway routing system having a shared
`H03K 191173(2006.01)
`
`
`subway bus coupled to the signal lines of the programmable
`
`
`
`(52)U.S. Cl. ............................. 326/38; 326/41; 326/47
`
`
`
`
`interconnect at a plurality of connection points by a plurality
`
`
`(58)Field of Classification Search ............. 326/37-47
`
`
`
`of corresponding subway ports. The subway routing system,
`
`
`
`See application file for complete search history.
`
`
`
`
`which provides alternate routing resources for the program­
`
`
`mable interconnect, may be used to route different signals
`
`
`
`
`different times. between different configu rable resources at
`
`(56)
`
`
`
`References Cited
`
`
`
`U.S. PATENT DOCUMENTS
`
`5,498,975 A * 3/1996 Cliff et al. .................... 326/10
`
`19 Claims, 7 Drawing Sheets
`
`
`
`
`
`
`400
`�
`
`410
`
`20
`
`L4
`
`--------------
`
`(, ____________________
`
`________
`
`421
`302
`
`212
`
`Input
`registers
`412
`
`231
`Output
`Latch
`422
`
`TS_Tx
`Transmit
`CLK_TM
`logic
`EN_Tx
`423
`
`EN_Rx
`Receive
`CLK_TM
`logic
`TS_Rx
`428
`
`212
`Output
`latches
`414
`
`302
`
`231
`Capture
`CKT
`427
`
`426
`
`Emerson Exhibit 1041
`Emerson Electric v. Ollnova
`IPR2023-00626
`Page 00001
`
`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 1 0f 7
`
`US 7,268,581 B1
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`100
`
`140
`
`110
`
`2
`
`C
`
`2
`
`IOB 120 IOB IOB 130 IOB
`,/
`2
`IOB CLB
`
`IOB
`
`IOB IOB
`
`IOB
`
`C
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`IOB CLB BRAM CLB CLB BRAM CLB CLB BRAM CLB CLB BRAM CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CQLB
`
`CLB CLB
`
`CLB IOB
`
`CLB IOB
`CLB CLB uP CLB CLB
`IOB CLB uP CLB CLB
`core
`BRAM
`core
`BRAM
`IOB CLB 1_5_0_ CLB CLB
`CLB CLB 15_o CLB CLB
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`CLB CLB uP CLB IOB
`CLB CLB UP CLB CLB
`IOB CLB
`BRAM
`core
`BRAM
`core
`IOB CLB
`CLB CLB @ CLB CLB
`CLB CLB 1519 CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`CLB IOB
`CLB CLB
`CLB CLB
`CLB CLB
`IOB CLB
`BRAM
`BRAM
`BRAM
`BRAM
`IOB CLB
`CLB CLB
`CLB CLB
`CLB CLB
`CLB IOB
`
`IOB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB CLB
`
`CLB IOB
`
`C
`
`IOB JTAG IOB IOB
`/
`160
`
`IOB IOB
`
`IOB IOB
`
`IOB
`
`C
`
`FIG.1
`
`IPR2023-00626 Page 00002
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`

`

`U.S. Patent
`
`Sep. 11, 2007
`
`Sheet 2 of 7
`
`US 7,268,581 B1
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`ES iy!eyAa Pitalyei= E*
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`
`104Y
`
`IPR2023-00626 Page 00003
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`IPR2023-00626 Page 00003
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`

`

`U.S. Patent
`
`Sep. 11, 2007
`
`Sheet 3 of 7
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`US 7,268,581 B1
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`a
`302
`212
`
`
`
`Subway
`Interconnect
`Interface
`Interface
`
`
`
`
`
`
`310
`320
`
`
`
`Signal
`
`Generator
`
`
`330
`
`231
`
`registers
`412
`
`
`
`
`
`Transmit
`
`logic
`423
`
`
`Receive
`
`logic
`428
`
`Capture
`CKT
`427
`
`IPR2023-00626 Page 00004
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`IPR2023-00626 Page 00004
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`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 4 0f 7
`
`US 7,268,581 B1
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`500\'\
`
`Compare Logic
`
`CNT
`Counter
`CLK TM
`- —> 502 —_> Memory
`—
`cells
`512
`
`Compare
`CKT
`Q
`
`TS—TX
`
`’ EN—TX
`
`550“
`
`Compare Logic
`560 —
`CNT
`Counter
`CLK_TM—> 552 ————> Memory
`Compare
`'_
`cells
`CKT ——> EN-RX
`@ @
`
`——>TS Rx
`—
`
`900“
`
`Processor
`9.32
`
`Subway
`<__—’ ports and ‘
`bus
`m
`
`>
`
`M
`emo
`'V
`m
`
`FIG. 9
`
`IPR2023-00626 Page 00005
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`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 5 0f 7
`
`US 7,268,581 B1
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`600
`
`700
`
`212
`
`FIG. 6
`
`Routing
`Logic
`Z19
`
`Data/DA
`
`702
`
`Ordering
`Logic
`7_20
`
`302
`
`FIG. 7A
`
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`
`p
`
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`CKT
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`
`DATA
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`
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`.m Wm? g mC7
`
`m
`
`SEL
`FIG. 75
`
`IPR2023-00626 Page 00006
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`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 6 0f 7
`
`US 7,268,581 B1
`
`800 \
`
`Analyze netlist for low /— 801
`performance signals
`
`l
`
`Identify and group nets
`associated with the low
`performance signals to form a
`sub-netlist
`
`/" 802
`
`l
`
`Modify netlist to exclude sub- /- 303
`netlist
`
`l
`
`Place and route components /- 804
`and signals associated with the
`modified netlist
`
`l
`
`Place and route signals /- 805
`associated with the sub-netlist
`
`l
`
`Select suitable phase for the /— 806
`time multiplexed control signal
`
`FIG. 8
`
`IPR2023-00626 Page 00007
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`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 7 0f 7
`
`US 7,268,581 B1
`
`1000 \
`
`Analyze netlist for low K- 1001
`performance signals
`
`l
`
`Identify and group nets
`associated with the low
`performance signals to form a
`sub-netlist
`
`l
`
`Modify netlist to exclude sub- /- 1003
`netlist
`
`l
`
`Place and route components /- 1004
`and signals associated with the
`modified netlist
`
`l
`
`Construct program executable /- 1005
`by the processor to implement
`selected logic in the sub-netlist
`
`l
`
`Place and route remaining /- 1006
`signals in the sub-netlist
`
`l
`
`Select suitable phase for the f- 1007
`time multiplexed control signal
`
`FIG. 10
`
`IPR2023-00626 Page 00008
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`

`

`US 7,268,581 B1
`
`1
`FPGA WITH TIME-MULTIPLEXED
`INTERCONNECT
`
`2
`and exhibits more routing e?iciencies than those provided
`by prior PLD signal routing techniques.
`
`FIELD OF INVENTION
`
`SUMMARY
`
`This invention relates generally to signal routing
`resources in a programmable logic device (PLD), and in
`particular to a PLD having a programmable interconnect and
`having a separate subway routing system that may be used
`to bypass corresponding portions of the programmable inter
`connect.
`
`DESCRIPTION OF RELATED ART
`
`A programmable logic device (PLD) is a Well-known
`general-purpose device that can be programmed by a user to
`implement a variety of selected functions. PLDs are becom
`ing increasingly popular With circuit designers because they
`are less expensive, more ?exible, and require less time to
`implement than custom-designed integrated circuits such as
`Application Speci?c Integrated Circuits (ASICs).
`There are many types of PLDs such as Field Program
`mable Gate Arrays (FPGAs) and complex PLDs (CPLDs).
`For example, an FPGA typically includes an array of con
`?gurable logic blocks (CLBs) surrounded by a plurality of
`input/output blocks (IOBs). The CLBs are individually
`programmable and can be con?gured to perform a variety of
`logic functions including, for example, logic in lookup
`tables (LUTs) and storage in ?ip-?ops or latches. The IOBs
`are selectively connected to various I/O pins of the FPGA,
`and can be con?gured as either input bu?ers or output
`buffers. The FPGA may also include tri-state bu?ers that
`users may use to share routing Wires. The FPGA has a
`con?gurable routing structure called a programmable inter
`connect for interconnecting the CLBs and IOBs according to
`the desired user circuit design. The FPGA also includes a
`number of con?guration memory cells that control the logic
`functions implemented by the CLBs and that designate
`speci?c signal routing paths in the programmable intercon
`nect to selectively interconnect the various CLBs and IOBs.
`The functionality of an FPGA may be increased by
`increasing the number of CLBs and the number of signal
`lines in the programmable interconnect. HoWever, for any
`given semiconductor fabrication technology, there are limi
`tations to the siZe of the programmable interconnect and to
`the number of CLBs that can be fabricated on an integrated
`circuit chip of practical siZe. Thus, there is a continuing
`desire to implement more CLBs and more complex pro
`grammable interconnects in less circuit area. More speci?
`cally, because the chip area of a PLD is typically dominated
`by its programmable interconnect, prior techniques have
`been proposed to increase the routing capabilities of the
`programmable interconnect. For example, US. Pat. No.
`6,829,754 to Trimberger, Which is incorporated herein by
`reference, discloses a technique for time multiplexing
`selected portions of a PLD’s programmable interconnect so
`that data may be routed on shared portions of the program
`mable interconnect at different times to different destina
`tions.
`HoWever, because a PLD’s programmable interconnect is
`designed to accommodate the most time-critical signals of
`numerous possible user designs that may be implemented by
`the PLD, the programmable interconnect typically consumes
`a signi?cant amount of silicon area of the PLD, and typically
`exhibits limited signal routing ?exibility. Therefore, there is
`a need for a PLD routing structure that offers more ?exibility
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`A method and apparatus are disclosed that provide a more
`?exible and more e?icient signal routing structure suitable
`for use in a PLD. In accordance With an embodiment of the
`present invention, a PLD includes a plurality of con?gurable
`resources, a programmable interconnect, and a separate
`subWay routing system. The programmable interconnect
`includes a plurality of signal lines that may provide dedi
`cated signal paths betWeen any of the con?gurable
`resources. The subWay routing system includes a shared
`subWay bus that is coupled to the programmable intercon
`nect’s signal lines at various interconnection points by a
`plurality of corresponding subWay ports. The subWay bus,
`Which is con?gured to route data between different subWay
`ports at different times, supplements the signal routing
`capability of the programmable interconnect. For example,
`data that is routed betWeen various con?gurable resources of
`the PLD via the subWay bus bypasses corresponding signal
`line portions of the programmable interconnect, thereby
`alloWing the corresponding signal line portions of the pro
`grammable interconnect to provide dedicated signal paths
`betWeen other con?gurable resources.
`For some embodiments, the programmable interconnect
`may provide dedicated signal paths suitable routing for high
`performance signals, and the subWay routing system may
`provide shared signal paths suitable for routing loW perfor
`mance signals. Accordingly, for such embodiments, the
`programmable interconnect may be used to route time
`critical signals across the PLD, and the subWay routing
`system may be used to time multiplex non-time critical
`signals across the PLD, thereby relieving routing demands
`on the programmable interconnect, Which in turn may alloW
`for a reduction in siZe of the programmable interconnect
`Without any performance degradation.
`For example, a netlist embodying a user design may be
`analyZed for loW performance signals. The nets associated
`With the loW performance signals may be identi?ed and
`grouped together to form a sub-netlist, Which in turn is
`removed from the original netlist to form a modi?ed netlist
`that includes various high performance signals suitable for
`routing over the PLD’s programmable interconnect. The
`design embodied by the modi?ed netlist may be mapped to
`the con?gurable resources of the PLD, and the high perfor
`mance signals associated With the modi?ed netlist may be
`routed using the PLD’s programmable interconnect. Then,
`the loW performance signals associated With the sub-netlist
`may be placed and routed on the subWay routing system,
`Which may use time-multiplexing techniques to route vari
`ous loW performance signals between different PLD
`resources at different times Without any performance deg
`radation. Accordingly, by using the programmable intercon
`nect to provide dedicated signal paths for high performance
`signals and using the subWay routing system to time
`multiplex a plurality of loW performance signals, embodi
`ments of the present invention may provide a routing
`structure that provides more ?exibility and exhibits superior
`e?iciency than prior PLD routing techniques.
`For some embodiments, data selected for routing over the
`subWay routing system may be assigned corresponding time
`slots and transmitted betWeen corresponding portions of the
`PLD Without using destination addresses. For example, for
`each time slot, the subWay ports associated With routing
`corresponding data over the subWay bus may be enabled to
`
`IPR2023-00626 Page 00009
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`

`

`US 7,268,581 B1
`
`3
`transmit data to and receive data from the subway bus, and
`the subway ports not associated With the corresponding data
`may be disabled from transmitting data to and receiving data
`from the subWay bus.
`For other embodiments, data may be routed over the
`subWay routing system using destination addresses, Which in
`turn may avoid potential performance degradation or failure
`resulting from imprecise time slot synchronization betWeen
`the various subWay ports of the subWay routing system. For
`example, each subWay port may be programmed to attach a
`predetermined destination address for data received from a
`corresponding signal path of the programmable interconnect
`and programmed to receive data from the subWay bus
`having designated destination addresses.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The features and advantages of the present invention are
`illustrated by Way of example and are by no means intended
`to limit the scope of the present invention to the particular
`embodiments shoWn, and in Which:
`FIG. 1 is a block diagram illustrating the general layout of
`an FPGA Within Which embodiments of the present inven
`tion may be implemented;
`FIG. 2 is simpli?ed block diagram depicting a portion of
`the FPGA of FIG. 1 including a subWay routing system in
`accordance With some embodiments of the present inven
`tion;
`FIG. 3 is a block diagram of a subWay port of FIG. 2 in
`accordance With some embodiments of the present inven
`tion;
`FIG. 4 is a block diagram of one embodiment of the
`subWay port of FIG. 3;
`FIG. 5A is a block diagram of one embodiment of the
`interconnect interface of the subWay port of FIG. 4;
`FIG. 5B is a block diagram of one embodiment of the
`subWay interface of the subWay port of FIG. 4;
`FIG. 6 is a block diagram of another embodiment of the
`subWay port of FIG. 3;
`FIG. 7A is a block diagram of one embodiment of the
`interconnect interface of the subWay port of FIG. 6;
`FIG. 7B is a block diagram of one embodiment of the
`subWay interface of the subWay port of FIG. 6;
`FIG. 8 is a How chart illustrating an exemplary operation
`for con?guring one embodiment of the subWay routing
`system of FIG. 2;
`FIG. 9 is a block diagram of a subWay routing system in
`accordance With another embodiment of the present inven
`tion; and
`FIG. 10 is a How chart illustrating an exemplary operation
`of the subWay routing system of FIG. 9.
`Like reference numerals refer to corresponding parts
`throughout the draWing ?gures.
`
`DETAILED DESCRIPTION
`
`Embodiments of the present invention are described
`beloW With respect to an exemplary FPGA architecture that
`is generally representative of the Virtex-II ProTM family of
`FPGA devices from Xilinx, Inc. for simplicity only. It is to
`be understood that embodiments of the present invention are
`equally applicable to other FPGA architectures and to other
`integrated circuits (ICs), including programmable logic
`devices such as complex PLDs. In the folloWing description,
`for purposes of explanation, speci?c nomenclature is set
`forth to provide a thorough understanding of the present
`invention. In other instances, Well-known circuits and
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`devices are shoWn in block diagram form to avoid obscuring
`the present invention. Further, the logic levels assigned to
`various signals in the description beloW are arbitrary and,
`thus may be modi?ed (e.g., reversed polarity) as desired.
`Accordingly, the present invention is not to be construed as
`limited to speci?c examples described herein but rather
`includes Within its scope all embodiments de?ned by the
`appended claims.
`FIG. 1 illustrates the general layout of an FPGA 100 that
`is generally representative and consistent With the Virtex-II
`ProTM FPGA family of FPGA devices available from Xilinx,
`Inc. FPGA 100 is shoWn to include a plurality of IOBs 110,
`CLBs 120, block RAMs (BRAM) 130, comer blocks 140,
`processor (uP) cores 150, and JTAG test circuitry 160. IOBs
`110 are Well-known, and are located around the perimeter of
`FPGA 100. CLBs 120 are Well-known, and may be arranged
`in columns in FPGA 100. BRAMs 130 are Well-known, and
`may be arranged in columns betWeen adjacent CLB col
`umns. Comer blocks 140 are Well-known, and may contain
`con?guration circuitry and/or may be used to provide addi
`tional routing resources. Processor cores 150, Which are
`Well-known and are depicted in the exemplary embodiment
`of FIG. 1 as lying Within corresponding BRAM columns,
`have direct access to adjoining BRAMs 130 and CLBs 110.
`A Well-known programmable interconnect (not shoWn in
`FIG. 1 for simplicity) is provided to programmably connect
`the IOBs 110, CLBs 120, block RAMs 130, corner blocks
`140, and processor cores 150. For some embodiments, the
`programmable interconnect also facilitates communication
`betWeen processor cores 150 and external memory (not
`shoWn for simplicity) that stores information (e.g., data,
`instructions, and the like) for use by processor cores 150.
`JTAG test circuitry 160 is Well-known, and may be used to
`con?gure FPGA 100 and to implement various testing
`operations for FPGA 100.
`The IOBs 110, CLBs 120, block RAM 130, corner blocks
`140, and the programmable interconnect each contain one or
`more con?gurable elements (not shoWn in FIG. 1 for sim
`plicity) that con?gure FPGA 100 to implement a desired
`function in response to con?guration data stored in associ
`ated con?guration memory cells (not shoWn in FIG. 1 for
`simplicity). Other Well-known components of FPGA 100 are
`not shoWn in FIG. 1 for simplicity.
`Further, although a particular FPGA layout is illustrated in
`FIG. 1, it is to be understood that many other FPGA layouts
`are possible, and are considered to fall Within the scope of
`the present invention. For example, other embodiments may
`have other numbers of IOBs 110, CLBs 120, block RAMs
`130, and processor cores 150 provided in different arrange
`ments, and/or may have other types of blocks. A more
`detailed description of the general operation of FPGA 100 is
`provided in “The Programmable Logic Databook 1998” pp.
`4-1 to 4-40, Which is available from Xilinx, Inc. of San Jose,
`Calif., and incorporated by reference herein.
`FIG. 2 shoWs an exemplary portion 200 of FPGA 100 in
`more detail. FPGA portion 200 is shoWn to include an array
`of CLB tiles 210, each including a CLB 104, a sWitch matrix
`211, and a plurality of signal lines 212 connected betWeen
`corresponding I/O ports of CLB 104 and sWitch matrix 211.
`SWitch matrix 211, Which is Well-known, is coupled to
`signal lines 222 via a corresponding programmable inter
`connect point (PIP) 213, Which is Well-known. For some
`embodiments, sWitch matrix 211 is of the type disclosed in
`US. Pat. No. 6,292,022 to Young et al., Which is incorpo
`rated herein by reference, although other sWitch matrices
`may be used. Further, each sWitch matrix 211 may include
`
`IPR2023-00626 Page 00010
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`

`

`US 7,268,581 B1
`
`5
`a number of PlPs for coupling the switch matrix to a number
`of adjacent sWitch matrices via corresponding signal lines
`221.
`Signal lines 221, Which extend across one CLB tile to
`connect sWitch matrices 211 in adjacent CLB tiles 210, are
`commonly knoWn as single-length lines. Signal lines 222,
`Which extend across multiple CLB tiles and may be used to
`route signals betWeen non-adjacent CLB tiles, are represen
`tative of intermediate length lines (e.g., such as double
`length lines, quad-length lines, hex-length lines, and so on)
`and long lines (e.g., such as global lines that extend across
`an entire roW or column of the FPGA). Together, PlPs 213
`and signal lines 221-222 form the programmable intercon
`nect of FPGA portion 200. For simplicity, each of signal
`lines 212, 221, and 222 shoWn in FIG. 2 is representative of
`a plurality of single-bit and/or multi-bit signal lines.
`As knoWn in the art, the programmable interconnect
`provides dedicated circuit-sWitched connections betWeen
`corresponding FPGA resources for each signal selected for
`routing over the programmable interconnect. For some
`embodiments, the programmable interconnect may be of the
`type disclosed in US. Pat. No. 5,469,003 to Kean, Which is
`incorporated herein by reference. For other embodiments,
`the tile-based interconnect structure disclosed in US. Pat.
`No. 5,581,199 to Pierce, Which is incorporated herein by
`reference, may be used. For still other embodiments, other
`suitable programmable interconnect circuitry may be used.
`Further, although not shoWn in FIG. 2 for simplicity, FPGA
`200 may include direct signal lines connected betWeen
`adjacent CLB tiles so that data may be exchanged betWeen
`adjacent CLBs 104 Without using the programmable inter
`connect.
`In an embodiment of the present invention, FPGA 200
`includes a subWay routing system including a plurality of
`subWay ports 230A-230D and a subWay bus 231. Each of
`subWay ports 230A-230D includes a ?rst interface coupled
`to the programmable interconnect via a corresponding
`sWitch matrix 232A-232D, and includes a second interface
`coupled to subWay bus 231. For purposes of discussion
`herein, sWitch matrices 232 are of the same architecture as
`sWitch matrices 211, although for actual embodiments
`sWitch matrices 232 may be different than sWitch matrices
`211. For other embodiments, subWay ports 230A-230D may
`be connected directly to the programmable interconnect,
`thereby eliminating the need for corresponding sWitch matri
`ces 232A-232D. For still other embodiments, one or more of
`subWay ports 230 may be connected directly to correspond
`ing CLB tiles 210.
`For simplicity, other con?gurable resources such as IOB
`tiles and comer blocks, as Well as block RAM, embedded
`processor cores, JTAG circuitry, and other Well-knoWn
`FPGA elements, are not shoWn in FIG. 2. Thus, although
`described beloW as routing data betWeen CLB tiles 210, for
`some embodiments, the subWay routing system may be used
`to route data to and from other FPGA resources including,
`for example, lOBs, block RAM, embedded processor cores,
`JTAG circuitry, and so on.
`As explained in detail beloW, the subWay routing system
`of one embodiment of the present invention alloWs data to
`be transmitted across portions of the FPGA Without using
`the programmable interconnect, thereby freeing correspond
`ing portions of the programmable interconnect for other
`routing functions. As knoWn in the art, the programmable
`interconnect achieves high performance by providing dedi
`cated circuit-sWitched signal paths betWeen various FPGA
`65
`resources. Thus, for some embodiments, the programmable
`interconnect may be used to route high performance signals
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`(e.g., time critical signals having minimal timing slack), and
`the subWay routing system may be used to route loW
`performance signals (e.g., non-time critical signals having
`greater timing slack than the time critical signals). In accor
`dance With some embodiments of the present invention,
`signals routed over the subWay routing system may be time
`multiplexed so that common sections of the subWay routing
`system may be used at different times to transmit data
`betWeen different resources of FPGA 200, thereby maximiZ
`ing bandWidth of the subWay routing system.
`Although only four subWay ports 230 are shoWn in FIG.
`2 for simplicity, actual embodiments of FPGA 200 may
`include any number of subWay ports 230. Further, the
`particular arrangement of subWay ports 230 depicted in FIG.
`2 is exemplary. For actual embodiments, subWay ports 230
`may be provided in any suitable arrangement across FPGA
`200. Thus, for some embodiments, subWay ports 230 may be
`arranged in a ?xed pattern across FPGA 200, for example,
`as depicted in the exemplary embodiment of FIG. 2. For
`other embodiments, subWay ports 230 may be provided in a
`non-regular arrangement so that subWay ports 230 are
`provided near the FPGA resources that are most likely to
`utiliZe the subWay routing system (e.g., near resources
`associated With loW performance signals). For example,
`referring also to FIG. 1, for actual embodiments, subWay
`ports 230 may be provided near lOBs 110 and embedded
`processor cores 150 because of relatively large latencies
`typically associated With lOBs 110 and processor cores 150.
`FIG. 3 shoWs a subWay port 300 that is one embodiment
`of subWay port 230 of FIG. 2. SubWay port 300 includes an
`interconnect interface 310 and a subWay interface 320
`coupled together via a plurality of signal lines 302. Referring
`also to FIG. 2, interconnect interface 310 is coupled to a
`plurality of signal line outputs of an associated sWitch matrix
`232 via a plurality of corresponding signal lines 212, and for
`some embodiments includes a control terminal to receive a
`time-multiplexed clock signal CLK_TM provided by a
`signal generator 330. SubWay interface 320 is coupled to
`subWay bus 231, and includes a control terminal to receive
`CLK_TM. As described in more detail beloW, interconnect
`interface 310 controls the transfer of data betWeen subWay
`port 300 and the programmable interconnect via its associ
`ated sWitch matrix 232, and subWay interface 320 controls
`the transfer of data betWeen subWay port 300 and subWay
`bus 231.
`For some embodiments, interconnect interface 310 pro
`vides a signal path betWeen corresponding pairs of signal
`lines 212 and 302, for example, so that data provided from
`a signal line output of associated sWitch matrix 232 via a
`corresponding signal line 212 is routed through interconnect
`interface 310 onto a corresponding signal line 302. Further,
`subWay interface 320 may be con?gured to identify Which
`signals provided on the subWay bus 231 are to be captured
`by subWay port 300 and routed to a designated signal line of
`the programmable interconnect via a corresponding signal
`path provided by the associated sWitch matrix 232, signal
`line 212, and interconnect interface 310.
`Signal generator 330 may be any suitable signal genera
`tor. For some embodiments, signal generator 330 may
`generate CLK_TM in response to an FPGA system clock
`(not shoWn for simplicity). For one embodiment, signal
`generator 330 may use the system clock as CLK_TM. For
`another embodiment, signal generator 330 may generate
`CLK_TM to have a frequency that is some fraction or
`multiple of the frequency of the system clock. As explained
`beloW, CLK_TM may be used to control the transfer of data
`betWeen different con?gurable resources (e. g., such as CLBs
`
`IPR2023-00626 Page 00011
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`US 7,268,581 B1
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`7
`104) of FPGA 200 over the shared subway bus 231 using
`suitable time-multiplexing techniques. In this manner, a
`plurality of signals may share the common routing resources
`of the subWay routing system to maximize the signal routing
`capability of the subWay routing system, Which in turn may
`minimize routing demands upon the programmable inter
`connect. Further, the selection of Which signals associated
`With a user design are to be routed over the subWay bus 231
`and the subsequent placement of these signals on the subWay
`routing system may be performed in a manner that is
`transparent to the end user.
`As mentioned above, for some embodiments, the subWay
`routing system may be utiliZed for routing loW performance
`signals, and the programmable interconnect may be utiliZed
`for routing high performance signals. More speci?cally, for
`some embodiments, a user design may be analyZed to
`identify a number of loW performance signals that may be
`routed over the subWay routing system, thereby bypassing
`corresponding portions of the programmable interconnect.
`For example, FIG. 8 is a How chart illustrating one
`embodiment for time multiplexing selected loW perfor
`mance signals associated With a user design on the subWay
`routing system of FPGA 200. First, a netlist embodying a
`user design is analyZed for loW performance signals, Which
`may comprise complete nets or subnets of the connections
`(e.g., destinations) of nets (step 801). For some embodi
`ments, the performance of the user design may be estimated
`using Well-known static timing analysis to identify the loW
`performance signals as signals that are not time critical, for
`example, by identifying those signals that have the greatest
`amount of timing slack. Next, the nets associated With the
`loW performance signals are identi?ed and grouped together
`to form a sub-netlist (step 802). For some embodiments,
`routing performance of the loW performance signals embod
`ied by the sub-netlist over the subWay routing system may
`be estimated using suitable simulation tools. Then, the
`original netlist is modi?ed to exclude the sub-netlist asso
`ciated With the identi?ed loW performance signals (step
`803).
`The modi?ed netlist is then placed and routed using
`conventional techniques (step 804). For example, as knoWn
`in the art, the structural components of the user design may
`be mapped to various con?gurable resources (e.g., such as
`CLB tiles 210) of the FPGA, and the signals associated With
`the modi?ed netlist may be routed using the FPGA’s pro
`grammable interconnect. Then, the signals associated With
`the sub-netlist may be placed and routed upon the subWay
`routing system (step 805). Thus, for each net omitted from
`the original netlist, a signal may be routed from the net’s
`source to a ?rst subWay port, from the ?rst subWay port to
`a second subWay port over the subWay bus, and then from
`the second subWay port to the destination. The subWay port
`may be selected in a manner that simpli?es signal routing
`and/or that eases routing congestion. When feasible, nets
`omitted from original netlist may be routed over the pro
`grammable interconnect, thereby avoiding the subWay rout
`ing system.
`Finally, a suitable phase of the time multiplexed clock
`signal CLK_TM is selected to control the transmission of
`signals across the shared subWay bus 231 (step 806). For
`some embodiments, CLK_TM may be properly timed to
`ensure that propagation delays of signals routed over the
`subWay routing system are matched to their intended desti
`nations. For example, for some embodiments, CLK_TM
`may be varied as needed so that each signal is received at its
`destination at the appropriate time. For other embodiments,
`the maximum speed of CLK_TM may be timed based on the
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`sloWest signal that is to be routed over the subWay routing
`system. Further, if time critical signals are not routed on the
`subWay routing system, then CLK_TM need not run faster
`than the system clock, thereby easing performance con
`straints on the FPGA. Conversely, if time critical signals are
`routed on the subWay routing system, then CLK_TM may
`run faster than the system clock. Further, for some embodi
`ments, the process How depicted in FIG. 8 may also include
`a scheduling step that assigns a time slot for each signal.
`For other embodiments, the process How described above
`With respect to FIG. 8 may be modi?ed to ensure that the
`subWay routing system is used in a manner that maximiZes
`the signal routing ef?ciencies of the programmable inter
`connect and the subWay routing system. For example, pro
`cessing step 804 of FIG. 8 may be modi?ed so that the CLBs
`104 are placed ?rst, and then before the signals are routed,
`signals associated With loW performance logic and/or signals
`that are routed long distances across