U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG ELECTRONICS AMERICA, INC., and QUALCOMM, INC.,
`Petitioners
`
`v.
`
`DAEDALUS PRIME LLC,
`Patent Owner.
`
`________________________
`
`Case No. IPR2023-00567
`U.S. Patent No. 10,049,080
`_______________________
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 10,049,080
`
`
`
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`
`
`Page
`
`
`INTRODUCTION .......................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES UNDER 37 C.F.R. §42.8 ................................... 1 
`III.  GROUNDS FOR STANDING ....................................................................... 4 
`IV.  FEE AUTHORIZATION ............................................................................... 4 
`V. 
`PRECISE RELIEF REQUESTED ................................................................. 4 
`VI.  THE CHALLENGED PATENT .................................................................... 5 
`VII.  PROSECUTION HISTORY .......................................................................... 7 
`VIII.  THERE IS NO BASIS FOR DISCRETIONARY DENIAL ......................... 8 
`A. 
`Advanced Bionics Part I ....................................................................... 8 
`B. 
`Advanced Bionics Part II .................................................................... 11 
`C.  Mathieson and Sutardja Render Claims 1, 4, 7-9, 12, 15-17, 20,
`and 23-24 Unpatentable ..................................................................... 12 
`IX.  LEVEL OF ORDINARY SKILL IN THE ART .......................................... 13 
`X. 
`PRIORITY DATE ........................................................................................ 13 
`XI.  CLAIM CONSTRUCTION ......................................................................... 14 
`XII.  BRIEF DESCRIPTION OF THE APPLIED PRIOR ART
`REFERENCES ............................................................................................. 14 
`A.  Mathieson (Ex-1005) .......................................................................... 14 
`B. 
`Carmack (Ex-1006) ............................................................................ 15 
`C. 
`Sutardja (Ex-1007, Ex-1008) ............................................................. 17 
`D. 
`Rychlik (Ex-1009) .............................................................................. 17 
`XIII.  DETAILED EXPLANATION OF THE UNPATENTABILITY
`GROUNDS ................................................................................................... 19 
`A.  Ground 1: Claims 1-4, 7-12, 15-20, 23-24 Are Rendered Obvious
`By Sutardja (Ex-1007, Incorporating Ex-1008) ................................. 19 
`1. 
`Independent Claim 1 ................................................................ 19 
`a. 
`Element 1[preamble]: A multi-core processor
`comprising: .................................................................... 19 
`
`i
`
`

`

`
`
`2. 
`
`3. 
`
`4. 
`
`5. 
`
`TABLE OF CONTENTS
`(continued)
`
`Page
`
`b. 
`
`c. 
`
`d. 
`
`e. 
`
`Element 1[a][i]: a first plurality of cores and a
`second plurality of cores that support a same
`instruction set, ................................................................ 20 
`Element 1[a][ii]: wherein the second plurality of
`cores consume less power, for a same applied
`operating frequency and supply voltage, than the
`first plurality of cores; and ............................................. 23 
`Element 1[b][i]: power management hardware to,
`from a state where the first plurality of cores and
`the second plurality of cores are enabled, disable
`all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of
`the second plurality of cores, ......................................... 24 
`Element 1[b][ii]: wherein an operating system to
`execute on the multi-core processor is to monitor a
`demand for the multi-core processor and control
`the power management hardware based on the
`demand. .......................................................................... 31 
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that have narrower logic gate driver transistors than
`corresponding logic gates of the first plurality of cores. ......... 33 
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that consume less power than corresponding logic gates of
`the first plurality of cores. ........................................................ 34 
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a
`maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of
`cores. ........................................................................................ 35 
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum
`operating frequency in the state. .............................................. 35 
`
`ii
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`6. 
`
`7. 
`
`b. 
`
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ..................................................................................... 36 
`a. 
`Element 8[a]: the power management hardware is
`to enable all of the first plurality of cores for an
`increase in demand above the threshold without
`disabling any of the second plurality of cores, .............. 36 
`Element 8[b]: wherein an operating system is to
`monitor a demand for the multi-core processor and
`control the power management hardware based on
`the demand. .................................................................... 39 
`Independent Claims 9 and 17: .................................................. 40 
`a. 
`Element 9[preamble]: A method comprising: ............... 40 
`b. 
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that
`when processed by a machine causes a method to
`be performed, the method comprising: .......................... 40 
`Elements 9[a][i] and 17[a][i]: operating a multi-
`core processor such that a first plurality of cores
`and a second plurality of cores execute a same
`instruction set, ................................................................ 40 
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same
`applied operating frequency and supply voltage,
`than the first plurality of cores; and ............................... 40 
`Elements 9[b][i] and 17[b][i]: disabling with
`power management hardware, from a state where
`the first plurality of cores and the second plurality
`of cores are enabled, all of the first plurality of
`cores for a drop in demand below a threshold
`without disabling any of the second plurality of
`cores, .............................................................................. 41 
`
`c. 
`
`d. 
`
`e. 
`
`iii
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`f. 
`
`8. 
`
`9. 
`
`Element 9[b][ii] and 17[b][ii]: wherein an
`operating system executing on the multi-core
`processor monitors a demand for the multi-core
`processor and controls the power management
`hardware based on the demand. ..................................... 41 
`Dependent Claims 10 and 18: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first
`plurality of cores. ..................................................................... 41 
`Dependent Claims 11 and 19: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that consume less power than
`corresponding logic gates of the first plurality of cores. ......... 41 
`10.  Dependent Claims 12 and 20: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the second plurality of
`cores at a maximum operating frequency that is less than
`a maximum operating frequeny of the first plurality of
`cores. ........................................................................................ 42 
`11.  Dependent Claims 15 and 23: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. ............. 42 
`12.  Dependent Claims 16 and 24: The [method of claim 9/non-
`transitory machine readable medium of claim 17], further
`comprising ................................................................................ 42 
`a. 
`Elements 16[a] and 24[a]: enabling, with the
`power management hardware, all of the first
`plurality of cores for an increase in demand above
`the threshold without disabling any of the second
`plurality of cores, ........................................................... 42 
`
`iv
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`B. 
`
`C. 
`
`2. 
`
`b. 
`
`b. 
`
`Elements 16[b] and 24[b]: wherein an operating
`system is to monitor a demand for the multi-core
`processor and control the power management
`hardware based on the demand. ..................................... 42 
`Ground 2: Claims 5-6, 13-14, and 21-22 Are Rendered Obvious
`By Sutardja/Rychlik ........................................................................... 43 
`1. 
`Dependent Claims 5, 13, and 21: ............................................. 43 
`a. 
`Elements 5[a], 13[a], 21[a]: The [multi-core
`processor of claim 1/method of claim 9/non-
`transitory machine readable medium of claim 17],
`[wherein the power management hardware is to
`disable/further comprising disabling, with the
`power management hardware,] an additional core
`of the second plurality of cores for each continued
`drop in demand below a next lower threshold until
`one core of the second plurality of cores remains
`enabled, and ................................................................... 43 
`Elements 5[b], 13[b], 21[b]: [lower/lowering] an
`operating frequency or a supply voltage of the one
`core of the second plurality of cores as demand
`drops below a next lower threshold. .............................. 46 
`Dependent Claims 6, 14, 22: [The multi-core processor of
`claim 5/method of claim 13/The non-transitory machine
`readable medium of claim 21], [wherein the power
`management hardware is to raise/further comprising
`raising, with the power management hardware,] a supply
`voltage or an operating frequency of said one core in
`response to higher demand. ...................................................... 48 
`Ground 3: Claims 7, 15, and 23 Are Rendered Obvious By
`Sutardja/Carmack ............................................................................... 48 
`1. 
`Dependent Claims 7, 15, 23: The [multi-core processor of
`claim 1/method of claim 9/non-transitory machine
`readable medium of claim 17], wherein [the operating
`comprises operating] the first plurality of cores [are] at a
`
`v
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`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`2. 
`
`3. 
`
`4. 
`
`b. 
`
`c. 
`
`d. 
`
`e. 
`
`maximum operating frequency in the state. ............................. 48 
`D.  Ground 4: Claims 1-4, 7-12, 15-20, and 23-24 Are Rendered
`Obvious By Mathieson/Sutardja ........................................................ 50 
`1. 
`A POSITA would have been motivated to combine
`Mathieson with Sutardja .......................................................... 50 
`Independent Claim 1 ................................................................ 51 
`a. 
`Element 1[preamble]: A multi-core processor
`comprising: .................................................................... 51 
`Element 1[a][i]: a first plurality of cores and a
`second plurality of cores that support a same
`instruction set, ................................................................ 52 
`Element 1[a][ii]: wherein the second plurality of
`cores consume less power, for a same applied
`operating frequency and supply voltage, than the
`first plurality of cores; and ............................................. 55 
`Element 1[b][i]: power management hardware to,
`from a state where the first plurality of cores and
`the second plurality of cores are enabled, disable
`all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of
`the second plurality of cores, ......................................... 56 
`Element 1[b][ii]: wherein an operating system to
`execute on the multi-core processor is to monitor a
`demand for the multi-core processor and control
`the power management hardware based on the
`demand. .......................................................................... 62 
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that have narrower logic gate driver transistors than
`corresponding logic gates of the first plurality of cores. ......... 64 
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that consume less power than corresponding logic gates of
`
`vi
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`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`5. 
`
`6. 
`
`7. 
`
`8. 
`
`b. 
`
`the first plurality of cores. ........................................................ 67 
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a
`maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of
`cores. ........................................................................................ 69 
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum
`operating frequency in the state. .............................................. 70 
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ..................................................................................... 72 
`a. 
`Element 8[a]: the power management hardware is
`to enable all of the first plurality of cores for an
`increase in demand above the threshold without
`disabling any of the second plurality of cores, .............. 72 
`Element 8[b]: wherein an operating system is to
`monitor a demand for the multi-core processor and
`control the power management hardware based on
`the demand. .................................................................... 77 
`Independent Claims 9 and 17: .................................................. 77 
`a. 
`Element 9[preamble]: A method comprising: ............... 77 
`b. 
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that
`when processed by a machine causes a method to
`be performed, the method comprising: .......................... 77 
`Elements 9[a][i] and 17[a][i]: operating a multi-
`core processor such that a first plurality of cores
`and a second plurality of cores execute a same
`instruction set, ................................................................ 77 
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same
`applied operating frequency and supply voltage,
`than the first plurality of cores; and ............................... 78 
`
`c. 
`
`d. 
`
`vii
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`9. 
`
`e. 
`
`f. 
`
`Elements 9[b][i] and 17[b][i]: disabling with
`power management hardware, from a state where
`the first plurality of cores and the second plurality
`of cores are enabled, all of the first plurality of
`cores for a drop in demand below a threshold
`without disabling any of the second plurality of
`cores, .............................................................................. 78 
`Element 9[b][ii] and 17[b][ii]: wherein an
`operating system executing on the multi-core
`processor monitors a demand for the multi-core
`processor and controls the power management
`hardware based on the demand. ..................................... 78 
`Dependent Claims 10 and 18: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first
`plurality of cores. ..................................................................... 78 
`10.  Dependent Claims 11 and 19: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that consume less power than
`corresponding logic gates of the first plurality of cores. ......... 79 
`11.  Dependent Claims 12 and 20: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the second plurality of
`cores at a maximum operating frequency that is less than
`a maximum operating frequency of the first plurality of
`cores. ........................................................................................ 79 
`12.  Dependent Claims 15 and 23: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. ............. 79 
`13.  Dependent Claims 16 and 24: The [method of claim 9/non-
`
`viii
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`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`b. 
`
`E. 
`
`transitory machine readable medium of claim 17], further
`comprising ................................................................................ 79 
`a. 
`Elements 16[a] and 24[a]: enabling, with the
`power management hardware, all of the first
`plurality of cores for an increase in demand above
`the threshold without disabling any of the second
`plurality of cores, ........................................................... 79 
`Elements 16[b] and 24[b]: wherein an operating
`system is to monitor a demand for the multi-core
`processor and control the power management
`hardware based on the demand. ..................................... 80 
`Ground 5: Claims 5-6, 13-14, and 21-22 Are Rendered Obvious
`By Mathieson/Sutardja/Rychlik ......................................................... 80 
`1. 
`Dependent Claims 5, 13, and 21: ............................................. 80 
`a. 
`Elements 5[a], 13[a], 21[a] ............................................ 80 
`b. 
`Elements 5[b], 13[b], 21[b] ........................................... 81 
`Dependent Claims 6, 14, 22 ..................................................... 81 
`2. 
`XIV.  CONCLUSION ............................................................................................. 82 
`
`
`
`
`ix
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`LIST OF EXHIBITS1
`
`Ex-1001 U.S. Patent No. 10,049,080 to George et al. (“the ’080 Patent”)
`Ex-1002 Declaration of Dr. Trevor Mudge
`Ex-1003 Curriculum Vitae of Dr. Trevor Mudge
`Ex-1004 Prosecution History of the ’080 Patent (Application No. 15/431,527)
`Ex-1005 U.S. Patent Pub. No. 2011/0213950 to Mathieson et al.
`(“Mathieson”)
`Ex-1006 U.S. Patent Pub. No. 2009/0309243 to Carmack et al. (“Carmack”)
`Ex-1007 U.S. Patent Pub. No. 2008/0288748 to Sutardja et al. (“Sutardja
`’748”)
`Ex-1008 U.S. Patent Pub. No. 2007/0083785 to Sutardja (“Sutardja ’785”)
`Ex-1009 U.S. Patent Pub. No. 2011/0145615 to Rychlik et al. (“Rychlik”)
`Ex-1010 Prosecution History of U.S. Patent No. 9,569,278 (“the ’278 Patent”)
`Ex-1011
`INTENTIONALLY LEFT BLANK
`Ex-1012
`INTENTIONALLY LEFT BLANK
`Ex-1013
`INTENTIONALLY LEFT BLANK
`Ex-1014
`INTENTIONALLY LEFT BLANK
`Ex-1015
`INTENTIONALLY LEFT BLANK
`Ex-1016
`INTENTIONALLY LEFT BLANK
`Ex-1017
`INTENTIONALLY LEFT BLANK
`Ex-1018
`INTENTIONALLY LEFT BLANK
`Ex-1019
`INTENTIONALLY LEFT BLANK
`
`
`1 Four-digit pin citations that begin with 0 are to the branded numbers added by
`Samsung in the bottom right corner of the exhibits. All other pin citations are to
`original page, column, paragraph, or line numbers.
`
`x
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Ex-1025
`
`Ex-1020 Claim Mapping Table
`Ex-1021
`INTENTIONALLY LEFT BLANK
`Ex-1022 U.S. Patent Pub. No. 2006/0095807 to Grochowski (“Grochowski”)
`Ex-1023 U.S. Patent Pub. No. 2012/0317568 to Aasheim (“Aasheim”)
`Ex-1024
`Jeffrey C. Mogul et al., Operating Systems and Asymmetric Single-
`ISA CMPs: The Potential for Saving Energy, Hewlett-Packard
`Development Company, L.P. (2007)
`Juan Carlos Saez et al., Operating System Support for Mitigating
`Software Scalability Bottlenecks on Asymmetric Multicore
`Processors, ACM 978-1-4503-004-5/10/05 (2010)
`Ex-1026 U.S. Patent No. 7,093,147 to Farkas et al. (“Farkas”)
`Ex-1027 Charles Lefurgy et al., Energy Management for Commercial Servers,
`Computer 39 (Dec. 2003).
`Ex-1028 Yushi Shen et al., Enabling the New Era of Cloud Computing: Data
`Security, Transfer, and Management (Information Science Reference
`2014).
`Ex-1029 Stefanos Kaxiras and Margaret Martonosi, Computer Architecture
`Techniques for Power-Efficiency, in Synthesis Lectures on Computer
`Architecture #4 (Morgan & Claypool 2008).
`Ex-1030 Vasanth Venkatachalam and Michael Franz, Power Reduction
`Techniques For Microprocessor Systems, 37 ACM Computing
`Surveys 195 (2005).
`Ex-1031 Euiseong Seo et al., Energy Efficient Scheduling of Real-Time Tasks
`on Multicore Processors, 19 IEEE Transactions on Parallel and
`Distributed Systems 1540 (Nov. 2008).
`Ex-1032 Rakesh Kumar et al., Single-ISA Heterogeneous Multi-Core
`Architectures: The Potential for Processor Power Reduction,
`Proceedings of the 36th International Symposium on
`Microarchitecture (MICRO-36 2003), IEEE Computer Society
`(2003).
`
`xi
`
`

`

`Ex-1033 U.S. Patent No. 8,615,647 to Hum et al. (“Hum”)
`
`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`xii
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., and
`
`Qualcomm, Inc. (collectively, “Petitioner”) request inter partes review (“IPR”) of
`
`Claims 1-24 of U.S. Patent No. 10,049,080 (“the ’080 Patent”) (Ex-1001), currently
`
`assigned to Daedalus Prime LLC (“PO”).
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. §42.8
`Real Parties-in-Interest: Petitioner identifies the following real parties-in-
`
`interest: Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., and Co-
`
`Petitioner Qualcomm Incorporated, and Qualcomm Technologies, Inc.
`
`Petitioner Qualcomm Incorporated further identifies, without conceding any
`
`such party is a Real Party-in-Interest, Mazda Motor Corporation, Mazda North
`
`American Operations, Mazda Motor of America, Inc., Mercedes-Benz Group AG,
`
`Mercedes-Benz AG, Mercedes-Benz USA, LLC, and Visteon Corporation as parties
`
`that Patent Owner has accused of infringing the ’080 Patent based on incorporation
`
`of Qualcomm products in Daedalus Prime LLC v. Mazda Motor Corporation et al.,
`
`1:22-cv-01109 (D. Del.) and Certain Semiconductors and Devices and Products
`
`Containing the Same, Including Printed Circuit Boards, Automotive Parts, and
`
`Automobiles, ITC Inv. No. 337-TA-1332 (Violation).
`
`Related Matters: Patent Owner has asserted the ’080 Patent against
`
`Petitioner in (1) Daedalus Prime LLC v. Arrow Electronics, Inc. et al., 1:22-cv-
`
`1
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`01107 (D. Del.); (2) Daedalus Prime LLC v. Mazda Motor Corporation et al., 1:22-
`
`cv-01109 (D. Del.); (3) Daedalus Prime LLC v. Mazda Motor Corporation et al.,
`
`1:22-cv-01108 (D. Del.); (4) Daedalus Prime LLC v. Samsung Electronics Co., Ltd.
`
`et al., 2:22-cv-00352 (E.D. Tex.); (5) Certain Integrated Circuits, Mobile Devices
`
`Containing the Same, and Components Thereof, U.S. International Trade
`
`Commission (“ITC”) Inv. No. 337-TA-1335 (Violation); and (6) Certain
`
`Semiconductors and Devices and Products Containing the Same, Including Printed
`
`Circuit Boards, Automotive Parts, and Automobiles, ITC Inv. No. 337-TA-1332
`
`(Violation).
`
`Lead and Back-Up Counsel:
`
` Lead Counsel:
`
`William M. Fink (Reg. No. 72,332)
`O’Melveny & Myers LLP
`1625 Eye Street, NW
`Washington, DC 20006
`Telephone: (202) 383-5300
`Fax: (202) 383-5414
`E-Mail: tfink@omm.com
`
` Backup Counsel:
`
`Ben Haber (Reg. No. 67,129)
`Nicholas J. Whilt (Reg. No. 72,081)
`Brian Cook (Reg. No. 59,356)
`O’Melveny & Myers LLP
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Telephone: (213) 430-6000
`
`2
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Fax: (213) 430-6407
`E-Mail: bhaber@omm.com
`E-Mail: nwhilt@omm.com
`E-Mail: bcook@omm.com
`Counsel for Petitioners Samsung Electronics Co., Ltd. and
`Samsung Electronics America, Inc.
`
`Daniel Leventhal (Reg. No. 59,576)
`Richard Zembek (Reg. No.43,306)
`Darren Smith (Reg. No. 64,261)
`Norton Rose Fulbright US LLP
`1301 McKinney, Suite 5100
`Houston, TX 77010
`Telephone: (713) 651-5151
`Fax: (713) 651-5246
`E-Mail: daniel.leventhal@nortonrosefulbright.com
`E-Mail: richard.zembek@nortonrosefulbright.com
`E-Mail: darren.smith@nortonrosefulbright.com
`Counsel for Petitioner Qualcomm Incorporated
`
`Eagle H. Robinson (Reg. No.61,361)
`Norton Rose Fulbright
`98 San Jacinto Blvd., Ste. 1100
`Austin, TX 78701
`Telephone: (512) 474-5201
`Fax: (512) 536-4598
`E-Mail: eagle.robinson@nortonrosefulbright.com
`Counsel for Petitioner Qualcomm Incorporated
`
`Service Information: Petitioner consents to electronic service by email to
`
`
`
`
`
`the following addresses:
`
` tfink@omm.com
` bhaber@omm.com
` nwhilt@omm.com
` bcook@omm.com
` daniel.leventhal@nortonrosefulbright.com
` richard.zembek@nortonrosefulbright.com
`
`3
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
` darren.smith@nortonrosefulbright.com
` eagle.robinson@nortonrosefulbright.com
`
`III. GROUNDS FOR STANDING
`Petitioner certifies that the ’080 Patent is available for review, and Petitioner
`
`is not barred or estopped from requesting review.
`
`IV. FEE AUTHORIZATION
`The PTO is authorized to charge any fees due during this proceeding to
`
`Deposit Account No. LA500639.
`
`V.
`
`PRECISE RELIEF REQUESTED
`Petitioner requests cancellation of Claims 1-24 under 35 U.S.C. §§103 on the
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`following grounds, supported by a declaration from Dr. Trevor Mudge. Ex-1002.
`
`Ground
`
`Summary
`
`1
`
`2
`
`Claims 1-4, 7-12, 15-20, and 23-24 are rendered obvious by
`Sutardja2 alone (Ex-1007, incorporating Ex-1008)
`
`Claims 5-6, 13-14, and 21-22 are rendered obvious by Sutardja in
`view of Rychlik (“Sutardja/Rychlik”)
`
`
`2 For clarity, this ground relies on Sutardja ’748 (Ex-1007) incorporating by
`reference Sutardja ’785 (Ex-1008), as a single reference obviousness ground,
`referred to herein as the “combined Sutardja” or simply “Sutardja.” When reference
`is made to a particular patent, Ex-1007 refers to Sutardja ’748, and Ex-1008 refers
`to the incorporated document Sutardja ’785. To the extent that any relied upon
`teaching is argued to have not been fully incorporated from Ex-1008 into Ex-1007,
`it would have been obvious to combine such feature/teaching from Ex-1008 with
`Ex-1007, for the same reasons provided herein.
`
`4
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Ground
`
`Summary
`
`3
`
`4
`
`5
`
`Claims 7, 15, and 23 are rendered obvious by Sutardja in view of
`Carmack (“Sutardja/Carmack”)
`
`Claims 1-4, 7-12, 15-20, and 23-24 are rendered obvious by
`Mathieson3 (Ex-1005, incorporating Ex-1006) in view of Sutardja
`(“Mathieson/Sutardja”)
`
`Claims 5-6, 13-14, and 21-22 are
`Mathieson/Sutardja
`in
`view
`(“Mathieson/Sutardja/Rychlik”)
`
`rendered obvious by
`of
`Rychlik
`
`
`
`VI. THE CHALLENGED PATENT
`The ’080 Patent is directed to power management in a multi-core processor.
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`Ex-1001, 3:34-62. The ’080 Patent explains that “a number of different power
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`management schemes are incorporated into modern day computing systems.” Ex-
`
`1001, 2:20-22. Prior art power management schemes include “enabl[ing]/disabl[ing]
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`entire cores and rais[ing]/lower[ing] their supply voltages and operating frequencies
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`in response to system workload,” as illustrated in Figure 2.4 Ex-1001, 2:30-33.
`
`
`3 For clarity, Ground 4 relies on Mathieson (Ex-1005) incorporating by reference
`Carmack (Ex-1006), referred to herein as simply “Mathieson.” To the extent that
`any relied upon teaching is argued to have not been fully incorporated from Ex-1006
`into Ex-1005, it would have been obvious to combine such teaching from Ex-1006
`with Ex-1005, for the same reasons provided herein.
`4 All annotations and emphasis have been added, unless otherwise noted.
`
`5
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`
`
`The ‘080 Patent allegedly improves upon the prior art using “[s]ome basic
`
`concepts of electronic circuit power consumption,” including that “the speed of
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`operation of interconnected logic gates [] rises as the width of its driving transistors
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`[] increase,” as does the power consumed by those logic gates. Ex-1001, 2:43-52,
`
`3:26-33. In particular, the ’080 Patent implements a multi-core processor in which
`
`one or more cores are “designed to be lower performance and therefore consume
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`less power than other cores,” while nevertheless supporting the same instruction set,
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`purportedly to achieve greater power savings. Ex-1001, 3:50-62, 4:20-29.
`
`But multi-core processors with both high-power and low-power cores, each
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`supporting the same instruction set, were well-known in the prior art. Ex-1002, ¶¶34,
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`54-57. Indeed, as explained below, the ’080 Patent’s claims would have been
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`obvious.
`
`6
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`VII. PROSECUTION HISTORY
`The ’080 Patent was filed February 13, 2017, as a continuation of Application
`
`No. 13/335,257 (now U.S. 9,569,278), filed December 21, 2011.
`
`During prosecution, the Examiner rejected pending claims corresponding to
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`issued claims 1, 4-9, 12-17, and 20-24 over U.S. Patent Pub. No. 2006/0095807 to
`
`Grochowski and pending claims corresponding to issued claims 2-3, 10-11, and 18-
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`19 over Grochowski in view of U.S. Patent Pub. No. 2008/0263324 (Sutardja ’324).
`
`Ex-1004, 0067-0072. Applicant argued that Grochowski failed to teach all of the
`
`limitations of the independent claims:
`
`Ex-1004, 0056. Notably, Applicant did not dispute that Sutardja ’324 teaches the
`
`transistor-related limitations of dependent Claims 2-3, 10-11, and 18-19. Ex-1004,
`
`
`
`0054-0057.
`
`7
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`As reflected in the file history, the purported novelty of the claims lay in the
`
`
`
`power management hardware. However, as explained in the Grounds below, this
`
`limitation (indeed all limitations of Claims 1-24) was well-known.
`
`VIII. THERE IS NO BASIS FOR DISCRETIONARY DENIAL
`The Board should not deny institution under 35 U.S.C. §314(a). The ’080
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`Patent has not been challenged in any other post-grant proceeding or reexamination.
`
`The only proceedings relating to the ’080 Patent with scheduled hearing dates are in
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`the ITC (the concurrent District court litigations are stayed pending the ITC
`
`proceedings), however, concurrent ITC proceedings are not a basis to discretionarily
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`deny IPR institution. See USPTO Memorandum by Katherine Vidal, June 21, 2022,
`
`Interim Procedure For Discretionary Denials in AIA Post-Grant Proceedings with
`
`Parallel District Court Litigation, at 5-7.
`
`Nor should the Board deny institution under 35 U.S.C. §325(d), because both
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`parts of the Advanced Bionics, LLC v. Med-El Elektromedizinische Geräte GMBH
`
`framework weigh against denial. IPR2019-01469, Paper 6, at 8 (PTAB Feb. 13,
`
`2020) (precedential).
`
`A. Advanced Bionics Part I
`First, to the best of Petitioner’s knowledge, none of Sutardja ’785 (Ex-1008),
`
`Mathieson (Ex-1005), Carmack (Ex-1006), or Rychlik (Ex-1009) were presented to
`
`or considered by the Examiner during prosecution. Second, although Sutardja ’748
`
`8
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`(Ex-1007) and its parent application, Sutardja ’324, are cited on the face of the ’080
`
`Patent, the Office never considered Sutardja ’785 (Ex-1008), incorporated by
`
`reference into Sutardja ’748 (Ex-1007) (i.e., the combined Sutardja applied