U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
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`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG ELECTRONICS AMERICA, INC., and QUALCOMM, INC.,
`Petitioners
`
`v.
`
`DAEDALUS PRIME LLC.
`Patent Owner.
`
`
`
`
`DECLARATION OF TREVOR MUDGE
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 10,049,080
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`I.(cid:3)
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`II.(cid:3)
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`V.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`INTRODUCTION .......................................................................................... 1(cid:3)
`A.(cid:3) Qualifications ....................................................................................... 1(cid:3)
`B.(cid:3) Materials Considered ............................................................................ 3(cid:3)
`LEGAL STANDARDS .................................................................................. 5(cid:3)
`A.(cid:3) Anticipation .......................................................................................... 5(cid:3)
`B.(cid:3)
`Obviousness .......................................................................................... 6(cid:3)
`C.(cid:3)
`Level of Ordinary Skill in the Art ........................................................ 9(cid:3)
`D.(cid:3)
`Claim Construction ............................................................................ 11(cid:3)
`SUMMARY OF GROUNDS ....................................................................... 12(cid:3)
`III.(cid:3)
`IV.(cid:3) THE ’080 PATENT ...................................................................................... 12(cid:3)
`A.(cid:3) Overview of the ’080 Patent ............................................................... 12(cid:3)
`B.(cid:3)
`Prosecution History of the ’080 Patent .............................................. 16(cid:3)
`TECHNOLOGY BACKGROUND .............................................................. 18(cid:3)
`A.(cid:3)
`Relationship between power, voltage, and frequency ........................ 19(cid:3)
`B.(cid:3) Multi-core processing approaches ...................................................... 20(cid:3)
`C.(cid:3)
`Processor Microarchitectures ............................................................. 24(cid:3)
`D.(cid:3) Heterogeneous multi-core processors ................................................ 25(cid:3)
`VI.(cid:3) THE PRIOR ART IN THE APPLIED INVALIDITY GROUNDS ........... 27(cid:3)
`A.(cid:3) Mathieson (Ex-1005) .......................................................................... 27(cid:3)
`B.(cid:3)
`Carmack (Ex-1006) ............................................................................ 30(cid:3)
`C.(cid:3)
`Sutardja – Sutardja ’748 (Ex-1007) and Sutardja ’785 (Ex-1008)
` ............................................................................................................ 32(cid:3)
`Rychlik (Ex-1009) .............................................................................. 34(cid:3)
`D.(cid:3)
`VII.(cid:3) CLAIM CONSTRUCTION ......................................................................... 35(cid:3)
`VIII.(cid:3) DETAILED EXPLANATION OF THE UNPATENTABILITY
`GROUNDS ................................................................................................... 36(cid:3)
`A.(cid:3) Ground 1: Claims 1-4, 7-12, 15-20, 23-24 are rendered obvious
`by Sutardja (Ex-1007, incorporating Ex-1008) .................................. 36(cid:3)
`1.(cid:3)
`Independent Claim 1 ................................................................ 36(cid:3)
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`ii
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`a.(cid:3)
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`b.(cid:3)
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`c.(cid:3)
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`d.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Element 1[pre]: A multi-core processor
`comprising: .................................................................... 36(cid:3)
`Element 1[a][i]: a first plurality of cores and a
`second plurality of cores that support a same
`instruction set, ................................................................ 37(cid:3)
`Element 1[a][ii]: wherein the second plurality of
`cores consume less power, for a same applied
`operating frequency and supply voltage, than the
`first plurality of cores; and ............................................. 46(cid:3)
`Element 1[b][i]: power management hardware to,
`from a state where the first plurality of cores and
`the second plurality of cores are enabled, disable
`all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of
`the second plurality of cores, ......................................... 47(cid:3)
`Element 1[b][ii]: wherein an operating system to
`execute on the multi-core processor is to monitor a
`demand for the multi-core processor and control
`the power management hardware based on the
`demand. .......................................................................... 58(cid:3)
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that have narrower logic gate driver transistors than
`corresponding logic gates of the first plurality of cores. ......... 61(cid:3)
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that consume less power than corresponding logic gates of
`the first plurality of cores. ........................................................ 63(cid:3)
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a
`maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of
`cores. ........................................................................................ 64(cid:3)
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum
`operating frequency in the state. .............................................. 65(cid:3)
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`e.(cid:3)
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`2.(cid:3)
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`3.(cid:3)
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`4.(cid:3)
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`5.(cid:3)
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`iii
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`6.(cid:3)
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`7.(cid:3)
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`b.(cid:3)
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`c.(cid:3)
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`d.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ..................................................................................... 66(cid:3)
`a.(cid:3)
`Element 8[a]: the power management hardware is
`to enable all of the first plurality of cores for an
`increase in demand above the threshold without
`disabling any of the second plurality of cores, .............. 66(cid:3)
`Element 8[b]: wherein an operating system is to
`monitor a demand for the multi-core processor and
`control the power management hardware based on
`the demand. .................................................................... 71(cid:3)
`Independent Claims 9 and 17: .................................................. 71(cid:3)
`a.(cid:3)
`Element 9[preamble]: A method comprising: ............... 71(cid:3)
`b.(cid:3)
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that
`when processed by a machine causes a method to
`be performed, the method comprising: .......................... 71(cid:3)
`Elements 9[a][i] and 17[a][i]: operating a multi-
`core processor such that a first plurality of cores
`and a second plurality of cores execute a same
`instruction set, ................................................................ 72(cid:3)
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same
`applied operating frequency and supply voltage,
`than the first plurality of cores; and ............................... 72(cid:3)
`Elements 9[b][i] and 17[b][i]: disabling with
`power management hardware, from a state where
`the first plurality of cores and the second plurality
`of cores are enabled, all of the first plurality of
`cores for a drop in demand below a threshold
`without disabling any of the second plurality of
`cores, .............................................................................. 72(cid:3)
`Element 9[b][ii] and 17[b][ii]: wherein an
`operating system executing on the multi-core
`processor monitors a demand for the multi-core
`processor and controls the power management
`hardware based on the demand. ..................................... 72(cid:3)
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`e.(cid:3)
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`f.(cid:3)
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`8.(cid:3)
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`9.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Dependent Claims 10 and 18: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first
`plurality of cores. ..................................................................... 73(cid:3)
`Dependent Claims 11 and 19: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that consume less power than
`corresponding logic gates of the first plurality of cores. ......... 73(cid:3)
`10.(cid:3) Dependent Claims 12 and 20: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the second plurality of
`cores at a maximum operating frequency that is less than
`a maximum operating frequency of the first plurality of
`cores. ........................................................................................ 73(cid:3)
`11.(cid:3) Dependent Claims 15 and 23: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. ............. 73(cid:3)
`12.(cid:3) Dependent Claims 16 and 24: The [method of claim 9/non-
`transitory machine readable medium of claim 17], further
`comprising ................................................................................ 74(cid:3)
`a.(cid:3)
`Elements 16[a] and 24[a]: enabling, with the
`power management hardware, all of the first
`plurality of cores for an increase in demand above
`the threshold without disabling any of the second
`plurality of cores, ........................................................... 74(cid:3)
`Elements 16[b] and 24[b]: wherein an operating
`system is to monitor a demand for the multi-core
`processor and control the power management
`hardware based on the demand. ..................................... 74(cid:3)
`Ground 2: Claims 5-6, 13-14, and 21-22 are rendered obvious by
`Sutardja in view of Rychlik ................................................................ 74(cid:3)
`1.(cid:3)
`Dependent Claims 5, 13, and 21: ............................................. 74(cid:3)
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`b.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Elements 5[a], 13[a], 21[a]: The [multi-core
`processor of claim 1/method of claim 9/non-
`transitory machine readable medium of claim 17],
`[wherein the power management hardware is to
`disable/further comprising disabling, with the
`power management hardware,] an additional core
`of the second plurality of cores for each continued
`drop in demand below a next lower threshold until
`one core of the second plurality of cores remains
`enabled, and ................................................................... 74(cid:3)
`Elements 5[b], 13[b], 21[b]: [lower/lowering] an
`operating frequency or a supply voltage of the one
`core of the second plurality of cores as demand
`drops below a next lower threshold. .............................. 80(cid:3)
`Dependent Claims 6, 14, 22: [The multi-core processor of
`claim 5/method of claim 13/The non-transitory machine
`readable medium of claim 21], [wherein the power
`management hardware is to raise/further comprising
`raising, with the power management hardware,] a supply
`voltage or an operating frequency of said one core in
`response to higher demand. ...................................................... 83(cid:3)
`Ground 3: Claims 7, 15, and 23 are rendered obvious by Sutardja
`in view of Carmack ............................................................................ 84(cid:3)
`1.(cid:3)
`Dependent Claims 7, 15, 23: The [multi-core processor of
`claim 1/method of claim 9/non-transitory machine
`readable medium of claim 17], wherein [the operating
`comprises operating] the first plurality of cores [are] at a
`maximum operating frequency in the state. ............................. 84(cid:3)
`D.(cid:3) Ground 4: Claims 1-4, 7-12, 15-20, and 23-24 are rendered
`obvious by Mathieson in view of Sutardja ......................................... 86(cid:3)
`1.(cid:3)
`A POSITA would have been motivated to combine
`Mathieson with Sutardja .......................................................... 86(cid:3)
`Independent Claim 1 ................................................................ 88(cid:3)
`a.(cid:3)
`Element 1[preamble]: A multi-core processor
`comprising: .................................................................... 88(cid:3)
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`C.(cid:3)
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`2.(cid:3)
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`2.(cid:3)
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`a.(cid:3)
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`b.(cid:3)
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`d.(cid:3)
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`e.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Element 1[a][i]: a first plurality of cores and a
`second plurality of cores that support a same
`instruction set, ................................................................ 89(cid:3)
`Element 1[a][ii]: wherein the second plurality of
`cores consume less power, for a same applied
`operating frequency and supply voltage, than the
`first plurality of cores; and ............................................. 93(cid:3)
`Element 1[b][i]: power management hardware to,
`from a state where the first plurality of cores and
`the second plurality of cores are enabled, disable
`all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of
`the second plurality of cores, ......................................... 96(cid:3)
`Element 1[b][ii]: wherein an operating system to
`execute on the multi-core processor is to monitor a
`demand for the multi-core processor and control
`the power management hardware based on the
`demand. ........................................................................ 104(cid:3)
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that have narrower logic gate driver transistors than
`corresponding logic gates of the first plurality of cores. ....... 107(cid:3)
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates
`that consume less power than corresponding logic gates of
`the first plurality of cores. ...................................................... 111(cid:3)
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a
`maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of
`cores. ...................................................................................... 112(cid:3)
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum
`operating frequency in the state. ............................................ 114(cid:3)
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ................................................................................... 116(cid:3)
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`b.(cid:3)
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`c.(cid:3)
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`3.(cid:3)
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`4.(cid:3)
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`5.(cid:3)
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`6.(cid:3)
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`7.(cid:3)
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`a.(cid:3)
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`b.(cid:3)
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`c.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Element 8[a]: the power management hardware is
`to enable all of the first plurality of cores for an
`increase in demand above the threshold without
`disabling any of the second plurality of cores, ............ 116(cid:3)
`Element 8[b]: wherein an operating system is to
`monitor a demand for the multi-core processor and
`control the power management hardware based on
`the demand. .................................................................. 121(cid:3)
`Independent Claims 9 and 17: ................................................ 121(cid:3)
`a.(cid:3)
`Element 9[preamble]: A method comprising: ............. 121(cid:3)
`b.(cid:3)
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that
`when processed by a machine causes a method to
`be performed, the method comprising: ........................ 122(cid:3)
`Elements 9[a][i] and 17[a][i]: operating a multi-
`core processor such that a first plurality of cores
`and a second plurality of cores execute a same
`instruction set, .............................................................. 122(cid:3)
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same
`applied operating frequency and supply voltage,
`than the first plurality of cores; and ............................. 122(cid:3)
`Elements 9[b][i] and 17[b][i]: disabling with
`power management hardware, from a state where
`the first plurality of cores and the second plurality
`of cores are enabled, all of the first plurality of
`cores for a drop in demand below a threshold
`without disabling any of the second plurality of
`cores, ............................................................................ 122(cid:3)
`Element 9[b][ii] and 17[b][ii]: wherein an
`operating system executing on the multi-core
`processor monitors a demand for the multi-core
`processor and controls the power management
`hardware based on the demand. ................................... 123(cid:3)
`Dependent Claims 10 and 18: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
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`d.(cid:3)
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`e.(cid:3)
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`f.(cid:3)
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`8.(cid:3)
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`9.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first
`plurality of cores. ................................................................... 123(cid:3)
`10.(cid:3) Dependent Claims 11 and 19: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating of the second plurality of cores comprises
`driving logic gates that consume less power than
`corresponding logic gates of the first plurality of cores. ....... 123(cid:3)
`11.(cid:3) Dependent Claims 12 and 20: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the second plurality of
`cores at a maximum operating frequency that is less than
`a maximum operating frequency of the first plurality of
`cores. ...................................................................................... 123(cid:3)
`12.(cid:3) Dependent Claims 15 and 23: The [method of claim 9/non-
`transitory machine readable medium of claim 17], wherein
`the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. ........... 124(cid:3)
`13.(cid:3) Dependent Claims 16 and 24: The [method of claim 9/non-
`transitory machine readable medium of claim 17], further
`comprising .............................................................................. 124(cid:3)
`a.(cid:3)
`Elements 16[a] and 24[a]: enabling, with the
`power management hardware, all of the first
`plurality of cores for an increase in demand above
`the threshold without disabling any of the second
`plurality of cores, ......................................................... 124(cid:3)
`Elements 16[b] and 24[b]: wherein an operating
`system is to monitor a demand for the multi-core
`processor and control the power management
`hardware based on the demand. ................................... 124(cid:3)
`Ground 5: Claims 5-6, 13-14, and 21-22 are rendered obvious by
`Mathieson/Sutardja in view of Rychlik ............................................ 125(cid:3)
`1.(cid:3)
`Dependent Claims 5, 13, and 21: ........................................... 125(cid:3)
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`b.(cid:3)
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`E.(cid:3)
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`a.(cid:3)
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Elements 5[a], 13[a], 21[a]: The [multi-core
`processor of claim 1/method of claim 9/non-
`transitory machine readable medium of claim 17],
`[wherein the power management hardware is to
`disable/further comprising disabling, with the
`power management hardware,] an additional core
`of the second plurality of cores for each continued
`drop in demand below a next lower threshold until
`one core of the second plurality of cores remains
`enabled, and ................................................................. 125(cid:3)
`Elements 5[b], 13[b], 21[b]: [lower/lowering] an
`operating frequency or a supply voltage of the one
`core of the second plurality of cores as demand
`drops below a next lower threshold. ............................ 126(cid:3)
`Dependent Claims 6, 14, 22: [The multi-core processor of
`claim 5/method of claim 13/The non-transitory machine
`readable medium of claim 21], [wherein the power
`management hardware is to raise/further comprising
`raising, with the power management hardware,] a supply
`voltage or an operating frequency of said one core in
`response to higher demand. .................................................... 127(cid:3)
`IX.(cid:3) CONCLUSION ........................................................................................... 127(cid:3)
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`b.(cid:3)
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`2.(cid:3)
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`x
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by Samsung Electronics Co., Ltd. and Samsung
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`Electronics America, Inc. (collectively, “Samsung” or “Petitioner”), as an
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`independent expert in this proceeding before the Patent Trial and Appeal Board
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`(“PTAB” or “Board”). I understand that Samsung is requesting that the Board
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`institute an inter partes review (“IPR”) proceeding of U.S. Patent No. 10,049,080
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`(“the ’080 Patent”) (Ex-1001), currently assigned to Daedalus Prime LLC (“Patent
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`Owner” or “PO”).
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`2.
`
` I am not and have never been an employee of Samsung. I am being
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`compensated at my usual and customary rate of $600 per hour. No part of my
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`compensation depends on the outcome of this proceeding, and I have no other
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`interest in this proceeding.
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`3.
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`I have been asked to provide my independent analysis of the ’080 Patent
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`in light of the prior art publications cited below. I have also been asked to consider
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`the state of the art and prior art available as of December 22, 2011. Based on the
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`prior art discussed in this declaration, it is my opinion that Claims 1-24 of the ’080
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`Patent is unpatentable for the reasons provided below.
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`A. Qualifications
`4.
`I am currently a the Bredt Family Professor of Computer Science and
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`Engineering at the University of Michigan, Ann Arbor. All of my opinions stated in
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`1
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`

`

`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`this declaration are based on my own personal knowledge and professional
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`judgment. In forming my opinions, I have relied on my over 45 years of research,
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`academic, industry, and consulting engineering experience in IC (integrated circuit)
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`processing, semiconductor devices, and computer architecture with an emphasis on
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`power and energy control.
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`5.
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` I am over 18 years of age and, if I am called upon to do so, I would be
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`competent to testify as to the matters set forth herein. I understand that a copy of
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`my current curriculum vitae, which details my education and professional and
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`academic experience, is being submitted by Petitioner as Exhibit 1003. The
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`following provides an overview of some of my experience that is relevant to the
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`matters set forth in this declaration.
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`6.
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`I received the Ph.D. in Computer Science from the University of
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`Illinois, Urbana. I am the Bredt Family Professor of Computer Science and
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`Engineering at the University. I am the author of numerous papers on computer
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`architecture, programming languages, VLSI design, and computer vision. I have
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`chaired 57 PhD theses in these areas. In 2014 I received the ACM/IEEE CS Eckert-
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`Mauchly Award for “pioneering contributions to low-power computer architecture
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`and its interaction with technology.” This is known as the computer architecture
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`community's most prestigious award. I also received the University of Illinois
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`2
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`Distinguished Alumni Award. I am a Life Fellow of the IEEE, a Fellow of the ACM,
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`and a member of the IET and the British Computer Society.
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`7.
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`Based on my experience and education, I believe that I am qualified to
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`opine as to the knowledge and level of skill of one of ordinary skill in the art at the
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`time of the alleged invention of the ’080 Patent, as well as the state of the art at that
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`time.
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`B. Materials Considered
`8.
`In forming my opinions, I have reviewed the following documents:1
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`Ex-1001 U.S. Patent No. 10,049,080 to George et al. (“the ’080 Patent”)
`Ex-1002 Declaration of Dr. Trevor Mudge
`Ex-1003 Curriculum Vitae of Dr. Trevor Mudge
`Ex-1004 Prosecution History of the ’080 Patent (Application No. 15/431,527)
`Ex-1005 U.S. Patent Pub. No. 2011/0213950 to Mathieson et al.
`(“Mathieson”)
`Ex-1006 U.S. Patent Pub. No. 2009/0309243 to Carmack et al. (“Carmack”)
`Ex-1007 U.S. Patent Pub. No. 2008/0288748 to Sutardja et al. (“Sutardja
`’748”)
`Ex-1008 U.S. Patent Pub. No. 2007/0083785 to Sutardja (“Sutardja ’785”)
`Ex-1009 U.S. Patent Pub. No. 2011/0145615 to Rychlik et al. (“Rychlik”)
`Ex-1010 Prosecution History of U.S. Patent No. 9,569,278 (“the ’278 Patent”)
`
`
`1 Four-digit pin citations that begin with 0 are to the branded numbers added by
`Samsung in the bottom right corner of the exhibits. All other pin citations are to
`original page, column, paragraph, or line numbers.
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`3
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
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`INTENTIONALLY LEFT BLANK
`Ex-1011
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`Ex-1012
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`Ex-1013
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`Ex-1016
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`Ex-1019
`Ex-1020 Claim Mapping Table
`Ex-1021
`INTENTIONALLY LEFT BLANK
`Ex-1022 U.S. Patent Pub. No. 2006/0095807 to Grochowski (“Grochowski”)
`Ex-1023 U.S. Patent Pub. No. 2012/0317568 to Aasheim (“Aasheim”)
`Ex-1024
`Jeffrey C. Mogul et al., Operating Systems and Asymmetric Single-
`ISA CMPs: The Potential for Saving Energy, Hewlett-Packard
`Development Company, L.P. (2007)
`Juan Carlos Saez et al., Operating System Support for Mitigating
`Software Scalability Bottlenecks on Asymmetric Multicore
`Processors, ACM 978-1-4503-004-5/10/05 (2010)
`Ex-1026 U.S. Patent No. 7,093,147 to Farkas et al. (“Farkas”)
`Ex-1027 Charles Lefurgy et al., Energy Management for Commercial Servers,
`Computer 39 (Dec. 2003).
`Ex-1028 Yushi Shen et al., Enabling the New Era of Cloud Computing: Data
`Security, Transfer, and Management (Information Science Reference
`2014).
`
`Ex-1025
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`
`Ex-1029 Stefanos Kaxiras and Margaret Martonosi, Computer Architecture
`Techniques for Power-Efficiency, in Synthesis Lectures on Computer
`Architecture #4 (Morgan & Claypool 2008).
`Ex-1030 Vasanth Venkatachalam and Michael Franz, Power Reduction
`Techniques For Microprocessor Systems, 37 ACM Computing
`Surveys 195 (2005).
`Ex-1031 Euiseong Seo et al., Energy Efficient Scheduling of Real-Time Tasks
`on Multicore Processors, 19 IEEE Transactions on Parallel and
`Distributed Systems 1540 (Nov. 2008).
`Ex-1032 Rakesh Kumar et al., Single-ISA Heterogeneous Multi-Core
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`Microarchitecture (MICRO-36 2003), IEEE Computer Society
`(2003).
`Ex-1033 U.S. Patent No. 8,615,647 to Hum et al. (“Hum”)
`II. LEGAL STANDARDS
`9.
`In forming my opinions and considering the subject matter of the ’080
`
`Patent and its claims in light of the prior art, I am relying on certain legal principles
`
`that counsel in this case explained to me. My understanding of these concepts is
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`summarized below.
`
`10.
`
`I understand that earlier publications and patents may act to render a
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`patent unpatentable for one of two reasons: (1) anticipation, and (2) obviousness.
`
`A. Anticipation
`11.
`It is my understanding that the claims of a patent are anticipated by a
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`prior art reference if each and every element of the claim is found either explicitly
`
`or inherently in the reference. I understand that inherency requires a showing that
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`the missing descriptive matter in the claim is necessarily present in the allegedly
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`anticipating reference, and that it would have been so recognized by a person of
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`ordinary skill in the art (“POSITA”).
`
`12.
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`I understand that when a challenged claim covers several structures,
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`either generically or as alternatives, the claim is deemed anticipated if any of the
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`structures within the scope of the claim is found in the prior art reference.
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`13. Although anticipation typically involves the analysis of a single prior
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`art reference, I understand that additional references may be used to show that the
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`prior art reference has enabling disclosure (i.e., allows a POSITA to make the
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`invention without undue experimentation), to explain the meaning of a term used in
`
`the prior art reference, and/or to show that a characteristic is inherent in the prior art
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`reference.
`
`B. Obviousness
`14.
`I understand that a claim is invalid as obvious if it would have been
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`obvious to a person of ordinary skill in the art at the time the alleged invention was
`
`made. This means that even if all of the elements of the claim cannot be found in a
`
`single prior art reference that would anticipate the claim, a person of ordinary skill
`
`in the art who was aware of the prior art would have been able to come up with the
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`claimed invention. This may be the case, for example, where the missing element
`
`represents only an insubstantial different over the prior art or a reconfiguration of a
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`U.S. Patent No. 10,049,080
`Declaration of Trevor Mudge
`known system. I understand that in an obviousness determination, the person of
`
`ordinary skill in the art is presumed to have knowledge of all material prior art.
`
`15.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged invention
`
`and the prior art, and the level of ordinary skill in evaluating the pertinent art.
`
`16.
`
`I understand that when a product is available, design incentives and
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`other market forces can prompt variations of it, either in the same field or a different
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`one. If a person of ordinary skill in the art can implement a predictable variation,
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`obviousness likely bars its patentability. For the same reason, if a technique has
`
`been used to improve one device and a person of ordinary skill in the art would
`
`recognize that it would improve similar devices in the same way, using the technique
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`would have been obvious.
`
`17.
`
`I understand that whether a prior art reference renders a patent claim
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`unpatentable as obvious is determine from the perspective of a person of ordinary
`
`skill in the art at the time of the alleged invention. I have been told that there is no
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`requirement that the prior art contain an express suggestion to combine known
`
`elements to achieve the claimed invention, but a suggestion to combine known
`
`elements to achieve the claimed invention may come from the prior art, as filtered
`
`through the knowledge of one skilled in the art. In addition, I have been told that
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`Declaration of Trevor Mudge
`the inferences and creative steps a person of ordinary skill in the art would employ
`
`are relevant to the determination of obviousness.
`
`18.
`
`I understand that one may consider, e.g., whether (1) the change was
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`merely the predictable result of using prior art elements according to their known
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`functions, or whether it was the result of true inventiveness; (2) there is some
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`teaching or suggestion in the prior art to make the modification or combination of
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`elements claimed in the patent; (3) the claimed innovation applies a known technique
`
`that had been used to improve a similar d