UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`QUALCOMM INCORPORATED,
`Petitioner,
`v.
`DAEDALUS PRIME LLC,
`Patent Owner.
`
`Case No. IPR2023-00567
`U.S. Patent No. 10,049,080
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107(A)
`
`

`

`Case No. IPR2023-00567
`Patent No. 10,049,080
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`B.
`
`C.
`
`Introduction ...................................................................................................... 5
`Technology Background .................................................................................. 6
`A.
`Prior Art Failures ................................................................................... 7
`III. Overview of the ’080 Patent ............................................................................ 9
`IV. Discretionary Factors ..................................................................................... 10
`A.
`Becton, Dickinson factor: “the similarities and material
`differences between the asserted art and the prior art involved
`during examination” ............................................................................ 11
`Becton, Dickinson factor: “the cumulative nature of the asserted
`art and the prior art evaluated during examination” ........................... 16
`Becton, Dickinson factor: “the extent to which the asserted art
`was evaluated during examination, including whether the prior
`art was the basis for rejection” ............................................................ 19
`Becton, Dickinson factor: “whether petitioner has pointed out
`sufficiently how the examiner erred in its evaluation of the
`asserted prior art” ................................................................................ 20
`Overview of Select Cited Art ........................................................................ 22
`A.
`Overview of Sutardja ’748 .................................................................. 22
`B.
`Overview of Sutardja ’785 .................................................................. 23
`C.
`Overview of Mathieson ....................................................................... 24
`VI. Ground 1 Fails ............................................................................................... 26
`A.
`Sutardja ’748 and Sutardja ’785 Are Not a Single Reference, and
`Petitioner Has Not Demonstrated They Would be Combined by
`a POSITA ............................................................................................ 26
`The Sutardja References do not render obvious Claim 1(a)(i) ........... 29
`B.
`The Sutardja References do not render obvious Claim 1(a)(ii) .......... 32
`C.
`The Sutardja References do not render obvious Claim 1(b)(i) ........... 34
`D.
`The Sutardja References do not render obvious Claim 1(b)(ii) .......... 38
`E.
`The Sutardja References do not render obvious Claims 9 and 17 ...... 40
`F.
`VII. Ground 4 Fails ............................................................................................... 41
`
`D.
`
`V.
`
`i
`
`

`

`A.
`
`Case No. IPR2023-00567
`Patent No. 10,049,080
`A POSITA Would Not Have Been Motivated to Combine
`Mathieson with the Sutardja References ............................................. 41
`B. Mathieson, Alone or in View of the Sutardja References, Does
`Not Render Obvious Claims 1, 3-4, and 7-8 ....................................... 43
`VIII. Conclusion ..................................................................................................... 53
`
`ii
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`

`

`TABLE OF AUTHORITIES
`
`Case No. IPR2023-00567
`Patent No. 10,049,080
`
`Page(s)
`
`Cases
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 31
`Callaway Golf Co. v. Acushnet Co.,
`576 F.3d 1331, 1346 (Fed. Cir. 2009) ................................................................ 27
`Personal Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987, 993 (Fed. Cir. 2017) .................................................................... 42
`Securus Techs., Inc. v. Global Tel*Link Corp.,
`701 F. App’x 971, 977 (Fed. Cir. 2017) ............................................................. 42
`Stone Basket Innovations, LLC v. Cook Med. LLC,
`892 F.3d 1175, 1179 (Fed. Cir. 2018) ................................................................ 12
`Advanced Bionics v. Med-El Elktro. GmbH
`IPR2019-01469, Paper 6 ............................................................................... 10-12
`Johns Manville Corp. v. Knauf Insulation, Inc.,
`IPR2018-00827, Paper 9 ..................................................................................... 42
`
`Statutes
`35 U.S.C. § 325(d) ............................................................................................... 5, 10
`
`iii
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`

`

`Case No. IPR2023-00567
`Patent No. 10,049,080
`
`TABLE OF EXHIBITS
`Description
`U.S. Pat. Pub. No. 2008/0263324 to Sutardja et al (“Sutardja ’324”)
`U.S. Pat. Pub. No. 2006/0095807 to Grochowski et al.
`(“Grochowski”)
`U.S. Patent No. 8,984,523 to Vajda
`U.S. Patent No. 8,892,931 to Kruglick
`U.S. Patent No. 9,086,883 to Thomson
`U.S. Patent Publication No. 2009/0222654 to Hum
`
`Exhibit
`2001
`2002
`
`2003
`2004
`2005
`2006
`
`iv
`
`

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`Case No. IPR2023-00567
`Patent No. 10,049,080
`
`I.
`
`Introduction
`The ’080 Patent improved how power is managed in computing systems by
`
`disclosing use of two sets of CPU cores that can consume different amounts of power
`
`and offer different performance capabilities. Whereas previously, multi-core
`
`processors used identical cores that were not intended for improved power savings
`
`or capabilities, the inventors of the ’080 Patent devised of a processor with a plurality
`
`of cores intended for each role. Even previous use of non-identical cores was
`
`insufficient, because they did not support the same instruction set, increasing the
`
`difficulty of moving computational processing between them. Using different cores
`
`that support the same instruction set, the multi-core processor of the ’080 Patent can
`
`operate at higher performance using the performance cores, or at higher efficiency
`
`using the low power cores, depending on computing demand. This greatly increases
`
`the power efficiency of the ’080 Patent’s processor at all levels of demand.
`
` The Petition asserts that the challenged claims of the ’080 patent are invalid
`
`as obvious, but fails because it: (1) improperly relies on the ipse dixit of a declarant
`
`who merely parrots attorney argument; (2) should be denied under 35 U.S.C. §
`
`325(d) for relying on substantially the same art and arguments previously presented
`
`to the Office; and (3) fails to demonstrate that the content of the cited art renders
`
`obvious any of the challenged claims.
`
`5
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`The cited art disclosed by Qualcomm Incorporated (“Petitioner”1) fails to
`
`render obvious the claims of the ’080 Patent, and the Petition should be denied in its
`
`entirety2.
`
`II.
`
`Technology Background
`Modern computing devices can make use of multicore processors that
`
`combine a plurality of processor cores on a single semiconductor die. Ex. 1001, 1:22-
`
`25. Multiple processor cores can be used, for example, to provide separate functional
`
`units, which can increase the amount of computations that can be performed at one
`
`time.
`
`The amount of power consumed by a processor is strongly correlated with its
`
`performance capabilities. Ex. 1001, 2:26-29. Because decreasing the processing
`
`performance of the system corresponds to power savings, processor power
`
`1 As filed, the Petition identified Samsung Electronics Co., Ltd. and Samsung
`Electronics America, Inc. (collectively “Samsung”) along with Qualcomm
`Incorporated as Petitioners. However, on June 2, 2023, Patent Owner and Petitioner
`Samsung jointly moved to terminate as to Samsung. Paper No. 10. On June 27, 2023,
`The Board granted the motion and terminated the proceedings as to Samsung, and
`noted that Qualcomm Incorporated would remain as Petitioner. Paper No. 11.
`2 Petitioner challenges independent claims 1, 9, and 17 as allegedly obvious only in
`Grounds 1 and 4. Thus, this Preliminary Response primarily addresses those
`Grounds; each of the challenged dependent claims is non-obvious at least because it
`depends from a non-obvious independent claim. Patent Owner reserves the right to
`address all arguments made in the Petition, including those made for other Grounds,
`in further briefing.
`
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`management typically scales up the performance of the system as the system’s
`
`workload increases, and scales down the performance as workload decreases. Ex.
`
`1001, 2:22-27. A typical way to scale processing performance and power
`
`consumption with workload is to enable or disable entire cores and raise or lower
`
`their supply voltages and operating frequencies (and thereby their power
`
`consumption) in response to system workload. Ex. 1001, 2:30-34.
`
`Prior Art Failures
`A.
`As set forth in the ’080 Patent, prior art approaches to power management did
`
`not provide for interchangeable use of different types of processor cores. For
`
`example, the ’080 Patent identifies a need in the industry for a suitable multi-core
`
`processor having non-identical cores supporting a same instruction set, and a power
`
`management scheme for the same that enables and disables the cores based on
`
`demand. See Ex. 1001, 2:19-20 (“Computer system power consumption is becoming
`
`more and more of a concern.”), 3:34-49 (“[P]rior art multi core processor power
`
`management schemes have been implemented on processors whose constituent
`
`cores are identical. … In other approaches, the cores are not identical but are
`
`radically different. … A problem with this approach, however, is that it is difficult
`
`for system software to adjust switch operation between processor cores having
`
`different instruction sets.”).
`
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`Case No. IPR2023-00567
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`Publications in the art noted a need for better power management, but failed
`
`to solve it. See Ex. 2003, 1:39-65 (“Amdahl’s law, even it’s [sic] version for chip
`
`multi-processors, will put a limit to the amount of performance increase that can be
`
`achieved even for highly parallelized applications.”). For example, some prior art
`
`approaches merely adjusted the frequency (also called “clock”) and voltage at which
`
`the cores operated to adjust the power consumption/processing capability balance,
`
`but such approaches presented core management difficulties. See Ex. 1001, 2:30-34
`
`(“A typical way to scale processing performance and power consumption with
`
`workload is to enable/disable entire cores and raise/lower their supply voltages and
`
`operating frequencies in response to system workload”); Ex. 2004, 1:31–37
`
`(“Attempts to apply [Dynamic Voltage and Frequency Scaling] to individual cores
`
`within a multicore processor may encounter a number of difficulties as the number
`
`of cores increases.”); Ex. 2005 at 1:42-56 (“Conventional [Dynamic Clock and
`
`Voltage Scaling] solutions [for multi-core processors] exhibit a number of
`
`performance problems, and implementing an effective DCVS method … for each
`
`core … is an important and challenging design criterion.”). Other prior art
`
`approaches attempted to use low power states, but this required time and energy to
`
`raise the cores or processor out of the low power state when needed. See Ex. 2006 at
`
`¶ 2 (“One approach to reducing power in a computing platform when there is
`
`relatively little activity, is to place the processor in a low-power state. However,
`8
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`placing a processor in a low-power state or returning a processor from a low-power
`
`state may require a non-trivial amount of time. Therefore, it may or may not be worth
`
`the time required to place a processor in a low-power state or to return the processor
`
`from a low-power state. Furthermore, not all processes and tasks that are run on a
`
`processor require the full processing throughput of the processor.”).
`
`III. Overview of the ’080 Patent
`The ’080 Patent describes a multicore processor that can make use of two sets
`
`of CPU cores that can consume different amounts of power and offer different
`
`performance capabilities. The CPU cores are thus referred to as “asymmetric.” The
`
`’080 Patent describes that its invention provides a way for a processor to make use
`
`of these two sets of asymmetric CPU cores to “scale up [it]s processing performance
`
`… as the system’s workload increases, and scale down [it]s processing performance
`
`… as the system’s workload decreases.”’ Ex. 1001 at 2:19-29, 3:50-62, 4:20-46.
`
`In particular, the ’080 Patent describes that a multi-core processor according
`
`to its invention can include power management hardware to enable and disable the
`
`cores in different configurations, and to change the frequency and voltage at which
`
`they operate, based on changes in computational demand. Ex. 1001 at 4:54-6:24. For
`
`example, in one embodiment the power management hardware may disable all of a
`
`first set of cores but keep all of a second set of cores active, when there is a drop in
`
`demand below a threshold. Ex. 1001 at 4:65-5:6, 5:25-28.
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`Case No. IPR2023-00567
`Patent No. 10,049,080
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`IV. Discretionary Factors
`It is well established that the Board has discretion to a deny petition where the
`
`art cited therein is merely cumulative of art previously considered during
`
`examination of the challenged patent. 35 U.S.C. § 325(d) (“the Director may take
`
`into account whether, and reject the petition or request because, the same or
`
`substantially the same prior art or arguments previously were presented to the
`
`Office”).
`
`[U]nder § 325(d), the Board uses the following two-part
`framework: (1) whether the same or substantially the same
`art previously was presented to the Office or whether the
`same or substantially the same arguments previously were
`presented to the Office; and (2) if either condition of first
`part of the framework is satisfied, whether the petitioner
`has demonstrated that the Office erred in a manner
`material to the patentability of challenged claims.
`
`Advanced Bionics v. Med-El Elktro. GmbH, IPR2019-01469, Paper 6, at 8 (PTAB
`
`Feb. 13, 2020) (precedential). In considering whether the same or substantially the
`
`same art or arguments were previously presented to the Office, “the Becton,
`
`Dickinson factors provide useful insight into how to apply the framework under 35
`
`U.S.C. § 325(d).” Id. at 9; id. at n.10 (identifying the Becton, Dickinson factors).
`
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`Here, Petitioner’s challenges all rely on the Sutardja references (Ex. 1007:
`
`Sutardja ’748, and Ex. 1008: Sutardja ’785), which were themselves considered
`
`during prosecution of the ’080 Patent, or Mathieson, which is cumulative of at least
`
`the Grochowski reference that was considered during prosecution. The Board should
`
`thus exercise its discretion to deny the Petition in its entirety.3
`
`A.
`
`Becton, Dickinson factor: “the similarities and material differences
`between the asserted art and the prior art involved during
`examination”
`Each of Petitioner’s cited references is materially similar to the art involved
`
`during examination, making this factor favor denial.
`
`Sutardja ’748 (Ex. 1007) was considered
`1.
`The first of the asserted Sutardja references, U.S. Patent Pub. No.
`
`2008/0288748 to Sutardja et al. (“Sutardja ’748,” Ex. 1007) was itself considered
`
`during prosecution of the ’080 Patent, making it perfectly similar to “the prior art
`
`involved during examination.” See IPR2019-01469 at n. 10 (factor (a)). For
`
`example, Sutardja ’748 (Ex. 1007) is identified on the face of the ’080 Patent as one
`
`3 Petitioner only challenges independent claims 1, 9, and 17 as either allegedly
`obvious over the Sutardja references (Ground 1), or Mathieson in view of the
`Sutardja references (Ground 4). Because Petitioner does not assert that any of the
`other cited art affects its contentions with respect to the independent claims, a finding
`that Mathieson and the Sutardja references are cumulative of art considered during
`prosecution could dispense of the entire Petition.
`11
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`of the “References Cited.” Ex. 1001 at References Cited. See Stone Basket
`
`Innovations, LLC v. Cook Med. LLC, 892 F.3d 1175, 1179 (Fed. Cir. 2018) (“when
`
`prior art is listed on the face of a patent, the examiner is presumed to have considered
`
`it”).
`
`Additionally, the parent application of Sutardja ’748 (Ex. 1007)—Sutardja
`
`’324 (Ex. 2001)—contains an identical disclosure and was also considered during
`
`examination of the ’080 Patent. See Ex. 1007; Ex. 2001; Pet. at 8-9. Specifically,
`
`the Sutardja ’748 (Ex. 1007) reference cited by Petitioner here is a continuation of
`
`Sutardja ’324 (Ex. 2001), which was considered during examination of the ’080
`
`Patent. Ex. 1007 at (63); Pet. at 9. Because it contains a disclosure identical to one
`
`considered during examination, Sutardja ’748 (Ex. 1007) is perfectly similar to “the
`
`prior art involved during examination.” See IPR2019-01469 at n. 10 (factor (a)).
`
`2.
`
`Sutardja ’785 (Ex. 1008) was considered under Petitioner’s
`positions4
`The second of the asserted Sutardja references, U.S. Patent Pub. No.
`
`2007/0083785 to Sutardja (“Sutardja ’785,” Ex. 1008) was considered during
`
`prosecution under Petitioner’s own logic. Petitioner asserts that Sutardja ’785 (Ex.
`
`4 Although Patent Owner disagrees with Petitioner’s assertion that the two Sutardja
`references should be treated as a single reference for the reasons discussed below, if
`they could be treated as such, then Sutardja ’785 was considered during examination.
`12
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`1008) “was not before the examiner” during the prosecution of the ’080 Patent, but
`
`Sutardja ’785 (Ex. 1008) is named by—and by Petitioner’s own assertion
`
`purportedly incorporated by reference into—each of Sutardja ’748 (Ex. 1007) and
`
`Sutardja ’324 (Ex. 2001).
`
`For example, Petitioner asserts that “Sutardja ’748 incorporates by reference
`
`the disclosure of Sutardja ’785 (Ex-1008) in its entirety.” Pet. at 17 (citing Ex-1007,
`
`¶1). Petitioner also repeatedly and throughout the Petition treats the two Sutardja
`
`references as a single reference because of the alleged incorporation of Sutardja ’785
`
`(Ex. 1008) into Sutardja ’748 (Ex. 1007). See, e.g., Pet. at 4 (identifying Ground 1
`
`as based on “Sutardja alone (Ex-1007, incorporating Ex-1008”); n.2 (“this ground
`
`relies on Sutardja ’748 (Ex-1007) incorporating by reference Sutardja ’785 (Ex-
`
`1008), as a single reference5 obviousness ground, referred to herein as the
`
`‘combined Sutardja’ or simply ‘Sutardja’”); 17 (providing overview of the combined
`
`“Sutardja (Ex. 1007, Ex. 1008)” and describing “[b]oth Sutardja ’748 and Sutardja
`
`’785 (collectively ‘Sutardja’)”). Thus, under Petitioner’s logic, by virtue of having
`
`considered Sutardja ’748 (Ex. 1007), the Examiner also considered Sutardja ’785
`
`(Ex. 1008).
`
`5 Emphasis added throughout unless otherwise noted.
`13
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`3. Mathieson is materially similar to art that was involved in
`examination
`Mathieson is materially similar to Sutardja ’748, which was involved in
`
`examination. For example, Petitioner admits that Mathieson is materially similar to
`
`Sutardja ’748, which was involved in examination. Petitioner asserts: “like
`
`Mathieson and the ’080 Patent, Sutardja [’748] teaches that the power consumption
`
`differences between cores are due to transistor differences,” Pet., p.17 (citing Ex.
`
`1007); “like Mathieson and the ’080 Patent, Sutardja [’748] teaches operating the
`
`multi-core processor in a high-power mode (with the high-power cores and,
`
`optionally, the low-power cores enabled) and a low-power mode (with only the low-
`
`power cores enabled), based on system loading,” Pet., p.17 (citing Ex. 1007).
`
`Additionally, Petitioner asserts in Ground 4 that Mathieson discloses or suggests the
`
`same limitations that it asserts Sutardja ’748 discloses in Ground 1, for similar
`
`reasons. These alleged similarities Sutardja ’748 and Mathieson confirm that
`
`Mathieson is materially examination.
`
`Additionally, Mathieson is materially similar to Grochowski, which was
`
`involved in examination. Petitioner asserts that the “Mathieson Ground, presented
`
`herein [is not] the same, substantially the same, or cumulative of Grochowski, relied
`
`upon by the Examiner in rejecting the independent claims of the ’080 Patent,” but
`
`provides only a single allegedly distinguishing feature of Mathieson:
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`teaching of
`the Examiner relied on Grochowski’s
`“parallelism in the program” and situations in which
`“parallelism increased” as teaching the claimed “demand”
`… Nor is Mathieson, in Ground 4, based on “parallelism
`as Grochowski is. Mathieson instead includes express
`teachings to consider “workloads” against “threshold”
`values to determine the claimed “demand.” None of these
`teachings
`relating
`to workloads,
`system
`loading
`parameters, and
`thresholds
`is cumulative of
`the
`Grochowski’s “parallelism” considerations as applied by
`the Examiner because they operate in substantially
`different ways than Grochowski.
`
`Pet. at 9-10 (citations omitted) (referring to U.S. Pat. Pub. No. 2006/0095807 to
`
`Grochowski et al., Ex. 2002). However, Petitioner does not explain how Mathieson
`
`allegedly works differently than Grochowski, or how Mathieson allegedly presents
`
`different considerations than Grochowski did.
`
`For example, Petitioner does not dispute that the examiner considered whether
`
`Grochowski’s disclosure of increased parallelism corresponds to an increased
`
`“demand.” Grochowski states:
`
`the amount of parallelism may be the number of
`simultaneous threads supported. In other embodiments,
`other metrics may be used to express the amount of
`parallelism, such as the aggregate number of instructions
`
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`retired per second, or the number of branch instructions
`that may support speculative multi-threaded execution.
`
`Ex. 2002 at [0024]. Nor did the applicant distinguish Grochowski on the ground that
`
`it described parallelism considerations. Therefore, Mathieson’s disclosure is
`
`materially similar to the disclosure of Grochowski that was previously considered
`
`during examination.
`
`B.
`
`Becton, Dickinson factor: “the cumulative nature of the asserted art
`and the prior art evaluated during examination”
`Petitioner’s cited art is also collectively cumulative of the prior art evaluated
`
`during examination, making this factor favor denial.
`
`1.
`
`The Sutardja References are cumulative of Grochowski in
`view of Sutardja ’324
`During examination of the ’080 Patent, the Examiner issued an office action
`
`based on Grochowski in view of Sutardja ’324. See Ex. 1004 at 0067-0072.
`
`Petitioner asserts that the Sutardja references are not cumulative of Grochowski, but
`
`ignores that (1) several of Grochowski’s disclosures mirror those that the Petition
`
`identifies in the Sutardja references, and (2) the prior art evaluated during
`
`examination included Grochowksi in combination with Sutardja ’324. Pet. at 10.
`
`For example, Petitioner asserts the following with respect to Grochowski:
`
`teaching of
`the Examiner relied on Grochowski’s
`“parallelism in the program” and situations in which
`
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`“parallelism increased” as teaching the claimed “demand.”
`But Grochowski discloses enabling high-power (A) cores
`and disabling low-power (B) cores in response to
`decreasing “parallelism.” In contrast, Sutardja discloses
`demand in the form of “system loading,” and its multi-core
`processor exhibits the opposite behavior—high-power
`cores are disabled and low-power cores remain enabled in
`response to decreasing loading.
`
`Pet. at 10 (citations omitted) (emphasis in original). However, Grochowski is not
`
`limited to disabling low power cores, the only thing allegedly distinguishing it from
`
`the Sutardja references. For example, as the Examiner cited, Grochowski explains
`
`that “[e]ach time the throttle module 210 makes the determination of the amount of
`
`parallelism in the program, it may initiate powering the A cores and B cores up or
`
`down using signal lines 224 through 266.” Ex. 2002 at [0034]; see also Ex. 1004 at
`
`0068 (citing Grochowski at [0034]). Because the disclosures in the Sutardja
`
`references mirror those of Grochowski, they are cumulative of the art evaluated
`
`during examination.
`
`Additionally, Grochowski was not considered
`
`in
`
`isolation during
`
`examination—it was specifically considered in combination with Sutardja ’324. See
`
`Ex. 1004 at 0067-0072. As explained above, Sutardja ’324 (Ex. 2001) contains the
`
`same disclosure as Sutardja ’748 (Ex. 1007) because it is the continuation-parent
`
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`thereof. And yet, Petitioner cites to Sutardja ’748 (Ex. 1007) as allegedly disclosing
`
`something not considered during examination: “system loading” and high-power
`
`cores being disabled. Pet. at 10 (citing Ex. 1007). This is nonsensical; the same
`
`disclosure cannot now disclose something that it did not during examination.
`
`2. Mathieson is cumulative of Grochowski in view of Sutardja
`’324
`Petitioner asserts that Mathieson is not cumulative of Grochowski, but ignores
`
`that the prior art evaluated during examination included Grochowksi in combination
`
`with Sutardja ’324. For example, Petitioner asserts that Mathieson is not “based on
`
`‘parallelism’ as Grochowski is,” and that Mathieson’s disclosures “relating to
`
`workloads, system loading parameters, and thresholds” are non-cumulative of
`
`Grochowski. Pet. at 10-11. As to parallelism, Petitioner ignores that the art
`
`considered during examination—including Sutardja ’324 (Ex. 2002)—was not
`
`exclusively directed to parallelism. As to disclosures of workloads, as explained
`
`above, Sutardja ’324 (Ex. 2001) contains the same disclosure as Sutardja ’748 (Ex.
`
`1007) because it is the continuation-parent thereof. And yet, Petitioner cites to
`
`Sutardja ’748 (Ex. 1007) as allegedly disclosing “a demand in the form of ‘system
`
`load’ and/or ‘power/performance demand.’” See Pet. at 26 (citing Ex. 1007). In fact,
`
`as explained above, Petitioner asserts that Mathieson is similar to Sutardja ’748 (Ex.
`
`1007): “like Mathieson and the ’080 Patent, Sutardja [’748] teaches that the power
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`consumption differences between cores are due to transistor differences,” Pet., p.17
`
`(citing Ex. 1007); “like Mathieson and the ’080 Patent, Sutardja [’748] teaches
`
`operating the multi-core processor in a high-power mode (with the high-power cores
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`and, optionally, the low-power cores enabled) and a low-power mode (with only the
`
`low-power cores enabled), based on system loading,” Pet., p.17 (citing Ex. 1007).
`
`These alleged similarities between Sutardja ’748 and Mathieson confirm that
`
`Mathieson is merely cumulative of the collective prior art evaluated during
`
`examination.
`
`C.
`
`Becton, Dickinson factor: “the extent to which the asserted art was
`evaluated during examination, including whether the prior art was
`the basis for rejection”
`The disclosures of Sutardja references were evaluated during examination,
`
`including by being used as the basis for rejection, making this factor favor denial.
`
`Specifically, Sutardja ’324 (Ex. 2001) formed the basis of an office action
`
`during examination of the ’080 Patent, and contains an identical disclosure to
`
`Sutardja ’748 (Ex. 1007). Ex. 1004 (’080 Patent FH Excerpts) at 0070-0072; Pet. at
`
`9. This demonstrates that the disclosure of Sutardja ’748 (Ex. 1007) was thoroughly
`
`considered during examination.
`
`Further, Sutardja ’748 (Ex. 1007) itself was considered during examination of
`
`a parent to the ’080 Patent. During examination of the ’278 patent, three separate
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`office actions were issued relying on Sutardja ’748 (Ex. 1007). See Ex. 1010 (’278
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`patent FH Excerpts) at 0049-0053, 0110-0116, 0153-0159; Pet. at 10, n.5. Indeed,
`
`the ’278 patent was examined by the same Examiner as the ’080 Patent—Eric
`
`Coleman—demonstrating the consideration of that disclosure that was undertaken
`
`during examination. See, e.g., Ex. 1010 at 0009; Ex. 1001 at cover page.
`
`D.
`
`Becton, Dickinson factor: “whether petitioner has pointed out
`sufficiently how the examiner erred in its evaluation of the asserted
`prior art”
`Petitioner has failed to demonstrate that the examiner erred in evaluating the
`
`asserted art, and this factor favors denial.
`
`Petitioner’s only assertion of examiner error is as follows:
`
`even if deemed presented, it was material error not to apply Sutardja
`’324 or ’748 incorporating Sutardja ’785 (Ex-1008) in a rejection
`because fully-incorporated Sutardja discloses and teaches the claims
`pending during prosecution. The incorporated Sutardja ’785 discloses
`what the applicant claimed was missing from the prior art: the plurality
`of low power cores.
` Pet., pp.11-12. However, Petitioner omits that arguments regarding failure to
`
`disclose the plurality of low power cores were not made during prosecution of the
`
`’080 patent at issue here. Rather, Petitioner cites to Ex. 1010, which is the
`
`“Prosecution History of U.S. Patent No. 9,569,278.” See Pet., p.12 (citing to “supra
`
`n.5,” which cites Ex. 1010); Pet., p.x (identifying Ex. 1010). Petitioner has not
`
`compared the claims that were pending during evaluation of the ’278 patent to those
`
`at issue here from the ’080 patent—evaluation of prior art with respect to different
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`claims is inapposite here. For example, the challenged claims of the ’080 patent and
`
`the pending claims of the ’278 patent are reproduced here:
`
`Pending claims of the ’278 Patent
`A multi-core processor comprising
`a plurality of cores that support a same
`instruction set, wherein at least two of
`the plurality of cores consume less
`power, for a same applied operating
`frequency and supply voltage, than at
`least one other of the plurality of cores.
`
`Challenged claim of the ’080 Patent
`[1pre] A multi-core
`processor
`comprising:
`[1a] a first plurality of cores and a
`second plurality of cores that support a
`same instruction set, wherein the second
`plurality of cores consume less power,
`for a same applied operating frequency
`and supply voltage,
`than the first
`plurality of cores; and
`[1b] power management hardware to,
`from a state where the first plurality of
`cores and the second plurality of cores
`are enabled, disable all of the first
`plurality of cores for a drop in demand
`below a threshold without disabling any
`of the second plurality of cores, wherein
`an operating system to execute on the
`multi-core processor is to monitor a
`demand for the multi-core processor
`and control the power management
`hardware based on the demand.
`
`Compare Ex. 1010 at 0125, 0135 with Ex. 1001 at cl. 1. In glossing over this
`
`distinction, Petitioner ignores that different arguments were made during evaluation
`
`of the ’080 Patent. For example, the cited art—including Sutardja ’748 (Ex. 1007)—
`
`was distinguished based on limitation [1b] of the ’080 Patent, which is distinct from
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`Case No. IPR2023-00567
`Patent No. 10,049,080
`arguments regarding failure to disclose the plurality of low power cores that
`
`Petitioner points to as alleged error. See Ex. 1004, pp.0054-0057.
`
`V.
`
`Overview of Select Cited Art
`A.
`Overview of Sutardja ’748
`Sutardja ’748 is directed to a “core switching system” that includes a “mode
`
`switching module that receives a switch signal to switch operation between a first
`
`mode and a second mode.” Ex. 1007 at Abstract. During the first mode, “instructions
`
`associated with applications are executed by a first asymmetric core, and a second
`
`asymmetric core is inactive.” Ex. 1007 at Abstract. During the second mode, “the
`
`instructions are executed by the second asymmetric core, and the first asymmetric
`
`core is inactive.” Ex. 1007 at Abstract.
`
`The multi-core processor disclosed in Sutardja ’748 includes a high power
`
`(“HP”) core and a low power (“LP”) core in which “the mult