`(12) Patent Application Publication (10) Pub. No.: US 2008/0263324 A1
`Sutardja et al.
`(43) Pub. Date:
`Oct. 23, 2008
`
`US 20080263.324A1
`
`(54) DYNAMIC CORE SWITCHING
`(76) Inventors:
`Sehat Sutardja, Los Altos Hills,
`CA (US); Hong-Yi Chen, Fremont,
`CA (US); Premanand Sakarda,
`Acton, MA (US); Mark N.
`Fullerton, Austin, TX (US); Jay
`Heeb, Gilbert, AZ (US)
`Correspondence Address:
`HARNESS, DICKEY & PIERCE P.L.C.
`5445 CORPORATE DRIVE, SUITE 200
`TROY, MI 48098 (US)
`(21) Appl. No.:
`12/145,660
`
`(22) Filed:
`
`Jun. 25, 2008
`Related U.S. Application Data
`(63) Continuation-in-part of application No. 1 1/523.996,
`filed on Sep. 20, 2006.
`(60) Provisional application No. 60/968,143, filed on Aug.
`27, 2007, provisional application No. 60/978,936,
`filed on Oct. 10, 2007, provisional application No.
`60/981,606, filed on Oct. 22, 2007, provisional appli
`cation No. 61/022.431, filed on Jan. 21, 2008, provi
`sional application No. 61/029,476, filed on Feb. 18,
`2008, provisional application No. 61/049,641, filed on
`
`May 1, 2008, provisional application No. 61/058,050,
`filed on Jun. 2, 2008, provisional application No.
`60/825,368, filed on Sep. 12, 2006, provisional appli
`cation No. 60/823,453, filed on Aug. 24, 2006, provi
`sional application No. 60/822,015, filed on Aug. 10,
`2006.
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 9/00
`(52) U.S. Cl. ................................... 712/43; 712/E09.001
`
`ABSTRACT
`(57)
`A system includes a first asymmetric core, a second asym
`metric core, and a core Switching module. The first asymmet
`ric core executes an application when the system operates in
`a first mode and is inactive when the system operates in a
`second mode. The second asymmetric core executes the
`application when the system operates in the second mode.
`The core Switching module Switches operation of the system
`between the first mode and the second mode. The core switch
`ing module selectively stops processing of the application by
`the first asymmetric core after receiving a first control signal.
`The core switching module transfers a first state of the first
`asymmetric core to the second asymmetric core. The second
`asymmetric core resumes executing the application in the
`second mode.
`
`Memory
`Applications
`
`Application
`Application
`
`Application
`
`Application
`Application
`
`Application
`
`Application
`Application
`
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`
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`Control Module
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 1 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 1 of 17
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`US 2008/0263.324 A1
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`Main Processor
`
`Processor
`
`
`
`
`
`10
`
`16
`
`HP ProCeSSOr
`
`
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`
`LP
`Processor
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 2 of 42
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`Oct. 23, 2008 Sheet 2 of 17
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`US 2008/0263.324 A1
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`40
`
`-2
`
`24
`
`THREADS
`
`Control Module
`
`34
`
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`
`FIG. 3A
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 3 of 42
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`US 2008/0263.324 A1
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`-2
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`Control Module
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`FIG. 3B
`
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 4 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 4 of 17
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`US 2008/0263.324 A1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 5 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 5 of 17
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`US 2008/0263.324 A1
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`
`
`Current
`operating
`mode?
`
`Mode
`Signal set to HP
`node?
`
`Mode
`Signal set to LP
`mode?
`
`Increase power to HP
`Core and HP Cache
`
`Increase power to LP
`Core and LP cache
`
`HP Core ready?
`
`LP Core ready?
`
`Transfer threads of
`running applications to
`HP Core
`
`Transfer threads of
`running applications to
`LP Core
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 6 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 6 of 17
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`US 2008/0263.324 A1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 7 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 7 of 17
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`US 2008/0263.324 A1
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`
`
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`
`250
`
`Profiling tool monitors system loading
`of LP Core,
`
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`Read state of HP Core and copy state
`into memory
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`itch to HP Core
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`260
`
`Transition LP Core to active state
`
`Read state of LP Core and copy state
`into memory
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`On resume status, load state from
`memory into LP Core
`
`Transition HP Core to inactive state
`
`Resume execution in LP processor
`
`Execute Application level
`
`Transition HP pressor to active
`
`Load state of LP Core from memory
`into HP processor
`
`Transition LP processor to inactive
`state
`
`Resume execution in HP processor
`
`Execute Application level
`
`Profiling tool monitors speed or other
`parameters of HP processor,
`
`264
`
`268
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`272
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`276
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`280
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`288
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`SWitch to LP
`Orocessor?
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`292
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`300
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`306
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`310
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`320
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`324
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`Patent Owner Daedalus Prime LLC
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`P processor active?
`
`Monitor speed of LP processor
`
`Monitor executing application type
`
`Erie,
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`System
`Loading > First
`hreshold?
`
`System
`loading < Second
`hreshold?
`
`Transition to HP processor
`HP S.
`
`Application
`closed?
`
`System
`loading Wlo App < 2"
`Threshold?
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 9 of 42
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`Oct. 23, 2008 Sheet 9 of 17
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`US 2008/0263.324 A1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 10 of 42
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`Oct. 23, 2008 Sheet 10 of 17
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 11 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 11 of 17
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`US 2008/0263.324 A1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 12 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 12 of 17
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`US 2008/0263.324 A1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 13 of 42
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 13 of 17
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`US 2008/0263.324 A1
`
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 14 of 42
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`
`
`Patent Application Publication
`
`Oct. 23, 2008 Sheet 14 of 17
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`US 2008/0263.324 A1
`
`s
`Event signated by
`ore profile module
`
`
`
`
`
`witch Cores
`based On reSource
`utilization?
`
`Disable interrupts
`
`Complete pending
`RTW
`
`Call hypervisor
`module to Switch
`Cores
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`502
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`Save Core 1 state
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`conerency
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`516
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`Send event to
`Core2
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`518
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`State
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`Resume Core 1
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`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 15 of 42
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`Oct. 23, 2008 Sheet 15 of 17
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`US 2008/0263.324 A1
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`866
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`976
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`User input
`
`FIG. 11B
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 16 of 42
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`
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`Patent Application Publication
`
`Oct. 23, 2008 Sheet 16 of 17
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`US 2008/0263.324 A1
`
`--989
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`Mobile Device
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`Audio Output
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`User input
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`1097
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`1096
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`1090
`
`FIG. 11D
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 17 of 42
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`
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`Patent Application Publication
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`Oct. 23, 2008 Sheet 17 of 17
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`US 2008/0263.324 A1
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`w
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`/O Devices
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`Multi-Core
`Processing
`System
`
`
`
`
`
`Multi-Core
`Control Module
`
`
`
`F.G. 11E
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 18 of 42
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`
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`Oct. 23, 2008
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`DYNAMIC CORE SWITCHING
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`0001. This application claims the benefit of U.S. Provi
`sional Application No. 60/968,143, filed Aug. 27, 2007; U.S.
`Provisional Application No. 60/978,936, filed Oct. 10, 2007:
`U.S. Provisional Application No. 60/981,606, filed Oct. 22,
`2007; U.S. Provisional Application No. 61/022,431 filed Jan.
`21, 2008; U.S. Provisional Application No. 61/029,476, filed
`Feb. 18, 2008; U.S. Provisional Application No. 61/049,641,
`filed May 1, 2008; and U.S. Provisional Application No.
`61/058,050, filed Jun. 2, 2008. The disclosures of the above
`applications are incorporated herein by reference in their
`entirety.
`
`FIELD
`0002 The present disclosure relates to mobile computing
`devices, and more particularly to dynamically Switching
`cores of multi-core processing systems of mobile computing
`devices.
`
`BACKGROUND
`0003. The background description provided herein is for
`the purpose of generally presenting the context of the disclo
`sure. Work of the presently named inventors, to the extent it is
`described in this background section, as well as aspects of the
`description that may not otherwise qualify as prior art at the
`time offiling, are neither expressly nor impliedly admitted as
`prior art against the present disclosure.
`0004 Mobile computing devices such as cellular phones,
`MP3 players, global positioning system (GPS) devices, etc.
`are typically powered using both line power and battery
`power. The mobile computing devices typically include a
`processor, memory and a display, which consume power dur
`ing operation. The processor generally executes both simple
`applications that are less processing-intensive and complex
`applications that are more processing-intensive. Therefore,
`the capabilities of the processor Such as processing speed are
`typically selected to match the performance requirements of
`the most processing-intensive applications that will be
`executed.
`0005 One significant limitation of mobile computing
`devices relates to the amount of time for which the devices
`can be operated using batteries without recharging. Using a
`high-speed processor that meets the performance require
`ments of the processing-intensive applications generally
`increases power consumption, which corresponds to a rela
`tively short battery life.
`0006 Referring now to FIGS. 1A and 1B, some desktop
`and laptop computers use multiple processor integrated cir
`cuits (ICs) or a single processor IC with multiple cores. These
`systems can be of different types. As used herein, the term
`processor is used to refer to an IC with one or more processing
`cores. A multi-core processor refers to an IC, a system-on
`chip (SOC), or a system-in-package (SIP) with two or more
`processing cores.
`0007. In FIG. 1A, an asymmetric multi-processor (MP)
`system 1 comprising a main processor 2 and one or more
`secondary processors 3 is shown. The asymmetric MP system
`1 may also be implemented as a single IC or SOC with a main
`core and a secondary core. The main processor 2 has a dif
`ferent instruction set architecture (ISA) than the secondary
`
`processors 3. An operating system (OS) may run on the main
`processor 2. Applications may run on the secondary proces
`sors 3. The secondary processors 3 do not run threads of the
`OS and may be invisible to an OS scheduler. An OS driver
`interface to a real-time OS (RTOS) may run on the secondary
`processors 3. Key functions may be offloaded to the second
`ary processors 3 for power saving and reducing the duty cycle
`of the main processor 2. For example only, the asymmetric
`MP system 1 can be used for special-purpose processing (e.g.,
`Video, 3D graphics, etc.). Since the secondary processors 3
`may run in addition to the main processor 2 when applications
`are executed, the asymmetric MP System 1 may consume
`large amounts of power.
`0008. In FIG. 1B, a symmetric MP system.5 may comprise
`N identical processors, where N is an integer greater than 1.
`The symmetric MP system 5 may also be implemented as a
`single IC or SOC with N identical cores. N may be propor
`tional to the processing load of the symmetric MP system 5.
`The N processors use the same ISA. The N processors may be
`visible to the OS scheduler. The N processors may have
`transparent access to system resources including memory and
`input/output (I/O). Depending on the processing load, one or
`more of the N processors can be utilized to execute applica
`tions. The high cost and high power consumption of the
`symmetric MP system 5 tends to make this architecture
`unsuitable for lower cost mobile devices.
`
`SUMMARY
`0009. A system comprises a first asymmetric core, a sec
`ond asymmetric core, and a core Switching module. The first
`asymmetric core executes an application when the system
`operates in a first mode and is inactive when the system
`operates in a second mode. The second asymmetric core
`executes the application when the system operates in the
`second mode. The core Switching module Switches operation
`of the system between the first mode and the second mode.
`The core Switching module selectively stops processing of the
`application by the first asymmetric core after receiving a first
`control signal. The core Switching module transfers a first
`state of the first asymmetric core to the second asymmetric
`core. The second asymmetric core resumes executing the
`application in the second mode.
`0010. In another feature, the first control signal indicates
`that interrupts are disabled.
`0011. In another feature, the second asymmetric core
`executes instructions without instruction translation when the
`second asymmetric core resumes executing the application
`during the second mode.
`0012. In other features, the system further comprises an
`operating system (OS) that provides services to the applica
`tion. The core switching module switches execution of the
`application between the first asymmetric core and the second
`asymmetric core transparently to the OS.
`0013. In other features, a first maximum speed of the first
`asymmetric core is greater than a second maximum speed of
`the second asymmetric core. The first asymmetric core oper
`ates at frequencies greater than a predetermined frequency.
`The second asymmetric core operates at frequencies less than
`the predetermined frequency. A first maximum operating
`power level of the first asymmetric core is greater than a
`second maximum operating power level of the second asym
`metric core.
`0014. In other features, the first asymmetric core uses a
`first instruction set architecture (ISA). The second asymmet
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 19 of 42
`
`
`
`US 2008/0263.324 A1
`
`Oct. 23, 2008
`
`ric core uses a second ISA. The first ISA is compatible with
`the second ISA. A first set of instructions of the first ISA is a
`superset of a second set of instructions of the second ISA. The
`first set includes more instructions than the second set.
`0015. In other features, the OS comprises a kernel. The
`core switching module executes above a level of the kernel.
`0016. In other features, the system further comprises a
`hypervisor module. The core Switching module is integrated
`with the hypervisor module.
`0017. In other features, the core switching module saves
`the first state when the core switching module selectively
`stops processing of the application by the first asymmetric
`core. The core Switching module powers up the second asym
`metric core and initializes the second asymmetric core using
`the first state. The interrupts are enabled after the second
`asymmetric core resumes executing the application. The core
`Switching module shuts down the first asymmetric core when
`the second asymmetric core powers up. One of no power and
`standby power is Supplied to the first asymmetric core after
`the first asymmetric core is shut down.
`0018. In other features, the system further comprises a
`level-2 (L2) cache that communicates with the first asymmet
`ric core. One of no power and standby power is supplied to the
`L2 cache after the first asymmetric core is shut down.
`0019. In other features, the core switching module initial
`izes the first asymmetric core using the first state when the
`second asymmetric core fails to power up. The first asymmet
`ric core resumes executing the application in the first mode
`and interrupts are enabled.
`0020. In other features, the core switching module
`switches operation of the system between the second mode
`and the first mode. The core switching module selectively
`stops processing of the application by the second asymmetric
`core after receiving the first control signal. The core Switching
`module transfers a second state of the second asymmetric
`core to the first asymmetric core. The first asymmetric core
`resumes executing the application in the first mode. The first
`control signal indicates that interrupts are disabled.
`0021. In another feature, instructions are executed without
`instruction translation when the first asymmetric core
`resumes executing the application during the first mode.
`0022. In other features, the system further comprises an
`operating system (OS) that provides services to the applica
`tion. The core switching module switches execution of the
`application between the second asymmetric core and the first
`asymmetric core transparently to the OS.
`0023. In other features, the core switching module saves
`the second state when the core switching module selectively
`stops processing of the application by the second asymmetric
`core. The core Switching module powers up the first asym
`metric core and initializes the first asymmetric core using the
`second state. The interrupts are enabled after the first asym
`metric core resumes executing the application.
`0024. In other features, the system further comprises a
`level-2 (L2) cache that communicates with the first asymmet
`ric core. Power is supplied to the L2 cache after the first
`asymmetric core powers up.
`0025. In other features, the core switching module shuts
`down the second asymmetric core when the first asymmetric
`core powers up. One of no power and standby power is Sup
`plied to the second asymmetric core after the second asym
`metric core is shut down.
`0026. In other features, the core switching module initial
`izes the second asymmetric core using the second state when
`
`the first asymmetric core fails to power up. The second asym
`metric core resumes executing the application in the second
`mode, and the interrupts are enabled.
`0027. In another feature, the system further comprises a
`core profile module that generates a second control signal
`based on at least one of core utilization, resource utilization,
`and performance of the application.
`0028. In other features, the system further comprises a
`core change sequence (CCS) module that initiates a CCS
`based on the second control signal. The core Switching mod
`ule switches execution of the application between one of the
`first and second asymmetric cores and another of the first and
`second asymmetric cores based on the CCS.
`0029. In other features, the CCS module initiates the CCS
`when the core utilization of the second asymmetric core by
`the application is greater than or equal to a first predetermined
`threshold. The CCS module initiates the CCS when the core
`utilization of the second asymmetric core by the application is
`greater than or equal to a second predetermined threshold for
`a first predetermined time period. The CCS module initiates
`the CCS when an anticipated core utilization of the second
`asymmetric core is greater than or equal to a third predeter
`mined threshold. The anticipated core utilization is deter
`mined based on at least one of a type of the application and a
`history of execution of the application. The CCS module
`initiates the CCS when the core utilization of the first asym
`metric core by the application is less than or equal to a fourth
`predetermined threshold. The CCS module initiates the CCS
`when the core utilization of the first asymmetric core by the
`application is less than or equal to a fifth predetermined
`threshold for a second predetermined time period.
`0030. In another feature, the CCS module initiates the
`CCS based on at least one of a type of the application, a
`number of applications, and a type of instruction executed by
`one of the first and second asymmetric cores.
`0031. In another feature, the core profile module generates
`the second control signal based on a number of times execu
`tion of applications is switched between one of the first and
`second asymmetric cores and another of the first and second
`asymmetric cores.
`0032. In other features, the system further comprises a
`power control module that controls power consumption of the
`system and that generates a third control signal based on the
`second control signal and the power consumption. The sys
`tem further comprises a core change sequence (CCS) module
`that initiates a CCS based on the third control signal. The core
`Switching module Switches execution of the application
`between one of the first and second asymmetric cores and
`another of the first and second asymmetric cores based on the
`CCS.
`0033. In another feature, the system further comprises a
`frequency change sequence (FCS) module that initiates a
`FCS based on the second control signal and that selects an
`operating frequency of at least one of the first and second
`asymmetric cores based on the FCS.
`0034. In another feature, the system further comprises a
`voltage change sequence (VCS) module that initiates a VCS
`based on the second control signal and that selects a Supply
`Voltage of at least one of the first and second asymmetric
`cores based on the VCS.
`0035. In another feature, the system further comprises a
`power management module that disables the interrupts when
`the system switches operation between the first mode and the
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 20 of 42
`
`
`
`US 2008/0263.324 A1
`
`Oct. 23, 2008
`
`second mode and that disables the interrupts when the system
`switches operation between the second mode and the first
`mode.
`0036. In other features, the system further comprises a
`plurality of the first asymmetric core. The core switching
`module selectively activates and deactivates more than one of
`the plurality of the first asymmetric core based on the CCS
`when the system operates in the first mode.
`0037. In another feature, the system further comprises a
`glue logic module that selectively communicates with the
`core Switching module, that receives interrupts, that receives
`first signals from the application, and that routes the interrupts
`and the first signals to the one of the first and second asym
`metric cores activated by the core Switching module.
`0038. In another feature, a system-on-chip (SOC) com
`prises the system.
`0039. In another feature, a system-in-package (SIP) com
`prises the system.
`0040. In still other features, a method comprises executing
`an application using a first asymmetric core when operating
`in a first mode. The first asymmetric core is inactive when
`operating in a second mode. The method further comprises
`Switching operation between the first mode and the second
`mode using a core Switching module. The method further
`comprises selectively stopping processing of the application
`by the first asymmetric core using the core Switching module
`after receiving a first control signal. The method further com
`prises transferring a first state of the first asymmetric core to
`the second asymmetric core using the core Switching module
`and resuming execution of the application in the second mode
`using the second asymmetric core.
`0041. In another feature, the method further comprises
`disabling interrupts and indicating via the first control signal
`that the interrupts are disabled.
`0042. In another feature, the method further comprises
`executing instructions without instruction translation when
`the second asymmetric core resumes executing the applica
`tion during the second mode.
`0043. In another feature, the method further comprises
`providing services to the application via an operating system
`(OS) and switching execution of the application between the
`first asymmetric core and the second asymmetric core trans
`parently to the OS using the core Switching module.
`0044. In other features, the method further comprises
`selectively operating the first asymmetric core at a first maxi
`mum speed and selectively operating the second asymmetric
`core at a second maximum speed. The first maximum speed is
`greater than the second maximum speed. The method further
`comprises selectively operating the first asymmetric core at a
`first maximum operating power level and selectively operat
`ing the second asymmetric core at a second maximum oper
`ating power level. The first maximum operating power level is
`greater than the second maximum operating power level. The
`method further comprises selectively operating the first
`asymmetric core at frequencies greater than a predetermined
`frequency and selectively operating the second asymmetric
`core at frequencies less than the predetermined frequency.
`0045. In other features, the method further comprises
`operating the first asymmetric core using a first instruction set
`architecture (ISA) and operating the second asymmetric core
`using a second ISA. The first ISA is compatible with the
`second ISA. The method further comprises operating the first
`asymmetric core using a first set of instructions of the first
`ISA and operating the second asymmetric core using a second
`
`set of instructions of the second ISA. The first set is a superset
`of the second set. The first set includes more instructions than
`the second set.
`0046. In another feature, the method further comprises
`providing a kernel of the OS and executing the core Switching
`module above a level of the kernel.
`0047. In another feature, the method further comprises
`providing a hypervisor module and integrating the core
`Switching module with a hypervisor module.
`0048. In other features, the method further comprises sav
`ing the first state when the core Switching module selective
`stops processing of the application by the first asymmetric
`core. The method further comprises powering up the second
`asymmetric core and initializing the second asymmetric core
`using the first state. The method further comprises enabling
`the interrupts after the second asymmetric core resumes
`executing the application. The method further comprises
`shutting down the first asymmetric core when the second
`asymmetric core powers up and Supplying one of no power
`and standby power to the first asymmetric core after the first
`asymmetric core is shut down.
`0049. In other features, the method further comprises pro
`viding a level-2 (L2) cache. The first asymmetric core com
`municates with the L2 cache when the first asymmetric core
`is active. The method further comprises Supplying one of no
`power and standby power to the L2 cache after the first asym
`metric core is shut down.
`0050. In another feature, the method further comprises
`initializing the first asymmetric core using the first state when
`the second asymmetric core fails to power up, resuming
`execution of the application in the first mode using the first
`asymmetric core, and enabling interrupts.
`0051. In another feature, the method further comprises
`Switching operation between the second mode and the first
`mode using a core Switching module, selectively stopping
`processing of the application by the second asymmetric core
`using the core Switching module after receiving the first con
`trol signal indicating that interrupts are disabled, transferring
`a second state of the second asymmetric core to the first
`asymmetric core using the core Switching module, and
`resuming execution of the application in the first mode using
`the first asymmetric core.
`0052. In another feature, the method further comprises
`executing instructions without instruction translation when
`the first asymmetric core resumes executing the application
`during the first mode.
`0053. In another feature, the method further comprises
`providing services to the application via an operating system
`(OS) and switching execution of the application between the
`second asymmetric core and the first asymmetric core trans
`parently to the OS using the core Switching module.
`0054. In other features, the method further comprises sav
`ing the second state when the core Switching module selec
`tively stops processing of the application by the second asym
`metric core. The method further comprises powering up the
`first asymmetric core and initializing the first asymmetric
`core using the second state. The method further comprises
`enabling the interrupts after the first asymmetric core resumes
`executing the application.
`0055. In other features, the method further comprises pro
`viding a level-2 (L2) cache. The first asymmetric core com
`municates with the L2 cache when the first asymmetric core
`is active. The method further comprises Supplying power to
`the L2 cache after the first asymmetric core powers up.
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2001 - Page 21 of 42
`
`
`
`US 2008/0263.324 A1
`
`Oct. 23, 2008
`
`0056. In other features, the method further comprises
`shutting down the second asymmetric core when the first
`asymmetric core powers up and Supplying one of no power
`and standby power to the second asymmetric core after the
`second asymmetric core is shut down.
`0057. In another feature, the method further comprises
`initializing the second asymmetric core using the second state
`when the first asymmetric core fails to power up, resuming
`execution of the application in the second mode using the
`second asymmetric core, and enabling the interrupts.
`0058. In another feature, the method further comprises
`generating a second control signal based on at least one of
`core utilization, resource utilization, and performance of the
`application.
`0059. In another feature, the method further comprises
`initiating a core change sequence (CCS) based on the second
`control signal and Switching execution of the application
`between one of the first and second asymmetric cores and
`another of the first and second asymmetric cores based on the
`CCS using the core Switching module.
`0060. In other features, the method further comprises ini
`tiating the CCS when the core utilization of the second asym
`metric core by the application is greater than or equal to a first
`predetermined threshold. The method further comprises ini
`tiating the CCS when the core utilization of the second asym
`metric core by the application is greater than or equal to a
`second predetermined threshold for a first predetermined
`time period. The method further comprises initiating the CCS
`when the core utilization of the first asymmetric core by the
`application is less than or equal to a third predetermined
`threshold. The method further comprises initiating the CCS
`when the core utilization of the first asymmetric core by the
`application is less than or equal to a fourth predetermined
`threshold for a first predetermined time period.
`0061. In another feature, the method further comprises
`determining an anticipated core utilization based on at least
`one of a type of the application and a history of execution of
`the application and initiating the CCS when the anticipated
`core utilization of the second asymmetric core is greater than
`or equal to a predetermined threshold.
`0062. In another feature, the method further comprises
`initiating the CCS based on at least one of a number of
`applications executed by one of the first and second asym
`metric cores, a type of the application executed by one of the
`first and second asymmetric cores, and a type of instruction
`executed by one of the first and second asymmetric cores.
`0063. In anot