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`....... .
`• • • • • '.4
`• • • •
`• • •
`
`LORI STEINTHAL
`12 INCORPORATED
`
`MANUFACTURERS REPRESENTATIVES
`
`3255 Scott Boulevard
`Suite 1-102
`Santa Clara, CA 95054-3013
`Tel: (408) 988-3400
`Fax: (408) 988-2079
`
`•
`
`0
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`.. . . . . .
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`
`XILINX EXHIBIT 1018, Page 1
`
`

`

`PRINTED IN KOREA
`Circuit diagrams utilizing SAMSUNG products are included as a means of illustrating typical semi(cid:173)
`conductor applications; consequently, complete information sufficient for construction purposes is
`not necessarily given. The information has been carefully checked and is believed to be entirely
`reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information
`does not convey to the purchaser of the semiconductor devices described herein any license under
`the patent rights of SAMSUNG or others. SAMSUNG reserves the right to change device specifica(cid:173)
`tions.
`
`XILINX EXHIBIT 1018, Page 2
`
`

`

`Certificate No
`
`FM 24651
`
`XILINX EXHIBIT 1018, Page 3
`
`

`

`TABLE OF CONTENTS
`
`I. General Information
`
`1. Introduction
`2. Product Guide
`3. Ordering Information
`
`--------------------------------------------------------------------------------------- 13
`--------------------------------------------------------------------------------- 21
`----------------------------------------------------------------------------- 25
`
`II. Data sheets
`
`1M DRAM
`- KM41 C1 OOOD
`- KM44C256D
`- KM48C128
`- KM48C124
`- KM416C60
`- KM416C64
`
`4M DRAM
`
`---------------------------------------- 1 Mx1, 5V, F/P
`----------------------- 31
`----------------------- 38
`---------------------------------------- 256KX4, 5V, F/P
`---------------------- 45
`---------------------------------------- 128KX8, 5V, F/P
`---------------------------------------- 128KX8, 5V, EDO -----------------------·52
`---------------------------------------- 64KX16, 5V, F/P
`------------------------ 59
`------------------------ --------------- 64KX16, 5V, EDO ----------------------- 66
`
`------------------ 75
`- KM41 C4000C, KM41 V4000C -------------------- 4Mx1, 5V/3.3V, F/P
`------------------ 83
`- KM44C1000C, KM44V1000C -------------------- 1 Mx4, 5V/3.3V, F/P
`-------------------- 1 Mx4, 5V, Quad CAS, F/P
`- KM44C1003C
`---------- 91
`- KM44C1004C, KM44V1004C -------------------- 1 Mx4, 5V/3.3V, EDO ------------------ 99
`-------------------- 1 Mx4, 5V, Quad CAS", EDO --------- 107
`- KM44C1005C
`- KM48C512B, KM48V512B
`-------------------- 512Kx8, 5V /3.3V, F/P ------------------ 115
`- KM48C514B, KM48V514B
`-------------------- 512KX8, 5V/3.3V, EDO ---------------- 122
`- KM416C256B, KM416V256B -------------------- 256Kx16, 5V /3.3V, F/P ---------------- 129
`- KM416C254B, KM416V254B -------------------- 256Kx16, 5V/3.3V, EDO -------------- 137
`---------------- 145
`-------------------~ 512Kx8, 5V/3.3V, F/P
`- KM48C512D, KM48V512D
`-------------------: 512KX8, 5V /3.3V, EDO ---------------- 152
`- KM48C514D, KM48V514D
`- KM416C256D, KM416V256D -------------------~ 256Kx16, 5V13.3V, F/P ---------------- 159
`- KM416C254D, KM416V254D --------------------* 256Kx16, 5V/3.3V, EDO ---------------- 167
`
`* The D-version is under development and will take the place of B-version from March 1996.
`
`XILINX EXHIBIT 1018, Page 4
`
`

`

`TABLE OF. CONTENTS(Continued)
`
`16M DRAM
`
`.----------------- 177
`
`.----------------- 185
`
`.----------------- 193
`.----------------- 201
`
`.----------------- 209
`.----------------- 217
`
`.----------------- 225
`
`.----------------- 233
`
`- KM41 C16000B
`-------------16Mx1, 5V, F/P
`KM41 V16000B
`16Mx1, 3.3V, F/P
`- KM44C4000B, KM44C4100B
`------------- 4Mx4, 5V, F/P
`KM44V4000B, KM44V4100B
`4Mx4, 3.3V, F/P
`__________ n _ 4Mx4, 5V, Quad CAS, F/P
`- KM44C4003B, KM44C4103B
`- KM44C4004B, KM44C4104B
`------------- 4Mx4, 5V, EDO
`4Mx4, 3.3V, EDO
`KM44V4004B, KM44V4104B
`------------- 4Mx4, 5V, Quad CA"S", EDO
`- KM44C4005B, KM44C4105B
`------------- 2Mx8, 5V, F/P
`- KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`2Mx8, 3.3V, F/P
`- KM4.8C2004B, KM4.8C2104B
`------------ 2Mx8, 5V, EDO
`2Mx8, 3.3V, EDO
`KM4.8V2004B, KM48V2104B
`--------1 Mx16, 5V, F/P(2nd gen.)
`- KM416C1000A, KM416C1200A
`KM416V1000A, KM416V1200A
`1 Mx16, 3.3V, F/P(2nd gen.)
`--------1 Mx16, 5V, EDO (2nd gen.)
`- KM416C1 004A, KM416C1204A
`KM416V1004A, KM416V1204A
`1Mx16, 3.3V, EDO (2nd gen.)
`- KM416C1000B, KM416C1200B
`-------~1 Mx16, 5V, F/P(3rd gen.)
`1 Mx16, 3.3V, F/P(3rd gen.)
`KM416V1000B, KM416V1200B
`------.:'-1 Mx16, 5V, EDO (3rd gen.)
`- KM416C1004B, KM416C1204B
`KM416V1004B, KM416V1204B
`1Mx16, 3.3V, EDO (3rd gen.)
`• The B-version is under development and will take the place of A-version from May 1996.
`
`.----------------- 241
`
`.----------------- 249
`
`.----------------- 257
`
`64M DRAM
`
`---------------- 16Mx4, 3.3V, F/P
`- KM44V16000A, KM44V16100A
`- KM44V16004A, KM44V161 04A ------------------ 16Mx4,3.3V, EDO
`- KM44C16000A, KM44C161 OOA ------------------ 16Mx4, 5V, F/P
`- KM44C16004A, KM44C161 04A ------------------ 16Mx4, 5V, EDO
`-------------------- 8Mx8, 3.3V, F/P
`. KM4.8V8000A, KM48V8100A
`- KM4.8V8004A, KM48V8104A
`-------------------- 8Mx8, 3.3V, EDO
`- KM48C8000A, KM4.8C.8100A
`-------------------- 8Mx.8, 5V, F/P
`- KM4.8C8004A, KM4.8C8104A
`-------------------- 8Mx8, 5V, EDO
`- KM416V4000A, KM416V4100A
`---------------- 4MX16, 3.3V, F/P
`- KM416V 4004A, KM416V 41 04A
`---------------- 4Mx16, 3.3V, EDO
`
`------------------ 267
`------------------ 275
`------------------ 283
`------------------ 291
`------------------ 299
`------------------ 307
`------------------ 315
`------------------ 323
`------------------ 331
`------------------ 340
`
`XILINX EXHIBIT 1018, Page 5
`
`

`

`TABLE OF CONTENTS (Continued)
`
`III. Timing Chart
`
`- F/P Mode, x1 Device
`------------------------------------------------------------------- 351
`- F/P Mode, x4 and x8 Device
`------------------------------------------------------------------- 365
`- F/P Mode, x16(2CAS) Device
`-------------------------------------------------------------------. 379
`- F/P Mode, x16(2WE) Device
`-------~-----------------------------------------------------------. 407
`- F/P Mode, Quad CAS Device
`------------------------------------------------------------------- 431
`- EDO Mode, x4 and x8 Device
`------------------------------------------------------------------- 445
`- EDO Mode, x16(2CAS) Device ------------------------------------------------------------------- 461
`- EDO Mode, x16(2WE) Device
`------------------------------------------------------------------- 491
`- EDO Mode, Quad CAS Device ------------------------------------------------------------------- 515
`
`IV. Package Dimension
`
`-------------------------------------------------------------------- 529
`
`v. Sales Offices and Manufacturer's Representives
`
`-------------------- 543
`
`XILINX EXHIBIT 1018, Page 6
`
`

`

`Changed Point 'in 196 DRAM Databook
`(Compared with 195 databook)
`
`Changed Point in '96 DRAM databook
`
`Remarks
`
`General
`
`- Remove TSOP lI(reverse) package
`- Remove 80ns version in 5V product
`- Remove SC Mode, WP8 Mode product
`- Remove 512Kx9 and 256Kx18 product
`
`Generation
`Change
`
`Device
`
`in '95
`
`in '96
`
`- None
`- 128Kx8, 64Kx16
`- C-version
`- 4Mx1, 1Mx4
`- 8-version
`- 512Kx8, 256Kx16
`- 16Mx1, 4Mx4, 2Mx8 - A-version
`- 1 Mx16
`- A-version
`
`- 16Mx4, 8Mx8
`
`-1st gen.
`
`- 4Mx16
`
`- None
`
`- 1 st gen.
`- C-Version
`- D-Version
`- 8-Version
`- A-Version &
`8-version
`- A-version
`(2nd gen.)
`- A-version
`
`1M
`
`- Add 128Kx8(FP/EDO), 64Kx16(2WE, FP/EDO)
`
`4M C-ver
`
`- Add EDO Quad CAS product
`- Remove DIP and ZIP package
`- Remove SC, WP8 Mode product
`
`4M 8IW
`
`- Remove 512Kx9 and 256Kx18 product
`
`16M
`(x1,x4,x8)
`
`16M
`(1Mx16)
`
`64M
`(x4,x8,x16)
`
`- Remove SC Mode WP8 Mode product
`- Add EDO Quad CAS product
`- Change the CMOS Standby current(ICC5) of Normal-power
`version from 1 rnA to 0.5mA
`
`- 50ns version will be available in 8-version(3rd gen.)
`from May 1 996.
`- Change the CMOS Standby current(ICC5) of Normal-power
`version from 1 rnA to 0.5mA
`
`- Add 4Mx16 product
`- Add 5V product
`- Change the Refresh cycle of Low -power version
`from 256ms t0128ms
`
`In "Remove - ", " - " means that "-" is not supported anymore.
`In "Add - ", "-" means that "-" is new product and is available from '96.
`
`- Add EDO Quad cA"S" product
`- Remove x9 & x18 product
`- Add EDO Quad CAS product
`- 8-ver. will be available
`from 3Q '96
`- Add 5V 64M DRAM
`: x4(4K) and x8(K)
`
`,
`
`- Changed package size
`from 400mil to 300mil
`
`XILINX EXHIBIT 1018, Page 7
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`CMOS DRAM
`
`2M x 8 Bit CMOS Dynamic RAM with Fast Page Mode
`
`DESCRIPTION
`
`This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed
`random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh
`cycle (2K Ref. or 4K Ref.), access time (-5, -6, -7 or -8), power consumption (Normal, Low power) and
`package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS
`refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, self-refresh operation is available
`in L-version.
`This 2Mx8 Fast Page mode DRAM family is fabricated using Samsung's advanced CMOS process to
`realize high band-width, low power consumption and high reliability. It may be used as main memory unit
`for high level computer, microcomputer and personal computer.
`
`FEATURES
`o Part Identification
`- KM48C2000B/B-L (5V, 4K Ref.)
`- KM48C2100B/B-L (5V, 2K Ref.)
`- KM48V2000B/B-L (3.3V, 4K Ref.)
`- KM48V2100B/B-L (3.3V, 2K Ref.)
`
`o Active Power Dissipation
`
`o Fast Page Mode operation
`o Byte ReadlWrite operation
`o CAS-before-l1AS refresh capability
`oRAS-only and Hidden refresh capability
`o Self-refresh capability (L-ver)
`o Fast parallel test mode capability
`o TIL(5V)/LVTIL(3.3V) compatible inputs and outputs
`o Early Write or output enable controlled write
`• JEDEC standard pinout
`• Available in Plastic SOJ and TSOP(II) packages
`• Single +5V±10% power supply (5V product)
`• Single +3.3V±O.3V power supply (3.3V product)
`
`o Refresh cycles
`
`FUNCTIONAL BLOCK DIAGRAM
`
`128ms
`
`RAS
`CAS
`W
`
`,-___ --.,. J-: ~::
`vee Generator I:J
`
`2K
`
`32ms
`
`o Performance range
`Speed, :tRAC tCAe ",IRC. l:_c'
`5V
`SOns 13ns 90ns 35ns
`-5
`60ns 15ns 110ns 40ns
`5V/3.3V
`-6
`70ns 20ns 130ns 45ns
`5V/3.3V
`-7
`80ns 20ns 150ns SOns
`3.3V
`-8
`
`Note)·' : 2K Refresh
`
`SAMSUNG ELECTRONIC CO. , LTD. reserves the right to
`change products and specifications without notice.
`
`tl"t'¥jiiW;
`
`ELECTRONICS
`
`217
`
`XILINX EXHIBIT 1018, Page 8
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`CMOS DRAM
`
`PIN CONFIGURATION (Top Views)
`
`• KM48C1V20(1 )OOBK
`
`• KM48CN20(1 )ooBS
`
`Vee
`DOO
`D01
`D02
`D03
`W
`RAS
`*A11(N.C)
`A10
`AO
`A1
`A2
`A3
`Vee
`
`Vss
`D07
`D06
`D05
`D04
`CAS
`Of
`A9
`A8
`A7
`A6
`A5
`A4
`Vss
`
`Vee
`DOO
`D01
`D02
`D03
`W
`RA5
`*A11(N.C)
`A10
`AO
`A1
`A2
`A3
`Vee
`
`* A11 is N.C for KM48CN2100B (5V/3.3V, 2K Ref. product)
`
`K : 300mil 28 SOJ
`S : 300mil 28 TSOP II
`
`Vss
`D07
`D06
`D05
`D04
`CAS
`OE
`A9
`A8
`A7
`A6
`A5
`A4
`Vss
`
`.,"{:f)idi•
`
`ELECl'RONICS
`
`218
`
`XILINX EXHIBIT 1018, Page 9
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`ABSOLUTE MAXIMUM RATINGS *
`
`CMOS DRAM
`
`* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
`Functional operation should be restricted to the conditions as detailed in the operational sections of
`this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
`device reliability.
`
`RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss, TA= 0 to 70°C)
`
`•
`
`*1 : Vcc+ 1.3V/1Sns(3.3V), Vcc+2.0Vl20ns(SV), Pulse width is measured at Vcc.
`*2: - 1.3V/1Sns(3.3V), - 2.0V/20ns(SV), Pulse width is measured at Vss.
`
`DC AND OPERATING CHARACTERISTICS
`(Recommended operating conditions unless otherwise noted.)
`
`3.3V
`
`5V
`
`tl"t'¥jiiW.
`
`ELECfRONICS
`
`219
`
`XILINX EXHIBIT 1018, Page 10
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`DC AND OPERATING CHARACTERISTICS
`(Recommended operating conditions unless otherwise noted.)
`
`Icc1
`
`Don't care
`
`-5
`-6
`-7
`-8
`
`Icc2
`
`Normal
`L
`
`Don't care
`
`Icc3
`
`Don't care
`
`Icc4
`
`Don't care
`
`Iccs
`
`Normal
`L
`
`Icc6
`
`Don't care
`
`Iccl
`
`L
`
`-5
`-6
`-7
`-8
`-5
`-6
`-7
`-8
`
`Don't care
`
`-5
`-6
`-7
`-8
`Don't care
`
`80
`70
`60
`
`80
`70
`60
`
`70
`60
`50
`
`0.5
`0.3
`
`80
`70
`60
`450
`
`100
`90
`80
`
`100
`90
`80
`
`80
`70
`60
`
`0.5
`0.3
`
`100
`90
`80
`400
`
`90
`80
`70
`
`2
`1
`90
`80
`70
`
`80
`70
`60
`
`1
`0.3
`90
`80
`70
`
`450
`
`CMOS DRAM
`
`110
`100
`90
`
`2
`1
`110
`100
`90
`
`90
`80
`70
`
`1
`0.3
`110
`100
`90
`
`400
`
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`mA
`
`mA
`mA
`mA
`mA
`mA
`mA
`
`I!A
`
`l.cc1' : Operating Current (RAS" and "CAS" cycling @tRC=min.)
`Icc2 : Standby Current (RAS"=CAS"=W=VIH )
`Icc3' : "RAS"-only Refresh Current (CAS"=VIH, RAS" cycling @tRC=min.)
`Icc4' : Fast Page Mode Current (RAS"=VIL,"CAS", Address cycling @tPC=min.)
`Iccs : Standby Current (RAS"=CAS"=W=Vcc-O.2V)
`Icc6' : "CAS"-Before-RAS" Refresh Current (RAS" and "CAS" cycling @tRC=min.)
`Iccl : Battery back-up current, Average power supply current, Battery back-up mode
`Input high voltage(VIH)=Vcc-O.2V, Input low voltage(VIL)=O.2V, "CAS"= O.2V
`Din = Don't care, TRc= 31.25iJS(4K/L-ver), 62.5iJS(2K1L-ver),
`TRAs= TRAsmin-300ns
`Iccs : Self Refresh Current
`"RAS"="CAS"=O.2V, W=OE=AO - A11 = Vcc-O.2V or O.2V, DaO - DQ7= Vcc-O.2V, O.2V or Open
`
`, NOTE: Icc1, Icc3, Icc4 and ICC6 are dependent on output loading and cycle rates. Specified values are
`obtained with the output open. Icc is specified as an average current. In Icc1, Icc3, and Iccs,
`address can be changed maximum once while RAS" =VIL. In Icc4, address can be changed
`maximum once within one fast page mode cycle time, tPC.
`
`tl:1:,¥jihitP
`
`ElECTRONICS
`
`220
`
`XILINX EXHIBIT 1018, Page 11
`
`

`

`KM48C20008, KM48C21 008
`KM48V20008, KM48V21 008
`
`CAPACITANCE (TA=25°C, Vcc=5V or 3.3V, 1=1 MHz)
`
`CMOS DRAM
`
`AC CHARACTERISTICS (O°C:,>TA:,>70°C, See note 1,2)
`Test condition (5V device)
`: Vcc=5.0V±10%, VihiViI=2.4/0.8V, VohiVoI=2.4/0.4V
`Test condition (3.3V device) : Vcc=3.3V±O.3V, VihNiI=2.010.8V, VohNoI=2.010.8V
`
`Note) *1 : 5V only, *2: 3.3V only
`
`.,&+)101•
`
`ELECTRONICS
`
`221
`
`XILINX EXHIBIT 1018, Page 12
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`CMOS DRAM
`
`AC CHARACTERISTICS (O°C:::;T~70°C, See note 1,2)
`Test condition (5V device)
`: Vcc=5.0V±10%, VnNiI=2.4/0:8V, VotNol=2.4/0.4V
`Test condition (3.3V device) : Vcc=3.3V±O.3V, VihNiI=2.0/0.8V, VotNOI =2.0/0.8V
`
`Note) *1 : 5V only, *2 : 3.3V only
`
`.,&:(110 liP
`
`ELECI'RONICS
`
`222
`
`XILINX EXHIBIT 1018, Page 13
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`CMOS DRAM
`
`, •
`
`Note) *1 : 5V only, *2 : 3.3V only
`
`tl:!t1¥jiiW;
`
`ELECTRONICS
`
`223
`
`XILINX EXHIBIT 1018, Page 14
`
`

`

`KM48C2000B, KM48C2100B
`KM48V2000B, KM48V2100B
`
`NOTES
`
`CMOS DRAM
`
`1. An initial pause of 200us is required after power-up followed by any 8 ROR or CSR cycles before
`proper device operatiori is achieved.
`2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are
`measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
`3. Measured with a load equivalent to 2 TTL(5V device)/1 TTL(3.3V device) loads and 100pF.
`4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a
`reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is
`controlled exclusively by tCAC.
`5. This parameter defines the time at which the output achieves the open circuit condition and is not
`referenced to Voh or Vol.
`6. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in
`the data sheet as electric characteristics only. If tWCS:<::tWCS(min), the cycle is an early write cycle
`and the data output will remain high impedance for the duration of the cycle. If tCWD:<::tCWD(min),
`tRWD:<::tRWD(min), tAWD:<::tAWD(min) and tCPWD:<::tCPWD(min), then the cycle is a read-modify-write
`cycle and the data output will contain the data read from the selected address. If neither of the above
`conditions is satisfied, the condition of the data out is indeterminate.
`7. Either tRCH or tRRH must be satisfied for a read cycle.
`8. These parameters are referenced to the 'CAS' falling edge in early write cycles and to the W falling edge
`in read-modify-write cycles.
`9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a
`reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is
`controlled by tAA.
`10. These specifications are applied in the test mode.
`11. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified
`values. These parameters should be specified in test mode cycles by adding 5ns to the specified value
`in this data sheet.
`12. For all of the refresh modes except for distributed CAS'-Sefore-RAS' refresh, 4096(4K Ref.)/2048(2K
`Ref.) cycles of burst refresh must be executed within 16ms before and after self-refresh in order to meet
`refresh specification.
`
`tl:!ti¥jlhi• ELEC1'RONICS
`
`224
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`XILINX EXHIBIT 1018, Page 15
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`© 1995 Semsung Electronics
`
`75 ir· 711>41ldll::ll:'- • • • •
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`XILINX EXHIBIT 1018, Page 16
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