United States Patent (19)
`Lee
`
`USOO5774.402A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,774,402
`Jun. 30, 1998
`
`54) INITIALIZATION CIRCUIT FOR A
`SEMCONDUCTOR MEMORY DEVICE
`
`75 Inventor: Cheol-Ha Lee, Kyungki-do, Rep. of
`Korea
`
`73 Assignee: Samsung Electronics Co., Ltd.,
`Suwon, Rep. of Korea
`
`21 Appl. No.: 697,356
`22 Filed:
`Aug. 23, 1996
`30
`Foreign Application Priority Data
`Aug. 23, 1995 KR Rep. of Korea .................. 26181/1995
`(51) Int. Cl. ................................................. G11C 7700
`52 U.S. Cl. ............................................. 365/191; 365/193
`58 Field of Search ..................................... 365/191, 193;
`327/143, 198, 217
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,984.215
`1/1991 Ushida ............................... 365/189.11
`5,305,271
`4/1994 Watanabe ................................ 365/205
`Primary Examiner David C. Nelms
`ASSistant Examiner Michael T. Tran
`Attorney, Agent, or Firm Marger, Johnson, McCollom &
`Stolowitz, PC
`ABSTRACT
`57
`An initialization circuit for a Semiconductor memory device
`includes an initialization Signal generator that generates an
`initialization Signal in response to a specific Sequence of
`reset control signals. A transfer unit activates a reset Signal
`for resetting various circuits on the device in response to
`either the initialization signal or a conventional power-up
`initialization signal. Thus, the initialization signal generator
`provides reliable initialization even if the power-up detec
`tion circuit fails. External row and column address Strobe
`Signals Serve as two reset control Signals, while a mode
`Selection signal Serves as another reset control Signal. The
`initialization signal is activated when the three reset control
`Signals are activated in the proper Sequence, then deactivated
`when one of the control Signals is deactivated.
`
`4,933,902 6/1990 Yamada et al. ......................... 327/198
`
`19 Claims, 4 Drawing Sheets
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`POWER SUPPLY
`VOLTAGE DETECTOR
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`ÖVCCH
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`14
`— —
`BACK-BAS
`VOLTAGE GEN
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`DSF
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`RASB
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`CASB
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`ØRST
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`XILINX EXHIBIT 1005
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`U.S. Patent
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`Jun. 30, 1998
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`Sheet 1 of 4
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`U.S. Patent
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`Jun. 30, 1998
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`Sheet 2 of 4
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`5,774,402
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`XILINX EXHIBIT 1005
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`U.S. Patent
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`Jun. 30, 1998
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`Sheet 4 of 4
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`XILINX EXHIBIT 1005
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`1
`INITIALIZATION CIRCUIT FOR A
`SEMCONDUCTOR MEMORY DEVICE
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`5,774,402
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`This application corresponds to Korean Patent Applica
`tion No. 26181/1995 filed Aug. 23, 1995 in the name of
`Samsung Electronics Co., Ltd., which is herein incorporated
`by reference.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to initialization
`circuits for Semiconductor memory devices and more par
`ticularly to initialization circuits which operate in response
`to an external control Signal, thereby providing reliable
`initialization when conventional power Supply reset circuits
`malfunction.
`2. Description of the Related Art
`AS the density and capacity of Semiconductor memory
`devices increases, their functional circuits become more
`complicated. Such devices require initialization circuits for
`resetting the various functional circuits within the chip.
`These initialization circuits are typically referred to as power
`on reset circuits and generate a reset Signal in response to a
`power Supply Voltage VCC being applied to the chip. The
`typical power on reset circuit operates by Sensing the level
`of the power Supply Voltage VCC and generating an initial
`ization Signal for a predetermined length of time when the
`power Supply Voltage reaches a predetermined level.
`FIG. 1 is a Schematic diagram of a prior art initialization
`circuit for a Semiconductor memory device. The circuit
`includes a power Supply voltage detector 12 for monitoring
`the State of the power Supply Voltage VCC and generating a
`power Supply detection signal (pVCCH. Aback bias Voltage
`generator 14 monitors a back bias voltage VBB and outputs
`a back bias detection signal (pDETB. An initialization signal
`generator 16 generates an initialization Signal (pNIT which
`is activated when the power supply detection signal pVCCH
`is activated and is deactivated when the back bias detection
`Signal (pDETB is activated. The initialization Signal genera
`tor 16 includes a flip-flop comprised of NAND gates 20 and
`22 which are cross coupled. The output terminal of NAND
`gate 20 is Set to a logic high-level by the power Supply
`detection signal and reset to a logic low-level by the back
`bias detection Signal.
`FIG. 2 is a timing diagram showing waveforms at various
`points in the circuit of FIG. 1. When the power supply
`Voltage VCC is first applied to the chip, the power Supply
`Voltage detector 12 monitors the Voltage level of the power
`supply VCC which gradually increases from 0 volts to an
`operating Voltage level, e.g. 3 Volts. The power Supply
`Voltage detector 12 activates the power Supply detection
`Signal (pVCCH when the power Supply Voltage reaches its
`operating level. The signal pVCCH is then deactivated by
`Switching to the logic low-level after a predetermined period
`of time. The power supply detection signal (pVCCH is then
`applied to the input terminal of an inverter 18 which sets the
`flip-flop, thereby activating the initialization signal (pNIT
`through inverters 24 and 26. The initialization signal (pNIT
`is maintained in its active high State until the back bias
`detection signal (pDETB is activated by the back bias voltage
`generator 14, thereby resetting the flip-flop.
`The back bias Voltage generator 14 operates from the
`power Supply VCC and generates a negative Voltage -V
`after the input power supply voltage VCC is stabilized at its
`65
`operational level, e.g., about 3 Volts. When the negative
`Voltage -V is Stabilized, e.g., at approximately -3 volts, the
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`back bias generator 14 generates the back bias detection
`signal (pDETB by driving it to its active low-level, thereby
`resetting the flip-flop in the initialization generator 16.
`A problem with the initialization circuit of FIG. 1 is that
`it may malfunction if the power supply voltage VCC is
`unstable input. For example, the rise time of the power
`supply voltage VCC is typically about 200 microseconds.
`However, if the power Supply Voltage level rises very
`Slowly, e.g., over the course of Several milliseconds, the
`power supply voltage detector 12 of FIG. 1 may
`malfunction, thereby generating an abnormal power Supply
`detection signal pVCCH. Thus, the initialization signal
`(pINIT may be extremely short or may not be generated at all,
`thereby failing to initialize the circuits within the chip.
`
`SUMMARY OF THE INVENTION
`It is therefor an object of the invention to reliably initialize
`a Semiconductor memory device when a power-up reset
`circuit malfunctions.
`A further object of the invention is to initialize a semi
`conductor memory device in response to external logic
`Signals.
`On aspect of the present invention is an initialization
`circuit for a Semiconductor memory device comprising: an
`initialization Signal generator that generates an initialization
`Signal responsive to a plurality of control Signals being
`activated in a predetermined Sequence, the initialization
`Signal generator including: a plurality of input terminals for
`receiving the plurality of control signals, an output terminal
`for transmitting the initialization Signal, and a control clock
`generator coupled to the plurality of input terminals, the
`control clock generator generating a control clock signal
`responsive to the control Signals.
`Another aspect of the present invention is an initialization
`circuit for a Semiconductor memory device comprising: a
`first initialization Signal generator that generates a first
`initialization Signal responsive to a Sequence of control
`Signals, a Second initialization Signal generator that gener
`ates a Second initialization Signal responsive to a power
`Supply start-up; and a transfer unit coupled to the first and
`Second initialization signal generators, the transfer unit
`generating a reset Signal responsive to the first and Second
`initialization signals.
`A further aspect of the present invention is a method for
`initializing a circuit in a Semiconductor memory device
`comprising: generating a Sequence of control signals, acti
`Vating a first initialization Signal responsive to the Sequence
`of control signals, and initializing the circuit responsive to
`activating the first initialization signal. The method further
`includes: activating a Second initialization signal responsive
`to a power Supply start-up; activating a reset Signal respon
`Sive to either the Second initialization signal or the first
`initialization signal; and initializing the circuit responsive to
`the reset Signal.
`The foregoing and other objects, features and advantages
`of the invention will become more readily apparent from the
`following detailed description of a preferred embodiment of
`the invention which proceeds with reference to the accom
`panying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a Schematic diagram of a prior art initialization
`circuit for a Semiconductor memory device.
`FIG. 2 is a timing diagram showing waveforms of Signals
`at various points within the circuit of FIG. 1.
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`FIG. 3 is a Schematic diagram of an embodiment of an
`initialization circuit in accordance with the present inven
`tion.
`FIG. 4 is a timing diagram showing waveforms of Signals
`at various points within the circuit of FIG. 3.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`Referring to FIG. 3, an embodiment of an initialization
`circuit for a Semiconductor memory device in accordance
`with the present invention includes a first initialization
`Signal generator 46, a Second initialization Signal generator
`16 and a transfer unit 56. The first initialization signal
`generator generates a first initialization signal (pSET in
`response to a Sequence of reset control signals DSF, RASB,
`and CASB. The Second initialization signal generator 16 is
`essentially the same as the circuit of FIG. 1 and generates a
`Second initialization Signal (pNIT in response to the power
`up of a power supply VCC. The transfer unit 56 generates a
`reset Signal (pRST for resetting a circuit within the memory
`device responsive to the first and Second initialization Sig
`nals.
`In operation, the transfer unit 56 activates the reset Signal
`(pRST in response to the activation of either the first or
`second initialization signals (pSET or (pNIT. If the second
`initialization signal (pNIT is activated, it is latched by the
`transfer unit 56 and the reset signal (pRST remains active
`until the first initialization signal generator 46 resets the
`latch by deactivating the first initialization signal pSET by
`driving it to a low logic level. Thus, the reset signal (pRST
`is activated in response to either the power Supply power-up
`or the reset information. Therefore, if the power-up reset
`circuit malfunctions, the circuitry will Still be properly
`initialized by the first initialization signal pSET.
`More detailed consideration will now be given to the
`structure of the circuit of FIG. 3. The first initialization
`signal generator 46 includes a first input buffer 30 which is
`connected to a first input terminal for receiving a first control
`signal CASB. Buffer 30 generates a column address clock
`signal pC in response to CASB. A second input buffer 28 is
`connected to a Second input terminal to receive a Second
`control signal RASB. Buffer 28 generates a row address
`clock Signal (pR in response to RASB. The first control Signal
`CASB is typically a column address Strobe Signal, and the
`Second control Signal RASB is typically a row address
`strobe signal. A third input buffer 32 is connected to a third
`input terminal and receives a mode Selection signal DSF for
`generating a mode Selection clock Signal (pDSF Input buffer
`32 is also connected to a delay clock signal (pMSH which is
`generated by delaying the row address clock signal (pR. The
`delay clock signal (pMSH is used to latch the mode selection
`clock signal (pR.
`A control clock generator comprises NAND gates 34 and
`36 and generates a control clock signal (pCTL responsive to
`(pR and (pC. The first NAND gate includes a first input
`terminal connected to an output terminal of input buffer 28,
`a Second input terminal connected to the output terminal of
`NAND gate 36, and an output terminal which forms the
`output terminal of the control clock generator for transmit
`ting the control clock signal (pCTL. The second NAND gate
`36 includes a first input terminal connected to an output
`terminal of buffer 30, and a second input terminal connected
`to the output terminal of NAND gate 34. A third NAND gate
`38 has a first input terminal connected to the output terminal
`of buffer 28, a second input terminal connected to the output
`terminal of NAND gate 34, and an output terminal for
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`generating a Second control clock signal pCR in response to
`the signals (pR and (pCTL. A two input NOR gate 40 has a
`first input terminal connected to the output terminal of
`NAND gate 38, a second input terminal connected to an
`output terminal of buffer 32 through an inverter 33, and an
`output terminal for generating the first initialization Signal
`(pSET. A transmission gate 42 is connected between the
`output terminal of NOR gate 40 and an output terminal of
`the first initialization signal generator 46. The transfer gate
`42 is driven by a delay clock signal (pMSH which is
`connected directly to the non-inverting control terminal of
`transmission gate 42 and which is also connected to the
`inverting control terminal through an inverter 44.
`The transfer unit 56 includes a two input NOR gate 50
`having a first input terminal connected to the output terminal
`of the first initialization signal generator 46, a Second input
`terminal connected to an output terminal of Second initial
`ization signal generator 16, and an output terminal which is
`connected back to its first input terminal through an inverter
`52. An inverter 54 has an input terminal connected to the
`output terminal of NOR gate 50 and an output terminal
`which forms the output terminal of the transfer unit 56 for
`Sending the reset Signal (pRST to a circuit to be initialized
`within the chip.
`More detailed consideration will now be given to the
`operation of the embodiment of the present invention shown
`in FIG. 3. When the power supply VCC is first powered-up,
`the Second initialization Signal generator 16 activates the
`second initialization signal (pNIT as shown in FIG. 2, thus
`driving the second input terminal of NOR gate 50 to a
`high-logic level. At this time, the first input terminal of NOR
`gate 50 which receives the signal pSET is at a low logic
`level. The transfer unit 56 activates the reset signal (pRST in
`response to the Second initialization Signal (pNIT and
`latches the Second initialization signal. Thus, all circuits
`within the chip which are connected to the output terminal
`of transfer unit 56 is held in the initialized state.
`In the meantime, if the reset signals DSF, RASB and
`CASB generate a predetermined bit pattern in the proper
`Sequence, the first initialization signal generator activates
`the first initialization signal pSET. For this to occur, the reset
`control signals DSF, RASB, and CASB must be activated in
`the CBR (CAS before RAS) mode. The mode selection
`clock signal (pDSF is first activated, i.e., driven to a high
`logic level. The mode selection clock signal (pDSF is
`latchated in the high state by the delay clock signal (pMSH
`which is generated by delaying the the row address clock
`signal (pR. If the first control signal CASB is then activated
`by being driven to a low logic State, the control clock signal
`(pCTL is driven to the active high logic level. Then, if the
`second control signal RASB is driven to the active low logic
`level, the Signal pR activates the Second control clock signal
`(pCR through NAND gate 38. NOR gate 40 then combines
`the signals (pCR and (pDSF to generate the first initialization
`signal cpSET at the output terminal of NOR gate 40. Trans
`mission gate 42 then transmits the signal pSET from NOR
`gate 40 to the input terminal of NOR gate 50 in response to
`the activation of the delay signal (pMSH.
`The transfer unit 56 combines the first initialization signal
`(pSET and the second initialization signal (pNIT and acti
`Vates the reset signal (pRST by driving it to a high logic level,
`thereby initializing the circuits within the chip. The reset
`signal (pRST remains at the logic high-level until the first
`control Signal CASB is deactivated and driven to the logic
`high-level. When the signal CASB Switches to the high
`level, the column address clock (pC Switches to a logic
`low-level, thereby driving the control clock (pCTL to the
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`low-logic level. Therefore, if signal CASB Switches to the
`high logic level while the second control signal RASB is in
`the active low state, the first initialization signal pSET is
`deactivated, which in turn, deactivates the reset Signal (pRST
`AS explained above, an initialization circuit according to
`the present invention generates a reset Signal in response to
`either a power Supply power-up or a Sequence of reset
`Signals. Thus, the present invention can properly reset cir
`cuits in the chip even when the power-up reset circuit
`malfunctions.
`In the embodiment of FIG. 3, the first and second initial
`ization signals are Supplied to individual circuits via one
`transfer unit. However, the improved reset operation of the
`present invention can also be obtained with an embodiment,
`which independently couples the two initialization signals to
`the various circuits to be reset.
`Having described and illustrated the principals of the
`invention in a preferred embodiment thereof, it should be
`apparent that the invention can be modified in arrangement
`and detail without departing from Such principals. We claim
`all modifications and variations coming within the Spirit and
`Scope of the following claims.
`I claim:
`1. An initialization circuit for a Semiconductor memory
`device comprising:
`an initialization signal generator that generates an initial
`ization Signal responsive to a plurality of control Sig
`nals including a row address Signal and a column
`address signal wherein the initialization Signal genera
`tor activates the initialization signal only when the
`column address Signal is activated before the row
`address signal, the initialization signal generator
`including:
`a plurality of input terminals for receiving the plurality
`of control signals,
`an output terminal for transmitting the initialization
`Signal; and
`a control clock generator coupled to the plurality of
`input terminals, the control clock generator generat
`ing a control clock Signal responsive to the control
`Signals.
`2. An initialization circuit for a Semiconductor memory
`device comprising:
`an initialization Signal generator that genrates an initial
`ization Signal responsive to a plurality of control Sig
`nals being activated in a predetermined Sequence, the
`initialization signal generator including:
`a plurality of input terminals for receiving the plurality
`of control signals,
`an output terminal for transmitting the initialization
`Signal; and
`a control clock generator coupled to the plurality of
`input terminals, the control clock generator generat
`ing a control clock Signal responsive to the control
`Signals;
`wherein;
`the plurality of input terminals includes a first input
`terminal for receiving a first control Signal, a Second
`input terminal for receiving a Second control Signal,
`and a third input terminal for receiving a third control
`Signal;
`the control clock generator includes a latch coupled to the
`first and Second input terminals, the latch generating
`the control clock Signal responsive to the first and
`Second control Signals, and
`the initialization signal generator includes a logic gate
`coupled to the latch and the third input terminal for
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`generating the initialization signal responsive to the
`control clock Signal and the third control Signal.
`3. An initialization circuit according to claim 2 wherein
`the latch includes:
`a first NAND gate having a first input terminal coupled to
`the Second input terminal of the initialization Signal
`generator, a Second input terminal, and an output ter
`minal for generating the control clock signal; and
`a Second NAND gate having a first input terminal coupled
`to the first input terminal of the initialization Signal
`generator, a Second input terminal coupled to the output
`terminal of the first NAND gate, and an output terminal
`coupled to the second input terminal of the first NAND
`gate.
`4. An initialization circuit according to claim 3 wherein
`the initialization Signal generator further includes a third
`NAND gate having a first input terminal coupled to the first
`input terminal of the first NAND gate, a second input
`terminal coupled to the output terminal of the first NAND
`gate, and an output terminal for generating a Second control
`clock signal.
`5. An initialization circuit according to claim 4 wherein
`the logic gate is a NOR gate having a first input terminal
`coupled to the output terminal of the third NAND gate, a
`Second input terminal coupled to the third input terminal of
`the initialization Signal generator, and an output terminal for
`generating the initialization signal.
`6. An initialization circuit according to claim 5 wherein
`the initialization Signal generator further includes an inverter
`having an input terminal coupled to the third input terminal
`of the initialization signal generator and an output terminal
`coupled to the first input terminal of the NOR gate.
`7. An initialization circuit according to claim 2 wherein
`the initialization Signal generator includes:
`a first input buffer coupled between the first input terminal
`of the initialization Signal generator and the latch;
`a Second input buffer coupled between the Second input
`terminal of the initialization signal generator and the
`latch; and
`a third input buffer coupled between the third input
`terminal of the initialization signal generator and the
`logic gate.
`8. An initialization circuit according to claim 2 wherein
`the initialization Signal generator further includes a trans
`mission gate having a controlled current path coupled
`between the output terminal of the logic gate and the output
`terminal of the initialization Signal generator and a control
`terminal for receiving a mode Selection clock Signal.
`9. An initialization circuit according to claim 8 wherein:
`the transmission gate further includes a Second control
`terminal; and
`the initialization Signal generator further includes a Sec
`ond inverter having an output terminal coupled to the
`Second control terminal of the transmission gate and an
`input terminal for receiving the mode Selection Signal.
`10. An initialization circuit for a Semiconductor memory
`device comprising:
`a first initialization Signal generator that generates a first
`initialization signal responsive to a Sequence of control
`Signals;
`a Second initialization Signal generator that generates a
`Second initialization Signal responsive to a power Sup
`ply Start-up; and
`a transfer unit coupled to the first and Second initialization
`Signal generators, the transfer unit generating a reset
`Signal responsive to the first and Second initialization
`Signals.
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`11. An initialization circuit according to claim 10 wherein
`the transfer unit includes a latch that activates the reset
`Signal responsive to the activation of either the first or
`Second initialization Signals and deactivates the reset Signal
`responsive to the deactivation of the first initialization
`Signal.
`12. An initialization circuit according to claim 11 wherein
`the latch includes:
`a NOR gate having a first input terminal for receiving the
`first initialization signal, a Second input terminal for
`receiving the Second initialization signal, and an output
`terminal; and
`an inverter having an input terminal coupled to the output
`terminal of the NOR gate and an output terminal
`coupled to the first input terminal of the NOR gate.
`13. An initialization circuit according to claim 12 wherein
`the transfer unit further includes an inverter having an input
`terminal coupled to the output terminal of the NOR gate and
`an output terminal for transmitting the reset Signal.
`14. A method for initializing a circuit in a Semiconductor
`memory device comprising:
`generating a Sequence of control Signals including a
`column address Signal and a row address Signal;
`activating a first initialization Signal responsive to the
`Sequence of control Signals only when the column
`address Signal is activated before the row address
`Signal; and
`initializing the circuit responsive to activating the first
`initialization signal.
`15. A method according to claim 14 wherein generating
`the sequence of control signals further includes activating a
`mode Selection signal.
`16. A method for initializing a circuit in a Semiconductor
`memory device comprising:
`generating a Sequence of control Signals including acti
`Vating a first control Signal and activating a Second
`control Signal;
`activating a first initialization Signal responsive to the
`Sequence of control Signals,
`initializing the circuit responsive to activating the first
`initialization signal;
`deactivating the first control Signal; and
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`deactivating the first initialization Signal responsive to
`deactivating the first control Signal.
`17. A method for initializing a circuit in a Semiconductor
`memory device comprising:
`generating a Sequence of control Signals,
`activating a first initialization signal responsive to the
`Sequence of control signals,
`initializing the circuit responsive to activating the first
`initialization signal;
`activating a Second initialization Signal responsive to a
`power Supply start-up;
`activating a reset Signal responsive to either the Second
`initialization signal or the first initialization Signal; and
`initializing the circuit responsive to the reset Signal.
`18. A method according to claim 16 further including:
`activating a Second initialization Signal responsive to a
`power Supply start-up;
`latching the Second initialization Signal;
`activating a reset Signal responsive to latching the Second
`initialization signal; and
`deactivating the reset Signal responsive to deactivating the
`first initialization signal.
`19. A method for initializing a circuit in a Semiconductor
`memory device comprising:
`generating a Sequence of control Signals,
`activating a first initialization signal responsive to the
`Sequence of control signals,
`initializing the circuit responsive to activating the first
`initialization signal;
`wherein the Semiconductor memory device further
`includes a Second circuit to be initialized, and wherein
`the method further includes:
`activating a Second initialization Signal responsive to a
`power Supply start-up;
`initializing the circuit responsive to activating the Second
`initialization signal; and
`initializing the Second circuit responsive to activating the
`first initialization signal.
`
`k
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`XILINX EXHIBIT 1005
`Page 9
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