UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC.,
`
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`
`Patent Owner.
`
`DECLARATION OF STEPHEN W. MELVIN
`
`Case No. IPR2023-00516
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`XILINX EXHIBIT 1003
`Page 1
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`TABLE OF CONTENTS
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`
`Introduction ...................................................................................................... 1 
`I. 
`Background and Qualifications ....................................................................... 1 
`II. 
`III.  Documents and Materials Considered ............................................................. 3 
`IV.  Relevant Legal Principles ................................................................................ 4 
`V. 
`Person of Ordinary Skill in the Art ................................................................ 11 
`VI. 
`’589 Patent ..................................................................................................... 12 
`VII.  Technology Background ................................................................................ 24 
`VIII.  Claim Construction ........................................................................................ 30 
`IX.  Summary of Opinions .................................................................................... 30 
`X. 
`Claims 1, 9, 11, and 13 are Anticipated by Kocis ......................................... 32 
`XI.  Claims 2, 8, 10, and 12 are Obvious Over Kocis in Combination with
`JESD 21-C ..................................................................................................... 47 
`XII.  Claims 1 and 11 are Anticipated by or Obvious Over Lee ........................... 58 
`XIII.  Claims 1 and 11 are Obvious Over Lee in Combination with Iketani .......... 74 
`XIV.  Claims 2, 8, 10, and 12 are Obvious Over Lee in Combination with
`JESD 21-C ..................................................................................................... 83 
`XV.  Claims 2, 8, 10, and 12 are Obvious over Lee in Combination with
`Iketani and JESD 21-C .................................................................................. 92 
`XVI.  Claims 9 and 13 are Obvious Over Lee in Combination with Kocis ............ 95 
`XVII. Claims 9 and 13 are Obvious Over Lee in Combination with Iketani
`and Kocis ....................................................................................................... 99 
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`Exhibit No.
`1001
`1002
`1003
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`TABLE OF EXHIBITS
`Description
`U.S. Patent No. 6,157,589 (the “’589 Patent”)
`U.S. Prosecution History of the ’589 Patent
`Declaration of Stephen W. Melvin
`U.S. Patent No. 5,559,753 to Kocis entitled “Apparatus and
`Method for Preventing Bus Contention During Power-Up in a
`Computer System With Two or More DRAM Banks” (“Kocis”)
`U.S. Patent No. 5,774,402 to Lee entitled “Initialization Circuit
`for a Semiconductor Memory Device” (“Lee”)
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Compilation of Releases 1 through 7, dated
`January 1997 (“JESD 21-C”)
`U.S. Patent No. 5,703,510 to Iketani et al. entitled “Power On
`Reset Circuit For Generating Reset Signal at Power On”
`(“Iketani”)
`Prosecution History of EPO Patent Application No. 99 113 048.5
`(Original)
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (Original)
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (English Translation)
`Japanese Patent Publication No. JP 09 106668 A to Samsung
`Electronics Co. Ltd. dated April 22, 1997 (“Tetsuka”)
`Declaration of Julie Carson
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Release 7, dated January 1997
`Scheduling Order, Polaris Innovations Limited v. Xilinx, Inc.,
`1:22-cv-00174-RGA, Docket No. 20 (May 31, 2022)
`United States District Courts — Federal Court Management
`Statistics, National Judicial Caseload Profile (June 30, 2022),
`available at https://www.uscourts.gov/sites/
`default/files/fcms_na_distprofile0630.2022_0.pdf
`Motion Success for Stay Pending IPR before Judge Richard G.
`Andrews in the District of Delaware (Docket Navigator data
`from 2020 to 1/20/2023)
`Excerpt of Micron Technology, Inc., “DRAM Data Book”
`(1992)
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`Exhibit No.
`1018
`
`1019
`
`Description
`Excerpt of Samsung Electronics Co., Ltd., “Data Book: DRAM”
`(Dec. 1995)
`Samsung Electronics, “4M x 8Bit x 4 Banks Synchronous
`DRAM” Doc. No. KM48S16030, Rev. 2 (March 1998)
`
`
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`I.
`
`Introduction
`
`1.
`
`I have prepared this Declaration in connection with Xilinx, Inc.’s
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589 (the “’589 Patent”)
`
`(Ex. 1001), which is to be filed concurrently with this Declaration.
`
`2.
`
`In the course of preparing this Declaration, I reviewed the ’589 Patent,
`
`its prosecution file history, as well as the other documents discussed in this
`
`Declaration.
`
`3.
`
`I have been retained by Xilinx, Inc. (“Xilinx” or “Petitioner”) as an
`
`expert in the fields of computer engineering, computer memory systems and related
`
`technologies. My employer is being compensated at my normal consulting rate for
`
`my time. My compensation is not dependent on and in no way affects the substance
`
`of my statements in this Declaration. I have no financial interest in Xilinx, the ’589
`
`Patent or the owner of the ’589 Patent.
`
`II. Background and Qualifications
`
`4.
`
`I received a Ph.D. in Computer Science from the University of
`
`California at Berkeley in 1991 and a B.S. in Electrical Engineering and Computer
`
`Science from the University of California at Berkeley in 1982. I have more than 40
`
`years of experience in computer science and computer engineering. I am an inventor
`
`on over 45 patents, and I am a registered patent agent before the USPTO.
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`5. My Ph.D. research areas
`
`included high-performance computer
`
`architecture and microarchitecture and microcode-based system performance
`
`analysis tools. From September 2001 through April 2002, I was a Visiting Scholar
`
`at the University of Texas, Austin, where I directed graduate students in research in
`
`the area of high-performance computer architecture.
`
`6.
`
`In May 2001, I co-founded and was the Chief Architect of Flowstorm,
`
`Inc., a start-up company based in Silicon Valley, where I defined and guided the
`
`overall chip architecture for a multithreaded packet processor. From March 2000
`
`through May 2001, I worked as the Senior CPU Architect at Clearwater Networks,
`
`where I was involved in defining the architecture and microarchitecture of
`
`Clearwater’s CNP810S multithreaded network processor.
`
` Both of
`
`those
`
`professional experiences required a deep understanding of memory devices and
`
`memory interfacing techniques, including DRAM devices conforming to JEDEC
`
`standards.
`
`7.
`
`From 1983 to 2020, I was the President of Zytek Communications
`
`Corporation (“Zytek”). Zytek was an engineering, consulting, and small-scale
`
`manufacturing company that provided intellectual property consulting services as
`
`well as services related to the design, implementation, and testing of embedded
`
`systems. Zytek’s general areas of activity included industrial control and
`
`measurement, Internet-related services, hard disk analysis and file recovery, and
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`computer engineering research services. Through my work at Zytek, I have designed
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`numerous microprocessor-based embedded systems, including analog and digital
`
`circuit design, firmware development for embedded microcontrollers, and software
`
`development for host interfacing, product development, and debugging. My designs
`
`for embedded systems have all involved an understanding of memory devices and
`
`interfacing between microprocessors and memory devices.
`
`8.
`
`I am currently employed as a Principal with Exponent, Inc., which is an
`
`international multidisciplinary engineering and scientific consulting firm.
`
`9.
`
`I am a member of the Institute of Electrical and Electronics Engineers
`
`(IEEE) and the Association for Computing Machinery (ACM).
`
`10.
`
`I served as General Chair of the 45th Annual International Symposium
`
`on Microarchitecture (Micro-45), held in Vancouver in December of 2012. I also
`
`served as co-chair of the 29th Annual International Symposium on Microarchitecture
`
`(Micro-29), held in Paris in December of 1996.
`
`11. Additional details regarding my employment and academic history are
`
`included in my curriculum vitae, attached hereto as Appendix A.
`
`III. Documents and Materials Considered
`
`12.
`
`In forming my opinions, in addition to my knowledge, education,
`
`training, and experience, I have considered the materials cited in this Declaration
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`and the documents and things that I have obtained, or that have been provided to me,
`
`as listed above in the Table of Exhibits.
`
`13.
`
`I may rely upon these materials and/or additional materials to respond
`
`to arguments raised by the Patent Owner. I may also consider additional documents
`
`and information in forming any necessary opinions, including documents that may
`
`not yet have been provided to me. My consideration of materials in relation to this
`
`Declaration is ongoing and I will continue to review any new materials as it is
`
`provided. This Declaration represents only those opinions I have formed to date and
`
`I may supplement or amend this Declaration if additional facts or information that
`
`affects my opinions becomes available.
`
`IV. Relevant Legal Principles
`
`14.
`
`I am not an attorney. I offer no opinions on the law. But counsel has
`
`informed me of legal standards that apply to the issue of patent validity. I have
`
`applied these standards in arriving at my conclusions.
`
`15.
`
`I understand that in an inter partes review the petitioner has the burden
`
`of proving a proposition of unpatentability by a preponderance of the evidence. I
`
`understand this standard is different from the standard that applies in a district court,
`
`where I understand a challenger bears the burden of proving invalidity by clear and
`
`convincing evidence.
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`16.
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`I understand that a patent claim is invalid based on anticipation if a
`
`single prior art reference discloses all of the features of that claim, and does so in a
`
`way that enables one of ordinary skill in the art to make and use the invention. Each
`
`of the claim features may be expressly or inherently present in the prior art reference.
`
`I understand that if the prior art necessarily functions in accordance with, or includes
`
`a claim’s feature, then that prior art inherently discloses that feature. I have relied on
`
`this understanding in expressing the opinions set forth below.
`
`17.
`
`I understand that a prior art reference describes the claimed invention
`
`if it either expressly or inherently describes each and every feature set forth in the
`
`claim; i.e., in determining whether a single item of prior art anticipates a patent
`
`claim, one should take into consideration not only what is expressly disclosed in that
`
`item, but also what is inherently present as a natural result of the practice of the
`
`system or method disclosed in that item.
`
`18.
`
`I understand that to establish inherency, the evidence must make clear
`
`that the missing descriptive matter is necessarily present in the item of prior art and
`
`that it would be so recognized by persons of ordinary skill in the art. I also understand
`
`that prior art use of the claimed patented invention that was accidental,
`
`unrecognized, or unappreciated at the time of filing can still be an invalidating
`
`anticipation.
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`19.
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`I understand that although multiple prior art references may not be
`
`combined to show anticipation, additional references may be used to interpret the
`
`allegedly anticipating reference and shed light on what it would have meant to those
`
`skilled in the art at the time of the invention. These additional references must make
`
`it clear that the missing descriptive matter in the patent claim is necessarily present
`
`in the allegedly anticipating reference, and that it would be so recognized by persons
`
`of ordinary skill in the art.
`
`20.
`
`I understand that a patent may not be valid even though the invention
`
`is not identically disclosed or described in the prior art if the differences between the
`
`subject matter sought to be patented and the prior art are such that the subject matter
`
`as a whole would have been obvious to a person having ordinary skill in the art in
`
`the relevant subject matter at the time the invention was made.
`
`21. To determine if a claim is obvious, the following factors should be
`
`considered: (1) the level of ordinary skill in the art at the time the invention was
`
`made; (2) the scope and content of the prior art; (3) the differences between the
`
`claimed invention and the prior art; and (4) secondary considerations, including
`
`evidence of commercial success, long-felt but unsolved need, unsuccessful attempts
`
`by others, copying of the claimed invention, unexpected and superior results,
`
`acceptance and praise by others, independent invention by others, and the like.
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`22. For example, I understand that the combination of familiar elements
`
`according to known methods is likely to be obvious when it does no more than yield
`
`predictable results. I also understand that an obviousness analysis need not seek out
`
`precise teachings directed to the specific subject matter of the challenged claim
`
`because a court can take account of the inferences and/or creative steps that a person
`
`of ordinary skill in the art would employ.
`
`23.
`
`I understand that the following rationales may be used to determine
`
`whether a piece of prior art can be combined with other prior art or with other
`
`information within the knowledge of one of ordinary skill in the art:
`
` Combining prior art elements according to known methods to yield
`predictable results;
`
` Simple substitution of one known element for another to obtain predictable
`results;
`
` Use of known techniques to improve similar devices (methods, or
`products) in the same way;
`
` Applying a known technique to a known device (method, or product) ready
`for improvement to yield predictable results;
`
` “Obvious to try” - choosing from a finite number of identified, predictable
`solutions, with a reasonable expectation of success;
`
` Known work in one field of endeavor may prompt variations of it for use
`in either the same field or a different one based on design incentives or
`other market forces if the variations would have been predictable to one of
`ordinary skill in the art; or
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` Some teaching, suggestion, or motivation in the prior art that would have
`led one of ordinary skill to modify the prior art reference or to combine
`prior art reference teachings to arrive at the claimed invention.
`
`24.
`
`I understand that when a work is available in one field of endeavor,
`
`design incentives and/or other market forces, for example, can prompt variations of
`
`it, either in the same field or a different one. Moreover, if a person of ordinary skill
`
`can implement a predictable variation, I understand that that likely bars its
`
`patentability.
`
`25.
`
`I understand that obviousness must be tested as of the time the invention
`
`was made. I understand that the test for obviousness is what the combined teachings
`
`of the prior art references would have suggested, disclosed, or taught to one of
`
`ordinary skill in the art. In particular, it is my understanding that a patent claim is
`
`invalid based upon obviousness if it does nothing more than combine familiar
`
`elements from one or more prior art references or products according to known
`
`methods to yield predictable results. For example, I understand that where a
`
`technique has been used to improve one device, and a person of ordinary skill in the
`
`art would have recognized that it would improve similar devices in the same way,
`
`using that technique is obvious. I understand that obviousness can be proved by
`
`showing that a combination of elements was obvious to try, i.e.: that it does no more
`
`than yield predictable results; implements a predictable variation; is no more than
`
`the predictable use of prior art elements according to their established functions; or
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`when there is design need or market pressure to solve a problem and there are a finite
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`number of identified, predictable solutions. I have been further informed that when
`
`a patent claim simply arranges old elements with each element performing the same
`
`function it had been known to perform and yields results no more than one would
`
`expect from such an arrangement, the combination is obvious.
`
`26.
`
`I understand that another factor to be considered is common sense. For
`
`example, I understand that common sense teaches that familiar items may have
`
`obvious uses beyond their primary purposes, and, in many cases, a person of
`
`ordinary skill will be able to fit the teachings of multiple patents together like pieces
`
`of a puzzle.
`
`27.
`
`I understand that the Supreme Court articulated additional guidance for
`
`obviousness in its KSR decision. My understanding is that the Supreme Court said
`
`that technical people of ordinary skill look for guidance in other solutions to
`
`problems of a similar nature, and that the obviousness inquiry must track reality, and
`
`not legal fictions. I have relied on these understandings in expressing the opinions
`
`set forth below.
`
`28.
`
`I understand that a new use of an old product or material cannot be
`
`claimed as a new product; the apparatus or system itself is old and cannot be
`
`patented. I further understand that, in general, merely discovering and claiming a
`
`new benefit to an old process cannot render the process newly patentable.
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`29.
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`I understand that, for purposes of my analysis in this inter partes review
`
`proceeding, the terms appearing in the patent claims should be interpreted according
`
`to their “ordinary and customary meaning.” In determining the ordinary and
`
`customary meaning, the words of a claim are first given their plain meaning that
`
`those words would have had to a person of ordinary skill in the art (“POSITA”). I
`
`understand that the structure of the claims, the specification, and the file history also
`
`may be used to better construe a claim insofar as the plain meaning of the claims
`
`cannot be understood. Moreover, treatises and dictionaries may be used, albeit under
`
`limited circumstances, to determine the meaning attributed by a POSITA to a claim
`
`term at the time of filing. I have followed this approach in my analysis, and for all
`
`of the claim terms considered in this declaration, I have applied the plain and
`
`ordinary meaning of those terms.
`
`30.
`
`I also understand that the words of the claims should be interpreted as
`
`they would have been interpreted by a POSITA at the time the alleged invention was
`
`made (not today). I have been asked to use the priority date of June 30, 1998.
`
`However, the plain meanings/interpretations that I employed in my analysis below
`
`would have also been correct if the date of invention was anywhere within the mid
`
`to late 1990s.
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`V.
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`Person of Ordinary Skill in the Art
`
`31.
`
`In order to determine the characteristics of a POSITA of the ’589
`
`Patent, I have used June 30, 1998 as the relevant time frame. My understanding is
`
`that this is the priority date of the application that resulted in the ’589 Patent. For
`
`purposes of this Declaration, any reference to the priority date of the ’589 Patent is
`
`intended to refer to this June 30, 1998 date.
`
`32.
`
`In determining the characteristics of a person of ordinary skill for the
`
`’589 Patent, I have considered the state of the art of semiconductor memory devices
`
`at that time, the types of problems encountered with power-on and initialization of
`
`such devices, and the solutions that then existed. I have also considered the then-
`
`existing technology for semiconductor memory devices and computer memory
`
`systems, including the sophistication of the technology involved. I have also
`
`considered the education and experience of those working in the field at that time. I
`
`have also considered my personal knowledge and experience in the field at that time,
`
`including those I worked and interacted with regarding semiconductor memory
`
`devices and computer memory systems. I have also considered the knowledge,
`
`education, and experience of those in academia and industry at that time that were
`
`working, innovating, or performing research in the field of semiconductor memory
`
`devices and computer memory systems.
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`33.
`
`It is my opinion that a POSITA for the ’589 Patent at the time of this
`
`filing date would have had a Bachelor’s degree in Electrical Engineering or
`
`Computer Science and two years of experience working in the field of system design
`
`using semiconductor memories, or a person with equivalent education, work, or
`
`experience in this field. More education could substitute for experience, and vice
`
`versa.
`
`34. Based on my background and qualifications, I was as of the priority
`
`date of the ’589 Patent someone who had more than the level of experience of a
`
`POSITA in the subject matter of the ’589 Patent. When developing the opinions set
`
`forth in this declaration, I assumed the perspective of a POSITA.
`
`VI.
`
`’589 Patent
`A. Overview
`
`35. The ’589 Patent is directed to a Dynamic Semiconductor Random
`
`Access Memory (“DRAM”) device and a method for initializing a DRAM device.
`
`EX1001 at 2:7-14. The device and method purportedly solve a problem in the prior
`
`art by providing a way for circuits to be “reliably held in a desired defined state”
`
`while the device is powering on. Id. at 1:22-35. This purported advancement is
`
`achieved by detecting a particular initialization sequence. Id. To detect the
`
`initialization sequence, the device contains an initialization circuit having a control
`
`circuit and an enable circuit. Id. at 2:15-36.
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`36. As seen in FIG. 1 of the ’589 Patent (reproduced below for reference),
`
`once the initialization circuit performs a switching-on operation and the internal
`
`voltage regulation and detection circuit 5 detects that the supply voltage at input 6 is
`
`stabilized, detection circuit 5 supplies a supply voltage stable signal (POWERON)
`
`to the enable circuit 9. Id. at 3:42-4:23.
`
`
`
`EX1001 (’589 Patent) at FIG. 1
`The enable circuit 9 receives the supply voltage stable signal (POWERON) at input
`
`11 and various command signals at input 10. Id. Once the enable circuit receives the
`
`supply voltage stable (POWERON) signal and the various command signals in a
`
`specific sequence, it outputs an enable signal (CHIPREADY) at output 12 which
`
`then unlatches the control circuit 13. Id.
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`37. FIG. 2 of the ’589 Patent (reproduced below for reference), illustrates
`
`an example of enable circuit 9 in more detail.
`
`
`
`EX1001 (’589 Patent) at FIG. 2
`It contains “three bistable multivibrator stages 14, 15 and 16 each having a set input
`
`S, a reset input R, and also an output Q.” Id. at 4:24-58. The supply voltage stable
`
`signal (POWERON), described above, is applied to the enable circuit at input 11. Id.
`
`Additionally, the command signals described above at input 10 are shown in more
`
`detail. Id. Input 10A receives a preparation command for word line activation, called
`
`PRE or PRECHARGE. Id. Input 10B receives a refresh command, called ARF or
`
`AUTOREFRESH. Id. Input 10C receives a loading configuration register command,
`
`called MRS or MODE-REGISTER-SET. Id. The enable signal (CHIPREADY) is
`
`output at output 12 after “a predetermined chronological initialization sequence of
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`the command signals PRE, ARF and MRS and activation of the [supply voltage
`
`steady] POWERON signal.” Id.
`
`B.
`
`38.
`
`Background / Applicant Admitted Prior Art
`
`I have reviewed the ’589 Patent, including the section of the
`
`Specification titled “BACKGROUND OF THE INVENTION.” I understand this
`
`section of the ’589 Patent to disclose technologies that were already known in the
`
`art as of the priority date of the ’589 Patent. In particular, I note that many of the
`
`elements that are recited in the ’589 Patent claims are described and/or rendered
`
`obvious in this Background section. For example:
`
`Claim Claim Language
`[1.P] A dynamic semiconductor
`memory device of a random
`access type
`
`See also, claim [11.P]
`
`[1.1]
`
`an initialization circuit
`controlling a switching-on
`operation and supplying a
`supply voltage stable signal
`once a supply voltage has
`
`Background
`“In the case of SDRAM semiconductor
`memories according to the JEDEC
`standard, it is necessary to ensure
`during the switch-on operation
`(“POWERUP”) that the internal control
`circuits provided for the proper
`operation of the semiconductor
`memory device are reliably held in a
`defined desired state” EX1001 at 1:22-
`27.
`
`“In the case of the SDRAM
`semiconductor memory modules that
`have been disclosed to date…”
`EX1001 at 1:65-66.
`“In the case of the SDRAM
`semiconductor memory modules that
`have been disclosed to date, all the
`control circuits of the component have
`been unlatched only with the
`POWERON signal. The signal
`
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`
`
`Claim Claim Language
`been stabilized after the
`switching-on operation
`
`See also, claim [11.1]
`
`[1.2]
`
`said initialization circuit
`having a control circuit for
`controlling operations and an
`enable circuit receiving the
`supply voltage stable signal
`and externally applied further
`command signals
`
`See also, claim [11.2]
`
`Background
`POWERON is active if the internal
`Supply Voltages have reached the
`necessary values that are necessary for
`the proper operation of the component.
`The module is then in a position to
`recognize and execute instructions.”
`EX1001 at 1:65-2:5.
`“According to the JEDEC standard for
`SDRAM semiconductor memories, a
`recommended initialization sequence
`(so-called “POWERON-SEQUENCE”)
`is provided as follows:
`a. the application of a supply voltage
`and a start pulse in order to maintain an
`NOP condition at the inputs of the
`component;
`b. the maintenance of a stable supply
`voltage of a stable clock signal, and of
`stable NOP input conditions for a
`minimum time period of 200 us;
`c. the preparation command for word
`line activation (PRECHARGE) for all
`the memory banks of the device;
`4. the activation of eight or more
`refresh commands (AUTOREFRESH);
`and
`5. the activation of a loading
`configuration register command
`(MODE-REGISTER-SET) for
`initializing the mode register.” EX1001
`at 1:43-61.
`
`“In the case of the SDRAM
`semiconductor memory modules that
`have been disclosed to date, all the
`control circuits of the component have
`been unlatched only with the
`POWERON signal.” EX1001 at 1:65-
`2:1.
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`
`Claim Claim Language
`[1.3]
`said enable circuit outputting
`an enable signal after a
`predetermined proper
`initialization sequence of the
`externally applied further
`command signals being
`identified and the enable
`signal effecting an unlatching
`of said control circuit
`
`See also, claim [11.3]
`
`Background
`“According to the JEDEC standard for
`SDRAM semiconductor memories, a
`recommended initialization sequence
`(so-called “POWERON-SEQUENCE”)
`is provided as follows:
`a. the application of a supply voltage
`and a start pulse in order to maintain an
`NOP condition at the inputs of the
`component;
`b. the maintenance of a stable supply
`voltage of a stable clock signal, and of
`stable NOP input conditions for a
`minimum time period of 200 us;
`c. the preparation command for word
`line activation (PRECHARGE) for all
`the memory banks of the device;
`4. the activation of eight or more
`refresh commands (AUTOREFRESH);
`and
`5. the activation of a loading
`configuration register command
`(MODE-REGISTER-SET) for
`initializing the mode register.” EX1001
`at 1:43-61.
`
`“In the case of the SDRAM
`semiconductor memory modules that
`have been disclosed to date, all the
`control circuits of the component have
`been unlatched only with the
`POWERON signal. The signal
`POWERON is active if the internal
`supply voltages have reached the
`necessary values that are necessary for
`the proper operation of the component.
`The module is then in a position to
`recognize and execute instructions.”
`EX1001 at 1:65-2:5.
`
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`Claim Claim Language
`[2]
`The semiconductor memory
`device according to claim 1,
`wherein the externally applied
`further command signals
`forming the predetermined
`proper initialization sequence
`to be identified by said enable
`circuit includes at least one of
`a preparation command signal
`for word line activation, a
`refresh command signal, and a
`loading configuration register
`command signal.
`
`See also, claim [12]
`The semiconductor memory
`device according to claim 1,
`wherein the identification of
`an initialization sequence that
`is identified as the
`predetermined proper
`initialization sequence by said
`enable circuit and generates
`the enable signal constitutes a
`command sequence
`conforming to a JEDEC
`standard.
`
`[8]
`
`[9]
`
`The semiconductor memory
`device according to claim 1,
`wherein said control circuit
`has output drivers remaining
`latched during the switching-
`on operation until said enable
`signal is generated by said
`enable circuit.
`
`Background
`“[A] recommended initialization
`sequence (so-called “POWERON-
`SEQUENCE”) is provided as follows:
`…c. the preparation command for word
`line activation (PRECHARGE) for all
`the memory banks of the device;
`4. the activation of eight or more
`refresh commands (AUTOREFRESH);
`and
`5. the activation of a loading
`configuration register command
`(MODE-REGISTER-SET) for
`initializing the mode register.” EX1001
`at 1:44-61.
`
`“In the case of SDRAM semiconductor
`memories according to the JEDEC
`standard, it is necessary to ensure
`during the switch-on operation
`(“POWERUP”) that the internal control
`circuits provided for the proper
`operation of the semiconductor
`memory device are reliably held in a
`defined desired state.” EX1001 at 1:22-
`27.
`
`“According to the JEDEC standard for
`SDRAM semiconductor memories, a
`recommended initialization sequence
`(so-called “POWERON-SEQUENCE”)
`is provided.” EX1001 at 1:43-46.
`“In the case of the SDRAM
`semiconductor memory modules that
`have been disclosed to date, all the
`control circuits of the component have
`been unlatched only with the
`POWERON signal. The signal
`POWERON is active if the internal
`supply voltages have reached the
`
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`
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`
`
`Claim Claim Language
`
`See also, claim [13]
`
`[10]
`
`The semiconductor memory
`device according to claim 1,
`wherein the predetermined
`proper initialization sequence
`