`
`
`
`LOALi,1@WHOMTHESE; PRESENTS: SHALL, COME?
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`
`Y
`
`March8, 2022
`
`THIS IS TO CERTIFY THAT ANNEXED IS A TRUE COPY FROMTHE
`
`RECORDS OF THIS OFFICE OF THE FILE WRAPPER AND CONTENTS
`
`APPLICATION NUMBER:69/343,431
`
`FILING DATE: June 30, 1999
`
`PATENT NUMBER: 6,157,589
`
`ISSUE DATE: December 5, 2000
`
`By Authority of the
`UnderSecretary of Commerce for Intellectual Property
`and Director of the United States Patent and Trademark Office
`
`
`Certifying Officer
`
`
`
`
`
`
`
`
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`XILINX EXHIBIT 1002
`Page 1
`
`XILINX EXHIBIT 1002
`Page 1
`
`

`

`.Subclass‘
`
`
`
`ISSUECLASSIFICATION
`
`:
`
`6157589
`
`SECTOR
`
`|CLASS
`
`|SUBCLASS
`
`iOBed
`EXAMINER
`FILEDWITH:oDISK(CRF)aFICHE
`
`« (Attachedin pocketolon:Light inside.fap):
`
`(FACE)
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`Form PTO-436A
`
`TERMINAL
`
`DISCLAIMER
`
`oO a) The term of this patent
`subsequentto
`has beendisclaimed.
`
`(date)
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`(] b) Theterm of this patent shall
`hot extend beyond the expiration date
`of U.S Patent. No.
`
`;
`
`
`(Assistant Exarningr
`
`:
`
`.
`Group cée~
`ALU 2ELE
`
`WA. Le
`EanhaAMiner
`
`Date Paid
`
`months of
`£1] c) The terminal
`this patent have been disclaimed.
`
`
`{Legal Instruments Examiner}
`
`™_
`
`ISSUE FEE IN FILE
`
`(LABEL AREA)
`.
`
`Formal Drawings(
`
`nersek
`
`shisjsel_—
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`XILINX EXHIBIT 1002
`Page 2
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`XILINX EXHIBIT 1002
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`

`

`
`
` SERIAL NUMBER FILING DATE
`GROUP ART UNIT
`ATTORNEY DOCKET NO.
`
`2818
`
`
`09/343,431 GR98P1989
`06/30/99
`
`GUNNAR KRAUSE, MUENCHEN, FED REP GERMANY.
`
`*KECONTINUING DOMESTIC DATAREEERKRERARK AHR ERE
`VERIFIED
`
`om
`
`rence
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`APPLICANT
`
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`
`
`
`
`**371 (NAT’L STAGE) DATARS ER KERR RRR KERR A RRR
`VERIFIED
`
`oO»
`Neve
`
`
`et
`
`
`
`**FOREIGN APPLICATIONS *# ****### 4 *%%
`VERIFIED
`FED REP GERMANY
`
`198 29 287.2
`
`.
`06/30/98
`
`
`
`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED 07/26/99
`
`
`Foreign Priority
`claimed
`STATE OR
`SHEETS,
`INDEPENDENT
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`35U c 119te.a) conditions met BioEe ClMetafterAllowance|COUNTRY DRAWING CLAIMS
`
`
`
`
`
`
`DEX 2 3
`
`Verified and Acknowledged
`
`
`
` LERNER AND GREENBERG PA
`ADDRESS
`' PO BOX 2480
`HOLLYWOOD FL 33022-2480
`
`
` pynd|Mic SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR IN'TIALTZING A
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE
`
`
`
`
`
`
`RECEIVED
`FEES: Authority has been given in Paper
`: ‘llFees (Fiting)
`FILING FEE
`206
`
`
`
`
`[1 1.17 Fees (Processing Ext. of time)
`No._ to charge/credit DEPOSIT ACCOUNT
`
`
`| 1.48 Fees (Issue)
`$890
`NO. ss—S—CCC_sfor the following:
`
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`[] Credit
`
`
`
`
`XILINX EXHIBIT 1002
`Page 3
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`XILINX EXHIBIT 1002
`Page 3
`
`

`

`
`
`ATTORNEY DOCKET NO.
`
`
`
`
`GROUP ART UNIT
`FILING DATE
`2818
`GRIBP1989
`06/30/99
`
`
`
`
`z GUNNAR KRAUSE, MUENCHEN, FED REP GERMANY.
`o1
`
`SERIAL NUMBER
`09/343,431
`
`QQ
`
`.<
`
`**KCONTINUING DOMESTIC DATAFRR RR AR Rak
`VERIFIED
`
`**371 (NAT'L STAGE) DATA* ¥ 2% 3k eR ee ee
`VERIFIED
`
`**POREIGN APPLICATIONS * ** ##% # eRe
`VERIFIED
`FED REP GERMANY
`
`198 29 287.2
`
`06/30/98
`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED 07/26/99
`
`
`
`
`
`INDEPENDENT
`TOTAL
`STATE OR -|
`SHEETS
`Foreign Priority claimed
`Clyes Lino
`/
`
`35 USC 119 {a-d) conditions met [lyes [jno L1Met after Allowance|COUNTRY DRAWING CLAIMS CLAIMS
`
`
`
`
`
`
`2
`DEX
`3
`13
`Verified and Acknowledged
`
`LERNER AND GREENBERG PA
`PO BOK 2480
`HOLLYWOOD FL 33022-2480
`
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INTIALIZING A
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE
`.
`
`&
`&
`Qo
`<
`
`up
`~
`-
`
`FILING FEE
`
`RECEIVED
`$890
`
`:
`
`FEES: Authority has been given in Paper
`No. _—__—_s to charge/credit DEPOSIT ACCOUNT
`NO.
`____for the following:
`
`[-] Credit
`
`by Aetoes (Filing)
`[| 1.17 Fees (Processing Ext. of time)
`|] 1.18 Fees (Issue)
`[-] Other
`
`XILINX EXHIBIT 1002
`Page 4
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`Page 4
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`

`

`|
`
`/oe/90vii
`OldMT
`
`
`
`s
`LERNER AND GREENBERG,P.A.
`
`PATENT ATTORNEYS AND ATTORNEYS AT LAW
`2200 Hollywood Boulevard
`Hollywood, Florida 33020
`Tel: (954) 925-1100
`Fax: (954) 925-1101
`
`e-mail:
`patents@patentusa.com
`
`Mailing Address:
`Post Office Box 2480
`Hollywood, FL 33022-2480
`
`Herbert L. Lerner avy Bar)
`Laurence A. Greenberg (FL Bar)
`-___o
`Wemer EL Stemer (eg. Pat. Agent)
`Ralph E. Locher GL,IL,MOBars)
`. Manfred Beck (Gernan Pat. Agent only)
`Mark P. Weichselbaum (TN Bar)
`Gregory L. Mayback (FL Bar)
`Otto S. Kauder (Reg. Pat. Agent)
`Adam A. Jorgensen (Reg. Pat. Agent)
`
`
`e =———
`==
`as =o
`aS Sc
`—
`be =
`G =O
`nn =
`NewYork Office
`153 E 57th Street
`Suite 15G
`NIew York, NY 10022
`
`"Express Mail" mailing label number ELO80659885US
`Date of Deposit June 30, 1999
`
`| hereby certify that this paperor fee is being deposited with the United States Postal Service
`“Express Mail Post Office to Addressee" service under 37 CFR 1.10 on the date indicated above and
`is addressed to the Assistant Commissionerfor Patents, Washington, D.C. 20231.
`
`XIOMARA D. JUNCO
`
`Docket No.: GR 98 P 1989
`
`Date: June 30, 1999
`
`ALIXaa nme sea -
`
`Hon. Commissioner of Patents and Trademarks
`Washington, D.C. 20231
`
`Sir:
`
`Enclosed herewith are the necessary papersforfiling the following application for
`Letters Patent:
`
`Applicant
`
`GUNNAR KRAUSE
`
`Title
`
`DYNAMIC SEMICONDUCTOR MEMORYDEVICE AND
`METHOD FOR INITIALIZING A DYNAMIC SEMICONDUCTOR
`MEMORYDEVICE
`
`3 sheets of formal drawings in triplicate.
`A checkin the amount of $760.00 covering thefiling fee.
`Information Disclosure Statement and 1 Reference.
`
`This application is being filed without a signed oath or declaration underthe provisions of 37
`CFR 1.53(d). Applicants await notification of the date by which the oath or declaration and
`the surcharge are due, pursuantto this rule.
`
`The Patent and Trademark Office is hereby given authority to charge Deposit Account No.
`12-1099 of Lerner and Greeriberg, P.A. for any fees due or deficiencies of payments made
`for any purpose during the pendency of the above-identified application.
`
`
`
`LAURENCE A. GREENSEpe
`REG.NO.29398
`
`XILINX EXHIBIT 1002
`Page 5
`
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`Page 5
`
`

`

`PATENT APPLICATION SERIAL NO.
`
`U.S. DEPARTMENT OF COMMERCE
`_ PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`O7/1/1999 RUBRLING GOM0G2E 09943431
`
`Ol Flsi1
`
`0.8
`
`PTO-1556
`(5/87)
`*U.S. GPO: 1998-433-214/80404
`
`XILINX EXHIBIT 1002
`Page 6
`
`XILINX EXHIBIT 1002
`Page 6
`
`

`

`“GR 98 P 1989
`
`09/ 34343
`AbstractoftheDisclosure:
`A dynamic semiconductor memory device of a random access type has
`an initialization circuit that controls the switching-on operation
`
`of the semiconductor memory device and of its circuit components.
`
`5
`
`The initialization circuit supplies a supply voltage stable signal
`
`once the supply voltage has been stabilized after the switching-on
`
`of the semiconductor memory device.
`
`The initialization circuit
`
`has an enable circuit that receives the supply voltage stable
`
`Signal and further command signals externally applied to the
`
`semiconductor memory device.
`
`The enable circuit supplies an
`
`enable signal after a predetermined proper initialization sequence
`
`Baregt
`
`10
`
`15
`
`
`
`
`. control circuit provided for the proper operation of the
`
`
`
`of the command signals applied to the semiconductor memory device
`
`is identified.
`
`The enable signal effects the unlatching of a
`
`semiconductor memory device.
`
`aREL/cgm
`
`-18-
`
`XILINX EXHIBIT 1002
`Page 7
`
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`Page 7
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`

`

`GR 98 P 1989
`
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INITIALIZING A
`
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE
`—
`
`Background of the Invention:
`
`Field of the Invention:
`
`The invention relates to a dynamic semiconductor memory device of
`
`the random access type (DRAM/SDRAM) having an initialization
`
`circuit which controls a switching-on operation of the
`
`semiconductor memory device and of its circuit components.
`
`The
`
`initialization circuit supplies a supply voltage Stable signal
`(POWERON) once a supply voltage has been stabilized after the
`
`switching-on of the semiconductor memory device.
`
`The invention
`
`also relates to a method for initializing such a dynamic
`
`semiconductor memory device, and also to the use of an enable
`circuit,
`that supplies an enable signal, for controlling the
`
`switching-on operation of the dynamic semiconductor memory device.
`
`10
`
`
`
`20
`
`In the case of SDRAM’ semiconductor memories according to the JEDEC
`standard, it is necessary to ensure ‘during the switch-on operation
`
`("POWEBRUP")
`
`that the internal control circuits provided for the
`
`proper operation of the semiconductor memory device are reliably
`held in a defined desired state,
`in order to prevent undesirable
`
`25
`
`activation of output transistors that would cause, on the data
`
`lines, a short circuit (so-called "bus contention" or "data
`
`XILINX EXHIBIT 1002
`Page 8
`
`XILINX EXHIBIT 1002
`Page 8
`
`

`

`SR 98 P 1989
`
`contention") or uncontrolled activation of internal current loads.
`
`The solution to the problem turns out to be difficult on account
`
`of a fundamental unpredictability of the time characteristic of
`
`the supply voltage and of the voltage level or levels at the
`
`external control inputs during the switch-on operation of the
`
`semiconductor memory. According to the specifications of the
`
`manufacturer an SDRAM component should ignore all commands which
`
`‘are present chronologically before a defined initialization
`
`sequence.
`
`The sequence consists of predetermined commands that
`
`must be applied in a defined chronological order. However, a
`
`series of functions and commands which are allowed during proper
`
`operation of the component are desired or allowed chronologically
`
`only after the initialization sequence. According to the JgEDEC
`
`standard for SDRAM semiconductor memories, a recommended
`
`initialization sequence (so-called "POWERON-SEQUENCE")
`
`is provided
`
`as follows:
`
`a.
`
`the application of a supply voltage and a. start pulse in order
`
`to maintain an NOP condition at the inputs of the component;
`
`b.
`
`the maintenance of a stable supply voltage of a stable clock
`
`signal, and of stable NOP input conditions for a minimum time
`
`period of 200 us;
`
`
`
`20
`
`25
`
`c.
`
`the preparation command fer word line activation (PRECHARGE)
`
`f6E.alt the memory banks of the device;
`
`XILINX EXHIBIT 1002
`Page 9
`
`XILINX EXHIBIT 1002
`Page 9
`
`

`

`
`
`CR 98 P 1989
`
`4.
`
`the activation of eight or more refresh commands
`
`(AUTOREFRESH) ;
`
`and
`
`5.
`
`the activation of a loading configuration register command
`
`(MODE-REGISTER-SET) for initializing the mode register.
`
`After the identification of such a defined initialization
`
`sequence,
`
`the memory module is normally in a so-called IDLE state,
`
`that is to say it is precharged and prepared for proper operation.
`
`In the case of the SDRAM semiconductor memory modules that have
`
`been disclosed to date, all the control circuits of the component
`
`have been unlatched only with the POWERON signal.
`The signal
`POWERON is active if the internal supply voltages have reached the
`
`necessary values that are necessary for the proper operation of
`
`the component.
`
`The module is then in a position to recognize and
`
`7execute instructions.
`
`
`
`Summary of the invention:
`
`20
`
`It is accordingly an object of the invention to provide a dynamic
`
`semiconductor memory device and a method for initializing a
`
`dynamic semiconductor memory device which overcome the above-
`mentioned disadvantages of the priorart methods and devices of
`
`this general type, which is as simple as possible in structural
`
`25
`
`terms and which effectively prevents the risk of a short circuit
`
`-3-
`
`!
`
`XILINX EXHIBIT 1002
`Page 10
`
`XILINX EXHIBIT 1002
`Page 10
`
`

`

`
`
`
`
`20
`
`Tasong
`
`JR 98 P 1989
`
`of the data lines and/or of uncontrolled activation of internal
`
`current loads.
`
`With the foregoing and other objects in view there is
`
`provided,
`
`in accordance with the invention, a dynamic
`
`semiconductor memory device of a random access type, containing an
`
`initialization circuit controlling a switching-on operation and
`
`supplying a supply voltage stable signal once a supply voltage has
`
`been stabilized after the switching-on operation.
`
`The
`
`initialization circuit has a control circuit for controlling
`
`operations and an enable circuit receiving the supply voltage
`
`stable signal and externally applied further command signals.
`
`The
`
`enable circuit outputting an enable signal after a predetermined
`
`proper initialization sequence of the externally applied further
`
`command signals are identified and the enable signal effecting an
`
`unlatching of the control circuit.
`
`The invention provides for the initialization circuit to have an
`enable circuit, which receives the supply voltage stable signal
`and the externally applied further command Signals.
`The enable
`circuit generates the enable signal after the identification of
`
`the predetermined proper initialization sequence of the command
`
`signals is achieved.
`
`The enable signal effects the unlatching of
`
`the control circuit provided for the proper operation of the
`
`25
`
`semiconductor memory device.
`
`-4-
`an
`rheanensanemnes
`
`XILINX EXHIBIT 1002
`Page 11
`
`XILINX EXHIBIT 1002
`Page 11
`
`

`

`
`
`3R 98 P 1989
`
`Following the principle of the invention,
`the enable signal
`(CHIPREADY) is generated and becomes active in dependence on
`further internal signals and the initialization sequence and then
`
`The predetermined circuits
`unlatches predetermined circuits.
`remain latched until the end of the predetermined initialization
`
`sequence.
`
`By way of example, commands are decoded but not
`
`executed and the output drivers are held at high impedance.
`
`According to the preferred application in SDRAM memory devices
`
`according to the JEDEC standard, it is provided that the command
`
`signals, externally applied to the semiconductor memory device, of
`the initialization sequence are to be identified by the enable
`
`circuit.
`
`The command signals include a preparation command signal
`
`for word line activation (PRECHARGE), and/or.a refresh command
`signal
`(AUTOREFRESH), and/or a loading configuration register
`
`command signal
`
`(MODE~REGISTER-SET) .
`
`
`
`According to an advantageous structural refinement of the
`initialization circuit according to the invention, it is provided
`
`20
`
`that the enable circuit has at least one bistable multivibrator
`stage with a set input which receives the command signal
`
`(PRECHARGE, AUTOREFRESH, MODE-REGISTER-SET).
`
`The bistable
`
`multivibrator also has a reset input to which the supply voltage
`stable signal
`(POWERON), a signal derived therefrom, or a linked
`signal is applied.
`The bistable multivibrator further has an
`
`25
`
`output at which the enable signal
`
`(CHIPREADY)
`
`is outputted.
`
`XILINX EXHIBIT 1002
`Page 12
`
`XILINX EXHIBIT 1002
`Page 12
`
`

`

`
`
`
`
`“GR 98 P 1989
`
`In particular,
`
`the enable circuit has a plurality of bistable
`
`multivibrator stages respectively receiving the command signals.
`
`In an expedient refinement of the invention, it is provided that
`
`the output of at least one of the bistable multivibrator stages is
`
`passed to a reset input of a further multivibrator stage.
`
`In this
`
`case, it may furthermore be provided that,
`
`in one of the bistable
`
`multivibrator stages,
`
`the supply voltage stable signal
`
`(POWERON)
`
`and the signal output from the output of the further multivibrator
`
`stage are passed, after having been logically combined by a gate,
`
`to the reset input of the multivibrator stage.
`
`Other features which are considered as characteristic for the
`
`invention are set forth in the appended claims.
`
`Although the invention is illustrated and described herein as
`
`embodied in a dynamic semiconductor memory device and a method for
`
`20
`
`initializing a dynamic semiconductor memory device, it is
`
`nevertheless not
`intended to be limited to the details shown,
`since various modifications and structural changes may be made
`
`therein without departing from the spirit of the invention and
`
`within the scope and range of equivalents of the claims.
`
`25
`
`The construction and method of operation of the invention,
`
`however,
`
`together with additional objects and advantages thereof
`
`XILINX EXHIBIT 1002
`Page 13
`
`XILINX EXHIBIT 1002
`Page 13
`
`

`

`
`
`
`
`~—@R 98 P 1989
`
`will be best understood from the following description of specific
`
`embodiments when read in connection with the accompanying
`
`drawings.
`
`Brief Description of the Drawings:
`
`Fig. 1 is a diagrammatic, block diagram of components of an
`
`initialization circuit which controls a switching-on operation of
`
`a semiconductor memory and its circuit components according to the
`
`invention;
`
`Fig.
`
`2 is. circuit diagram of an enable circuit that supplies an
`
`enable signal
`
`(CHIPREADY) ;
`
`Fig.
`
`3 is a time sequence diagram for elucidating a method of
`
`operation of the circuit according to Fig. 2; and
`
`Fig. 4 is a circuit diagram of the enable circuit according to an
`
`exemplary embodiment of the invention.
`
`20
`
`Description of the Preferred Embodiments:
`In all the figures of the drawing, gub-featuresand integral parts
`
`that correspond to one another bear the same reference symbol in
`
`each case. Referring now to the figures of the drawing in detail
`
`and first, particularly,
`to Fig.
`1 thereof,
`there are shown
`circuit components,
`important for understanding the invention, of
`
`25
`
`an SDRAM memory device operating according to the JEDEC standard.
`
`
`
`XILINX EXHIBIT 1002
`Page 14
`
`XILINX EXHIBIT 1002
`Page 14
`
`

`

`
`
`GR 98 P 1989
`
`The circuit components include an initialization circuit
`
`controlling a switching-on operation of the SDRAM memory device
`
`and its circuit components.
`
`The initialization circuit has an
`
`input circuit 1,
`
`to whose input 2 command and clock signals that
`
`5
`
`are externally applied in reference to the semiconductor memory
`
`are provided.
`
`The command and clock signals are amplified and
`
`conditioned before being received by a command decoder 3 connected
`
`downstream of the input circuit 1 and at whose output 4,
`
`inter
`
`alia,
`
`the command signals PRE or PRECHARGE (preparation command
`
`. for word line activation), ARF or AUTOREFRESH (refresh command)
`
`and MRS or MODE-REGISTER-SET (loading configuration register
`
`command) are output.
`
`The initialization circuit further has a
`
`circuit 5 for internal voltage regulation and/or detection, at
`
`
`
`whose input 6 the external supply voltages that are externally
`
`
` second output
`
`applied to the semiconductor memory externally are fed in.
`
`The
`
`circuit 5 has a first output 7 outputting a POWERON signal and a
`
`8 supplying stabilized internal supply voltages.
`
`The method of operation and the structure of the circuits 1,
`5 are sufficiently known to the person skilled in the art and
`therefore do not need to be explained in any more detail. What is
`
`3 and
`
`20
`
`important for understanding the invention is the fact that the
`circuit 5 supplies an active POWERON signal if, after the POWERUP
`phase of the SDRAM memory,
`the internal supply voltages present at
`the output
`8 have reached the values necessary for proper
`
`25
`
`operation of the component.
`
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`~~GR 98 P 1989
`
`According to the invention,
`
`the initialization circuit furthermore
`
`has an enable circuit 9 connected downstream of the circuits 3 and
`
`5.
`
`The command signals PRE, ARF and MRS are applied to an input
`
`10 of the enable circuit 9 and the POWERON signal is applied to an
`
`input 11 of the enable circuit 9.
`
`An enable signal CHIPREADY is
`
`supplied at an output 12 of the enable circuit 9 after the
`
`identification of a predetermined proper initialization sequence
`of the command signals applied to the semiconductor memory device
`
`is achieved.
`
`The enable signal effects unlatching of control
`
`circuits 13 provided for proper operation of the semiconductor
`
`memory device.
`
`The internal control circuits 13 serve inter alia
`
`for sequence control for one or more of the memory blocks of the
`
`SDRAM memory and are known as such.
`
`2 shows a preferred exemplary embodiment of the enable
`Fig.
`circuit 9 according to the invention.
`The enable circuit 9
`
`contains three bistable multivibrator stages 14, 15 and 16 each
`
`having a set input S, a reset input R, and also an output Q. An
`
`AND gate 17 connected upstream of the reset input R of the
`
`20
`
`multivibrator stage 15 and an AND gate 18 connected downstream of
`all the outputs Q of the multivibrator «stages 14, 15, 16 are
`
`further provided.
`
`The enable circuit further has an inverter 19
`
`connected downstream of the AND gate 18.
`
`The enable signal
`
`CHIPREADY being output at the output 12 of the inverter 19 and the
`
`25
`
`enable signal CHIPREADY is active HIGH,
`
`that is to say activated
`
`when its voltage level is at logic HIGH.
`
`The command Signals PRE,
`
`
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`“GR 98 P 1989
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`ARF, MRS applied to the respective set inputs S of the bistable
`
`multivibrator stages 14, 15, 16 are each active LOW,
`that is to
`say these signals are active when their voltage level is at logic
`
`LOW, while the POWERON signal is again active HIGH.
`
`The POWERON
`
`5
`
`Signal is applied directly to the reset inputs R in the case of
`the multivibrator stages 14 and 16 and is firstly applied to one
`
`input of the AND gate 17 in the case of the multivibrator stage
`
`15,
`
`the signal output from the output Q of the multivibrator stage
`
`14 is applied to the other input of the AND gate 17,
`
`the output of
`
`the AND gate 17 is connected to the reset input of the
`
`10
`
`/multivibrator stage 15.
`
`, The method of operation of the enable circuit 9 illustrated in
`
`
`
`Fig.
`
`2 is such that activation of the enable signal CHIPREADY at
`
`the output 12 to logic HIGH is generated only when a predetermined
`
`chronological initialization sequence of the command signals PRE,
`
`
`
`
`S ARF and MRS and activation of the POWERON signal to the logic
`
`level HIGH are detected. Only then are the control circuits 13
`
`unlatched on account of the activation of the enable signal
`
`20
`
`CHIPREADY;
`
`the control circuits 13 remaining latched prior to
`
`this.
`
`
`
`In the schematic time sequence diagram according to Fig. 3,
`
`exemplary command sequences during the switching-on operation of
`
`25
`
`the semiconductor memory device are illustrated in order to
`
`elucidate the method of operation of the enable circuit 9.
`
`-1LO-
`
`q4
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`/
`?
`ii
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`--GR 98 P 1989
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`In the case situation A,
`
`the signal PRECHARGE is activated to
`
`active LOW too early relative to the activation of the POWERON
`
`signal, with the result that,
`the enable signal CHIPREADY is not
`yet activated to logic HIGH since the proper initialization
`
`:
`
`5
`
`‘sequence requires a waiting time before the first command.
`
`The
`
`signal swing of the command PRECHARGE according to case situation
`
`A is thus correctly ignored.
`
`In case situation B,
`
`the
`
`chronological order of the activation of the signal AUTOREFRESH to
`
`10
`
`logic LOW is incorrect since the proper initialization sequence
`
`‘ prescribes a previous PRECHARGE command before the AUTOREFRESH
`
`' command.
`The signal swing of the AUTOREFRESH signal to logic LOW
`
`according to case situation B is therefore likewise ignored, and
`
`“the enable signal does not go to logic HIGH.
`
`In case situation ¢C,
`
`
`
`a correct chronological order of the commands PRECHARGE,
`
`AUTOREFRESH, MODE-REGISTER-SET is present conforming to the JEDEC
`
` ia Standard,
`in a logically consistent manner, since the POWERON
`signal is also at logic HIGH, an enable signal’ CHIPREADY at logic
`
`Illustrated using dashed lines, another
`HIGH is now supplied.
`further conceivable initialization sequence that is allowed and
`
`20
`
`therefore triggers an enable signal is represented by the symbol
`
`D; activation of the command MODE-REGISTER-SET to logic LOW is
`
`allowed at any time after the activation of the POWERON signal.
`
`25
`
`Fig.
`
`4 shows further details of a preferred exemplary embodiment
`
`of the enable circuit 9 according to the invention.
`
`[In this
`
`
`
`-11L-
`
`/ AE
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`~aR 98 P 1989
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`exemplary embodiment, each of the bistable multivibrators 14, 15,
`
`16 is constructed from in each case two NAND gates 14A, 14B, 15A,
`
`17, 16A, 16B and also an inverter 14C, 15C and 16C, which are
`
`connected to one another in the manner illustrated.
`
`The NAND gate
`
`17 is provided with three inputs in the bistable multivibrator 15.
`
`-12-
`
`—
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`XILINX EXHIBIT 1002
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`and supplyingasupply voltagestable signal once a supply voltage
`
`
`
`
`“uwR 98 P 1989
`
`IClaim:
`
`1.
`
`A dynamic semiconductor memory device of a random access
`
`type, comprising:
`
`an initialization circuit controlling a switching-on operation
`
`has been stabilized after the switching-on operation, said
`initialization circuit having a control circuit for controlling
`
`operations and an enable circuit receiving the supply voltage
`Power oA
`Pre MSTae
`stable signal and externally applied further command signals, said
`enable circuit outputting an enable signal after a predetermined—
`proper initialization sequence of the externally applied further
`command signals being identified and the enablé Signal effecting
`
`an unlatching of said control circuit.
`
`2.
`
`The semiconductor memory device according to claim 1,
`
`wherein the externally applied further command signalsForming the
`
`predetermined proper initialization sequence to be identified by
`
`Said enable circuit includes at least one of a preparation command
`Dre.
`Signal for word line activation, a refresh command signal, and a
`
`loading configuration register command signal.
`
`3.
`
`The semiconductor memory device according to claim 1, wherein
`at
`
`Said enable circuit has at least one bistable multivibrator stage
`
`having a set input receiving the externally applied further
`
`command signals, a reset input receiving one of the supply voltage
`peecet
`
`
`
`-13-.-
`/ fj
`CLA
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`

`IR 98 P 1989
`
`stable signal, a signal derived from the supply voltage stable
`signal and a linked signal, and an output outputting said-enable
`a 5
`-
`
`signal.
`
`4.
`
`The semiconductor memory device according to claim 3, wherein
`
`said at least one bistable multivibrator stage is a plUratity of -
`
`bistable multivibrator stages respectively receiving one of the
`
`externally applied further command signals.
`
`5.
`The semiconductor memory device according to claim 4, wherein
`said output of one of said plurality of bistable multivibrator
`
`stages is passed to said reset input of another of said plurality
`
`of bistable multivibrator stages.
`
`6.
`
`The semiconductor memory device according to claim 4,
`
`including an AND gate receiving the supply voltage stable signal
`+
`Se
`
`and a signal output from said output of one of said plurality of
`
`bistable multivibrator stages, said AND gate outputting an output
`
`signal received at said reset input of another of said plurality
`
`of bistable multivibrator stages.
`
`7.
`
`The semiconductor memory device according to claim 4, wherein
`
`a
`’
`'
`2
`s
`z
`said plurality of bistable multivibrator stages are each formed of
`
`an RS flip-flop constructed from one of at least two NOR and at
`
`least two NAND gates.
`
`
`
`
`
`
`XILINX EXHIBIT 1002
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`

`
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`
`
`
`~GR 98 P 1989
`
`The semiconductor memory device according to claim 1, wherein
`8.
`the identification of an initialization sequence that is
`identified as the predetermined proper initialization sequence by
`
`said enable circuit and generates the enable signal constitutes a
`
`command sequence conforming to a JEDEC standard.
`
`9.
`
`The semiconductor memory device according to claim 1, wherein
`
`said control circuit has output drivers remaining latched during
`—_—
`
`the switching-on operation until said enable signal is generated
`
`by said enable circuit.
`
`10.
`
`The semiconductor memory device according to claim 1,
`
`wherein the predetermined proper initialization sequencoe—includes
`
`one of the following chronologically successive command sequences:
`
`a) firstly PRE, secondly ARF,
`
`thirdly MRS;
`
`b) firstly PRE, secondly MRS,
`
`thirdly ARF; and
`
`c) firstly MRS, secondly PRE, or thirdly ARF;
`
`where,
`
`PRE
`
`the preparation command signal for word line
`
`activation,
`
`ARF = the refresh command signal, and
`
`MRS = the loading configuration register command signal.
`
`-15-
`
`.
`
`XILINX EXHIBIT 1002
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`
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`“GR 98 P 1989
`
`11. An improved method for initializing a dynamic semiconductor
`
`memory device of a random access type via an initialization
`
`circuit controlling a switching-on operation of the dynamic
`semiconductor memory device and of its circuit components,
`
`the
`
`improvement which comprises:
`
`supplying, via the initialization circuit, a supply voltage stable
`
`signal once a supply voltage has been stabilized after the
`
`switching-on operation of the dynamic semiconductor memory device;
`
`and
`
`supplying, via an enable circuit of the initialization circuit, an
`
`enable signal,
`
`the initialization circuit receiving the supply
`
`voitage stable signal and further command signals externally
`
`applied to the dynamic semiconductor memory device, after an
`
`identification of a predetermined proper initialization sequence
`
`of the further command signals the enable signal being generated
`
`and effecting an unlatching of a control circuit provided for a
`
`proper operation of the dynamic semiconductor memory device.
`
`12.
`
`The method according to claim 11, which comprises
`
`,
`~~
`providing at least one of a preparation command signal for word
`
`line activation, a refresh command signal, and a loading
`
`configuration register command signal as the further command
`
`signals.
`
`-16-
`
`2
`
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`

`13.
`
`The method according to claim 11, which comprises maintaining
`
`a latched condition of output drivers 6f the dynamic semiconductor
`
`GR 98 P 1989
`
`memory device during the switching-on operation until the enable
`
`signal is generated by the enable circuit.
`
`
`
`
`XILINX EXHIBIT 1002
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`
`
`Docket No.: GR 98 P 1989
`
`COMBINED DECLARATION AND POWER OF ATTORNEY
`IN ORIGINAL APPLICATION
`
`As a below namedinventor, | hereby declare that: my residence, post office address and
`citizenship are as stated below next to my name; that | verily believe that | am the original,
`first and sole inventor (if only one nameis listed below) or an original, first and joint
`inventor (if plural namesare listed below) of the subject matter which is claimed and for
`which a patent is sought on the invention entitled:
`
`DYNAMIC SEMICONDUCTOR MEMORYDEVICE AND METHOD FOR INITIALIZING A
`DYNAMIC SEMICONDUCTOR MEMORYDEVICE
`
`described and claimed in the specification bearing thattitle, that | understand the content
`of the specification, that | do not know and do not believe the same was ever known or
`used in the United States of America before my or our invention thereof, or patented or
`described in any printed publication in any country before my or our invention thereof or
`more than one yearprior to this application, that the same wasnot in public use or on sale
`in the United States of America more than one yearprior to this application, that the
`invention has not been patented or made the subject of.an inventor's certificate issued
`before the date of this application in any country foreign to the United States of America
`on an application filed by me or my legal representatives or assigns more than twelve
`: monthpriorto this application, that | acknowledge myduty to disclose information of which
`.
`| am aware whichis material to the examination of this application under 37 C.F.R. 1.56a,
`and that no application for patent or inventor's certificate of this invention has beenfiled
`earlier than the following in any country foreign to the United States prior to this
`application by me or mylegal representatives or assigns:
`German Application No. 198 29 287.2, filed June 30, 1998,théInfemational Priority of
`whichis claimed under 35 U.S.C. §119.
`oe
`/
`| hereby appoint the following attorney(s) and/or agent(s) to prosecute this application and
`to transact all business in the Patent and_TrademarkOffice connected therewith:
`HERBERT L. LERNER (Reg.No.20,435)
`LAURENCE A. GREENBERG(Reg.No.29,308)
`WERNERH. STEMER(Reg.No.34,956)
`RALPH E. LOCHER(Reg.No.41,947)
`
`a
`
`Address all corresp