Stephen W. Melvin, Ph.D. - November 21, 2023
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` U N I T E D S T A T E S P A T E N T A N D T R A D E M A R K O F F I C E
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` B E F O R E T H E P A T E N T T R I A L A N D A P P E A L B O A R D
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` X I L I N X , I N C . , )
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` I P R 2 0 2 3 - 0 0 5 1 6
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` P a t e n t N o . 6 , 1 5 7 , 5 8 9
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` D e p o s i t i o n o f
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` S T E P H E N W . M E L V I N , P h . D .
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` T u e s d a y , N o v e m b e r 2 1 , 2 0 2 3
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` R E P O R T E D B Y : J O H N W I S S E N B A C H , R D R , C R R , C S R 6 8 6 2
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`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
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`2 (Pages 2 to 5)
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`Page 4
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` THE VIDEOGRAPHER: We are now on the record
`for the video deposition of Dr. Stephen Melvin --
`the time is 8:33 a.m. November 21st, 2023 -- in the
`matter of Xilinx, Incorporated vs. Polaris
`Innovations Limited, IPR Number 2023-00516, being
`held in the United States Patent and Trademark
`Office before the Patent Trial and Appeal Board.
`The court reporter is John Wissenbach, the
`videographer is Gus Phillips, and both are
`representatives of GregoryEdwards LLC.
` Will counsel please state their appearances
`for the record, beginning with the petitioner.
` MR. KAPADIA: Yes. Aashish Kapadia, for
`petitioner, Xilinx, Incorporated.
` MR. DeZERN: And David DeZern, of Nelson
`Bumgardner Conroy, for the respondent, Polaris.
` THE VIDEOGRAPHER: Will the court reporter
`please administer the oath.
` STEPHEN W. MELVIN, Ph.D.,
`having been first duly sworn, testified as follows:
` EXAMINATION BY MR. DeZERN
` Q. All right. Good morning.
` A. Good morning.
` Q. Could you please state your name.
` A. Yes. Stephen Melvin.
`
`Page 5
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` Q. And Dr. Melvin, because this is a remote
`deposition and we aren't in the same room, do you
`have any materials, written or electronic, with you
`today?
` A. I don't.
` Q. Do you intend to open any materials during
`the course of this deposition?
` A. Only the PDFs that -- that you put in the
`chat box.
` Q. Okay. Well, I'd just ask you, if there's
`any materials you might want to open that you have
`accessible, please let me know, so that we can mark
`them and keep a clean record of this deposition. Is
`that okay?
` A. Okay. That's fine, yes.
` Q. And do you have access to any chat or
`messaging applications other than through this Zoom
`platform that we are using?
` A. Not at the moment, no.
` Q. Okay. Will you let me know if you receive
`any messages during this deposition?
` A. Yes.
` Q. And is there anyone else in the room with
`you?
` A. No.
`
`Page 2
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` INDEX OF EXAMINATIONS
` Page
`WITNESS:
`STEPHEN W. MELVIN, Ph.D.
` Examination by Mr. DeZern 4
`
` * * * *
`
` EXHIBITS REFERENCED
` Exhibit 1003 (Deposition Exhibit 1)
` Exhibit 1005 (Deposition Exhibit 2)
` Exhibit 1006 (Deposition Exhibit 3)
`
` * * * *
`
`Page 3
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` BE IT REMEMBERED that, pursuant to the laws
`governing the taking and use of depositions, on
`Tuesday, November 21, 2023, commencing at 8:33 a.m.,
`before me, JOHN WISSENBACH, CSR 6862, of San
`Francisco, California, appeared through
`videoconference STEPHEN W. MELVIN, Ph.D., at Delta,
`British Columba, Canada, called as a witness by the
`Patent Owner, who, being by me first duly sworn, was
`thereupon examined as a witness in said action.
` APPEARANCES OF COUNSEL VIA VIDEOCONFERENCE
`For the Petitioner:
` McDERMOTT WILL & EMERY LLP
` BY: AASHISH KAPADIA, Attorney at Law
` BRIAN W. OAKS, Attorney at Law
` 300 Colorado Street, Suite 2200
` Austin, Texas 78701
` (512) 298-6488 akapadia@mwe.com
` (512) 726-2574 boaks@mwe.com
`For the Patent Owner:
` NELSON BUMGARDNER CONROY PC
` BY: DAVID T. DeZERN, Attorney at Law
` 2727 N. Harwood Street, Suite 250
` Dallas, Texas 75201
` (214) 446-4958 david@nelbum.com
`ALSO PRESENT: GUS PHILLIPS, Videographer
`
` * * * *
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`GregoryEdwards, LLC | Worldwide Court Reporting
`GregoryEdwards.com | 844-483-2643
`
`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 6
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` Q. And will you please advise if anyone does
`enter?
` A. Yes, I will.
` Q. Okay. Dr. Melvin, you've been deposed
`before, right?
` A. Yes.
` Q. Approximately how many times?
` A. 20 -- 20 to 30 times, maybe.
` Q. Okay. So you know the drill. I'll ask
`questions. You're under oath to answer. Your
`counsel may object, but you still have to answer.
`Is that okay?
` A. Yes.
` Q. And if you need a break, please just let me
`know. We can do that. But I'd ask that you finish
`responding to any pending questions.
` A. Okay.
` Q. Any reason you can't testify truthfully to
`the best of your ability today?
` A. No.
` (Deposition Exhibit 1 was marked for
`identification.)
`BY MR. DeZERN:
` Q. All right. Now, I'm going to mark as
`Exhibit 1 -- which, as we discussed, I'm submitting
`
`Page 7
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`through the chat. And it will upload. And I'll
`give you a second. Please let me know when you've
`got that.
` A. Okay. I have it. Shall I open it?
` Q. Please.
` A. Okay. I see it.
` Q. And is this Exhibit 1 your declaration?
` A. Yes, it is.
` Q. And specifically, just looking at the top
`of it, this is a declaration you submitted in this
`IPR, which relates to -- actually, the patent
`number's not on the top, is it? -- the -- if you go
`to the second page, this is about your opinions
`regarding U.S. Patent Number 6,157,589, correct?
` A. That's correct.
` Q. And could we just refer to that as the '589
`patent this morning?
` A. Sure.
` Q. Dr. Melvin, was anyone else involved in
`creating this declaration?
` A. Well, I worked with the attorneys on it.
` Q. Your counsel defending you today?
` A. Yes.
` Q. And potentially other lawyers at his law
`firm, I presume?
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`3 (Pages 6 to 9)
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`Page 8
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` A. Yes.
` Q. Did anyone else contribute to the work or
`analysis for your opinions in this declaration?
` A. I don't recall any.
` Q. Okay. And in your declaration, you
`provided your opinions regarding the validity of the
`'589 patent based on several different references,
`right?
` A. That's correct.
` Q. So I just have to -- I just want to ask a
`few questions about some of -- some of those
`opinions. And let's start with -- well, actually,
`we can -- if you still have the second page of your
`declaration pulled up, some of the opinions you
`provided were based on a reference which is listed
`here as 1005, U.S. Patent Number 5,774,402, to Lee,
`correct?
` A. That's correct.
` Q. And can we just refer to that as the Lee
`reference this morning?
` A. Yeah, sure.
` Q. Okay. So if you will flip in your
`declaration to page 70, I believe. Please let me
`know when you're there.
` A. Okay. That's page 70 on the bottom or --
`
`Page 9
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` Q. It is. And it should also be page 70 in
`the PDF.
` A. Okay. There's different numbers. The
`exhibit page number is four off from the PDF. So
`which page? I think you want me to turn to page 66
`of the -- the --
` Q. Oh, I'm sorry. I forgot there are two page
`numbers. I was looking in the bottom right corner.
`So, yes, 66 in the middle; page 70 in the bottom
`right.
` A. Yeah. Okay. I got it.
` Q. Okay. And this is an annotated figure of
`Lee of one of -- of figure 3 from Lee that you
`provide in your declaration, correct?
` A. That is correct.
` Q. So I just want to kind of use this to
`orient -- orient us to -- to what we're talking
`about here. So just at a high level, can you kind
`of describe what is presented here and -- and
`generally what -- what this annotated figure is
`showing?
` A. Yeah. In -- what I'm doing here with this
`figure is mapping the -- the circuitry that's
`disclosed in Lee onto the claim limitations. And
`this signal INIT is what I'm saying is -- I'm
`
`GregoryEdwards, LLC | Worldwide Court Reporting
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`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 10
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`mapping that to the supply voltage stable signal.
`And the signal RST, R-S-T, is the enable signal.
`And what's shown in gray is the enable circuit. And
`what's shown in yellow is the initialization
`circuit.
` Q. Okay. And you've got -- I believe you put
`some orange -- an orange bracket around the inputs
`to what you've labeled as the "Enable Circuit."
`There's three different signals there, right?
` A. On the left you mean, yeah, the command
`signals.
` Q. And those signals are, in Lee, DSF, RASB,
`and CASB, right?
` A. That is correct. Yeah.
` Q. So I wanted to ask you some questions about
`what those signals are precisely. And feel free to
`reference your declaration or point me to anywhere
`where you've discussed it if that would be helpful.
`But let's just start at the top. Well, actually,
`let's start at the bottom.
` So what -- what is CASB? And is that how
`you would refer to it, or call it "CASB," or what
`would be easiest this morning?
` A. I would refer to it as CAS. It's --
` Q. CAS?
`
`Page 11
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` A. The B is -- stands for "bar," meaning it's
`low true. But RAS and CAS are commonly used signals
`in DRAMs. Frequently they're low. They're low
`active. They're drawn with a bar over them. So
`what Lee has done is -- which is fairly common, is
`just labeled it, you know, "CASB," which is -- which
`is the same as "CAS" with a bar over it, meaning
`it's low -- it's low active. So I think we could
`just refer to those as RAS and CAS if you want.
` Q. Okay. That works.
` And what is the DSF signal?
` A. That's a special mode pin that is used on
`certain DRAMs to enable the activation of certain
`modes, special modes.
` Q. And so I believe in your declaration, you
`refer to these -- these are examples of control
`signals that are typically provided to a DRAM,
`right?
` A. That's correct.
` Q. And I think you had identified some other
`ones. There are additional control signals, such as
`Chip Select, Write Enable. Does that sound right?
` A. Did I identify those with respect to Lee or
`in general? I mean --
` Q. Just in general for DRAM devices.
`
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`4 (Pages 10 to 13)
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`Page 12
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` A. Yeah. So DRAMs have other signals,
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`typically Output Enable, Write Enable, Chip Enable.
`
`They sometimes have different names. But those are
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`commonly used in -- in memory -- memory devices as
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`additional control signals.
`
` Q. Okay. And, actually, if I could direct you
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`to paragraph 53 of your declaration, which is on
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`page 31 in the bottom right corner, which is 31 of
`
`the PDF --
`
` A. Okay.
`
` Q. -- or page 27 in the -- in the middle.
`
` A. Yes, I see that.
`
` Q. Okay. So I'm just looking at this
`
`statement. The -- well, let me back up.
`
` So at the start of paragraph 53, brief
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`explanation of CAS and RAS and those other
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`additional control signals, such as Chip Select and
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`Write Enable, right?
`
` A. Yes, I see that.
`
` Q. And then you explain, let's see, "These
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`various input signals are used to perform specific
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`commands by way of a command decoder," et cetera,
`
`right? Do you see that?
`
` A. Yes.
`
` Q. And then "Depending on the combination of
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`Page 13
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`these input signals sent from the memory controller
`to the DRAM device, a different command is
`identified and performed," correct?
` A. Yes.
` Q. Okay. So -- so signals such as RAS and CAS
`and -- or DSF, those would be individual signals
`provided to a DRAM normally, right?
` A. Yeah. In general those are signals coming
`in externally to the DRAM.
` Q. Okay. Those are -- those are examples of
`signals that come in externally to the DRAM. Got
`it.
` And can you kind of walk me through --
`again, looking back at your annotated figure of Lee,
`what does the -- what you have put a box around
`calling it "Enable Circuit," what does it do with
`these signals that are provided to the DRAM?
` A. So there's a circuit -- there's a -- a
`circuit there. You see the three inputs coming into
`input buffers. And then there's a circuit that
`requires a certain sequence, or a certain pattern,
`if you will, of those signals. And when it gets
`that pattern, then it -- then SET goes out. Then
`the output SET is activated and then deactivated.
` And I think -- there's a timing diagram in
`
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`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 14
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`figure 4. I don't know if it's here. We'd have to
`pull up Lee. But it illustrates the -- the sequence
`of -- or the pattern of -- of -- of inputs that
`causes that to happen. So the purpose of the gray
`box is to -- or at least the -- box 46 is to detect
`that sequence on the input signals.
` Q. Okay. And let me -- since you mentioned
`Lee and the timing diagram, let me just go ahead and
`mark Lee for us. If you'll give me a second.
` (Deposition Exhibit 2 was marked for
`identification.)
`BY MR. DeZERN:
` Q. I've put in the chat what I've marked as
`Exhibit 2. Let me know when you've got it pulled
`up, please.
` A. Okay. I have it.
` Q. Okay. And if you could flip to figure 4,
`which I believe is the timing diagram you were just
`referring to. And let me know when you've got that.
` A. Yeah, I have that.
` I've got it.
` Q. Okay. Thank you. Sorry. I just wanted to
`make sure I've got it, too.
` Okay. So with figure 4 pulled up, if you
`could just kind of explain at a high level what --
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`Page 15
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`what's going on in your annotated figure 3 using
`these RAS, CAS, and DSF signals and reference --
`referencing the -- figure 4 of Lee as needed to help
`me understand what's going on.
` A. Yeah. So this is showing RAS -- showing
`CAS going low, and then there's a little arrow that
`is drawn down to the signal C. I'm just going to
`call it C. There's a little Greek symbol before it
`indicating that's a clock signal, PHY symbol. But
`let's just call it C.
` So CAS goes down to C. And so this shows
`the causality here, where CAS goes low, causes C to
`go high, and that causes this -- the signal called
`CTL to go high. And then you have RAS going low,
`which causes R to go high, which then causes the
`signal MSH to go high; and similarly with DSF.
` So the top three lines in this figure are
`the external pins, and everything else are the
`internal signals. And this is illustrating how this
`sequence of CAS low, RAS low, with DSF low causes
`ultimately SET to go high. And the SET signal going
`high is what will basically hold the RST signal
`high.
` Now, one thing to understand about figure 4
`is that the very last line on this figure is --
`
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`5 (Pages 14 to 17)
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`Page 16
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`illustrates what Lee calls -- calls the failure
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`mode, or the error, or the case when the supply
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`voltage stable signal doesn't trigger properly. But
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`in the normal operation, that RST signal would be
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`shown as high coming in from the left. And it's
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`the -- it's the -- the ultimate goal of this whole
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`sequence is for the RST signal to go low, which
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`causes the -- releases the circuits out of
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`initialization.
`
` So -- so that very last little arrow going
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`down to RST is not actually -- doesn't actually
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`exist in the normal operation, but in the case
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`that -- what Lee calls the -- the failure of the
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`power-up signal to enable properly, then that would
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`cause RST to go high before it goes low.
`
` Q. Okay. So let me follow up on -- on some of
`
`that to make sure I understand.
`
` So if we're looking at figure 4 of Lee --
`
`and correct me if I'm wrong, but if -- if operating
`
`normally, then the RST signal, R-S-T -- again, we'll
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`just -- we'll ignore the Greek symbol in front of
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`it. But the RST signal, you're saying, should be
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`high. It should already have been high regardless
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`of the operation of -- of this -- the rest of this
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`timing diagram that we're looking at?
`
`Page 17
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` A. Yeah, that's right. And that can be seen
`by looking at figure 3, because in -- when -- when
`the INIT -- the INIT signal triggers RST to go high.
`And everything in figure 4 is what happens after
`power-on, after the voltage supply signal.
` So in the normal mode, the INIT signal --
`and you can see the INIT signal goes down to this
`gate 50 if you look at figure 3. And that's a
`little latch, because there's feedback. So -- so
`when INIT goes high, then the output goes low, which
`causes 52 to go high, which then will hold that NOR
`gate in -- in a high state -- or I mean in a low
`state, which will cause RST to go high.
` So in the normal mode of operation, when,
`you know, the -- the power-up circuit works
`correctly, then you would see the RST signal high
`coming in from the left, because -- because you only
`need the circuit -- you only need 46 to -- to
`trigger it to go low in the normal mode. But the --
`Lee has drawn it this way, I think, to illustrate
`one of the ideas, which was that even in the case
`that you have failed -- that the power-up supply
`circuit has failed, you can still --
` (Discussion off the record.)
` THE WITNESS: I'm sorry.
`
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`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 18
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` -- the power-up circuit has failed, you can
`still recover -- you can still initialize the
`device.
`BY MR. DeZERN:
` Q. Okay. And let me just clarify one thing.
` So the -- when the INIT signal from the --
`the circuit on top -- which I believe is labeled 16
`in figure 3 of Lee, right?
` A. Yes.
` Q. And I believe you said that's provided to,
`I think you were talking about the NOR gate 50,
`correct?
` A. Correct.
` Q. And you said that -- that latches the value
`or -- or that is a latch? I may have missed that.
` A. This -- this -- the combination of 50 and
`52 is a latch, a type of latch, because -- because
`of the feedback. And you can see that because when
`one side of the NOR gate is high, then the output
`will go low, and then 50 will cause the other side
`of the NOR gate to go high, which now means it will
`be held high, regardless of what the first input
`does. So what that means is a pulse on INIT, which
`is what happens if you look at figure 2 -- just a
`high-going pulse on INIT will cause this thing to
`
`Page 19
`
`latch high and stay high --
` Q. Okay.
` A. -- because of the feedback.
` Q. Okay. And so that latch should maintain
`the value that's provided it from INIT?
` A. Yeah, until something happens on SET.
` Q. Okay. And so let's go back, then, to --
`well, let's talk about the SET signal, then. So if
`we're looking at figure 4 of Lee, you first walked
`through, a moment ago, how the -- the external
`control signals RAS, CAS, and DSF results in sending
`SET high, right?
` A. Right.
` Q. And that -- that I believe you described as
`a -- a fail-safe to deal with in case -- in case --
`in case RST is not already high from the -- from the
`INIT operation that we just discussed, right?
` A. Yeah, that's right. The -- in the normal
`mode, SET going high doesn't trigger anything,
`because RST is already high.
` Q. Okay. And then what I wanted to ask you
`about -- okay. So then what does -- what does the
`circuit 46 in figure 3 of Lee -- what does it then
`do to change that? Can you -- can you walk through
`the operation of --
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`6 (Pages 18 to 21)
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`Page 20
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` A. Yes. So --
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` Q. Yeah. Go ahead.
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` A. Yeah. So, I mean, the -- on the right half
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`of figure 4, you see the sequence that leads to SET
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`going low. And so basically once CAS and RAS are
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`both low, with DSF low, then at some point later CAS
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`will go high. And that's shown with that little
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`arrow. That will cause the internal signal C to go
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`causes SET to go low, which then causes RST to go
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`low. So that whole sequence of events there will
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`then result in the RST signal going low.
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` Q. Okay. And then -- then what's your
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`understanding of -- what happens when that RST
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`signal goes low?
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` A. Well, that basically releases the -- the
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`circuits from -- the control circuits in the chip
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`from being held in RST. So they're no longer being
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`held, and so they can then operate normally, is
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`essentially what happens.
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` Q. Well, can you point me to where in Lee --
`
`well, first of all, actually, let me back up.
`
` So looking at your annotated figure on,
`
`again, in the bottom right corner, page 70 of your
`
`Page 21
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`declaration, you've drawn in a control circuit to
`the right here, correct?
` A. Yes.
` Q. Because Lee doesn't explicitly describe any
`control circuit, correct?
` A. Well, I think there is explicit disclosure
`in Lee, in the spec, that describes circuits that I
`would consider to be control circuits. And that's
`why I consider Lee to be an anticipatory reference,
`even outside, you know, the obviousness question or
`the combination with Iketani. I've drawn it in here
`because it's not in a figure. But somewhere in
`here -- I don't know the paragraph -- I quote from
`the spec where Lee talks about control circuits and
`functional circuitry, and I think that that would be
`understood -- especially in the context of power-on
`reset and what that means, someone of skill in the
`art would understand that that is control circuitry
`is -- as that is in the '589, in my opinion.
` Q. Okay. Can you point me to the places in
`Lee that you're describing that -- that suggest this
`control circuitry?
` A. Yeah. Let me just look at the declaration.
` MR. KAPADIA: Objection; misstates --
`objection; misstates witness testimony.
`
`GregoryEdwards, LLC | Worldwide Court Reporting
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`
`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 22
`
` THE WITNESS: Okay. In paragraph 129, I
`have some citations to Lee, and -- so, I mean, we
`could go back and look at Lee, but, I mean, I think
`that I've kind of summarized them in paragraph 129,
`the portions of Lee, at least the most significant
`ones, that I think disclose a control circuit.
`BY MR. DeZERN:
` Q. Okay. So let's start with the first one.
`I'm looking at paragraph 129. And you've quoted
`from Lee. Again, in your declaration Exhibit 1005
`is Lee, correct?
` A. That's right.
` Q. And you've quoted: "'An inverter 54'" --
`and I won't read the whole thing, but it goes on,
`"'...for sending the reset signal RST to a circuit
`to be initialized within the chip,'" right?
` A. That's right.
` Q. So that's one. Let me look at the next
`one.
` And, again, I won't read the whole quote.
`You're quoting again from column 4, 59 to 62, and at
`the end of that quote, you know, "'thereby
`initializing the circuits within the chip,'" right?
` A. Yes.
` Q. So what's your understanding of what it
`
`Page 23
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`means to -- when Lee says "initializing the
`circuits" in "the chip"?
` A. Well, you know, in the context of Lee,
`which is a semiconductor memory, and what's
`understood as a power-on reset, what -- I think it's
`pretty clear to someone of skill that that means
`circuitry in the chip, for example, sequential
`circuitry or other circuitry, that needs to be
`initialized in order to -- for it to operate
`properly.
` It's -- I mention in here in the background
`section it's well known that circuitry with state
`needs to be initialized. And so I think it's pretty
`clear that when Lee talks about circuits to be
`initialized, they mean that there are circuits, and
`the RST signal will hold them in RST until it goes
`low, and then they're allowed to operate. And those
`circuits are circuits in a RAM -- a DRAM or a memory
`device that control the operation.
` Q. Okay. Let me unpack that a little bit.
` So circuits to be -- if I understood
`correctly, are you saying that for -- for circuits
`that have state, initializing is to put them in a
`particular state?
` A. It's to -- yeah. It -- generally speaking,
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`7 (Pages 22 to 25)
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`Page 24
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`a flip-flop or a latch powers up in an undetermined
`state. You don't know whether it's a 0 or a 1, for
`example. So they need to be reset. And the way
`that works in a power-on environment is that there's
`a signal that holds them in an uninitialized state
`until the reset is deasserted, in which case they
`have been initialized. And once they -- once the
`initialization signal is deasserted, then they
`operate the way they're intended. They operate
`normally.
` Q. Okay. So when -- when the RST signal in
`Lee is asserted, that -- that holds these circuits
`in a particular state?
` A. Correct.
` Q. Okay. And now let me ask you, and so in
`particular, when we're talking about the circuitry
`in figure 3 of Lee, when it operates as you've
`described and asserts that RST, that initializes
`the -- that initializes some circuit and holds them
`in a particular state, right?
` A. That's right. I think it's -- that would
`be understood by one of skill in the art as what RST
`does --
` Q. Okay.
` A. -- given the disclosure of Lee.
`
`Page 25
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` (Discussion off the record.)
` THE WITNESS: Given the disclosure of Lee.
`BY MR. DeZERN:
` Q. Okay. And then looking at figure 3 again,
`so this RST signal is asserted based on the
`occurrence of DSF, RAS, and CAS signals, which are
`externally provided to the DRAM, right?
` A. No. It's asserted when the power is -- is
`provided. Right? So in the normal mode, as soon as
`the power is applied, RST goes high. So it starts
`out high, essentially, before anything is applied to
`the chip, in the normal mode.
` Q. Okay. Yeah. You're -- thank you. So --
`so assuming the -- the top circuit and the -- the
`INIT signal operates as -- as expected or hoped,
`then RST would already be asserted high, correct?
` A. Correct.
` Q. And then in Lee, Lee, in order to provide a
`solution in case there's a malfunction, it provides
`this other circuitry which will assert it high -- if
`it's -- if it's not already, it will assert the RST
`high based on the external signals, RAS, CAS, and
`DSF, right?
` A. That's not exactly correct. The RAS, CAS,
`and DSF are needed to enable the circuit, period,
`
`GregoryEdwards, LLC | Worldwide Court Reporting
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`
`

`

`Stephen W. Melvin, Ph.D. - November 21, 2023
`
`Page 26
`
`regardless of whether you're in the normal mode or
`not, because they're needed in order to deassert
`RST. So -- so when -- in the normal mode, RST
`starts out high, and then after a sequence of
`signals on RAS, CAS, and DSF, then it gets
`deasserted.
` Q. Okay.
` A. So it's not just to deal with this failure
`mode. It's in normal mode as well. You need the
`external sequence in order to deassert RST.
` Q. So what do you mean by "normal mode" in
`this context?
` A. I'm using the word "normal mode" to mean
`when the circuit 16 -- or 12, 14, and 16 operate,
`you know, without an error, you know --
` Q. Okay.
` A. -- sort like figure 2, which is prior art,
`but it shows these solid lines and these little
`dotted lines. And the dotted lines indicate a --
`what they -- what Lee calls a malfunction, and the
`solid line is valid operation. So I guess even
`though this is prior art, that applies to the top
`half of figure 3. So when I say the normal mode,
`I'm talking about what he calls "Valid Operation."
` Q. Okay. And so -- so, then, it needs the --
`
`Page 27
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`the application of the external signals, DSF, RAS,
`and CAS, to -- I forget how you said it -- deassert
`RST or to drop RST low?
` A. Yeah, "deassert" is okay; drop it low.
`Same thing. Yeah. To deassert it.
` Q. Okay. So thereafter, if -- if the circuit
`in Lee received those external signals -- again,
`DSF, RAS, and CAS -- would the same operation play
`out again; i.e., it would -- it would cause RST to
`rise and then bring it down again?
` A. Yeah, theoretically one could do that. I
`don't think that Lee's concerned with that idea.
`It's the -- it's just when you're powering up. But
`in theory one could apply that pattern subsequent
`to -- I mean, multiple times. But the teaching of
`Lee is that, you know, this is done at power-up.
` Q. Okay. So -- well, what would happen in
`a -- I mean, because we talked at the beginning, the
`DSF, RAS, and CAS, these are -- are or were
`common -- common external signals provided to a
`DRAM, right?
` A. Yes.
` Q. So if a DRAM included the circuit described
`in Lee and it received those signals, RAS, CAS, and
`DSF, you would expect the behavior to continue where
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`8 (Pages 26 to 29)
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`Page 28
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`RST would go high and then go low, right?
` A. Yeah. I think what you're asking is,
`theoretically if a memory controller were applied
`this initialization sequence at some subsequent
`time, which in theory it could happen, then, yeah,
`RST would go high and would -- low -- low again.
` Q. Okay.
` A. So --
` Q. And you experience it -- oh, I'm sorry. I
`didn't mean to cut you off.
` A. No, so, I mean, that would be -- you know,
`that would be the case if -- if you were to assert
`the same pattern of signals in the circuit of Lee.
` Q. And these -- these external signals like
`RAS and CAS are used in DRAMs for a number of
`purposes, right?
` A. Well, yeah. RAS and CAS are used for
`normal reads and writes to strobe -- I mean, it's a
`Row Address Strobe and Column Address Strobe, is
`what the acronym stands for. So it's used to -- to
`indicate to the DRAM that there's address -- that
`the address signals are valid.
` Q. Okay. Yeah, and I think you described
`generally in your declaration, if I can remind
`myself -- again, I think this is in column -- I'm
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`Page 29
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