UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`XILINX, INC.,
`Petitioner
`
`
`v.
`
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner
`
`
`
`Case No.: IPR2023-00516
`Patent No.: 6,157,589
`For: Dynamic Semiconductor Memory Device and Method for Initializing a
`Dynamic Semiconductor Memory Device
`
`
`
`DECLARATION OF TIMOTHY D. DORNEY, PH.D.
`
`PURSUANT TO 37 C.F.R. § 1.68
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`
`
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`TABLE OF CONTENTS
`
`V.
`
`INTRODUCTION ........................................................................................... 1
`I.
`PROFESSIONAL BACKGROUND ............................................................... 3
`II.
`III. MATERIALS REVIEWED AND RELIED UPON ........................................ 7
`IV. LEGAL STANDARDS .................................................................................... 8
`A. Anticipation ........................................................................................... 8
`B. Obviousness ........................................................................................... 8
`C.
`Claim Construction Standard ..............................................................10
`THE ’589 PATENT ........................................................................................ 11
`A. Overview of the ’589 Patent Background ........................................... 11
`B.
`The ’589 Patent Invention ...................................................................13
`1.
`The ’589 Patent teaches “said enable circuit outputting an
`enable signal after a predetermined proper initialization
`sequence of the externally applied further command signals
`being identified”. .......................................................................13
`The ’589 Patent teaches “the enable signal effecting an
`unlatching of said control circuit.”............................................15
`Prosecution History .............................................................................18
`C.
`VI. KOCIS (EXHIBIT 1004) ...............................................................................19
`A. Overview of Kocis’ Background .........................................................19
`B. Kocis’ Disclosure ................................................................................20
`C.
`Limitations of the Kocis’ Disclosure ...................................................23
`VII. LEE (EXHIBIT 1005) ...................................................................................24
`A. Overview of Lee’s Background ...........................................................24
`B.
`Lee’s Disclosure ..................................................................................26
`C.
`Limitations of the Lee’s Disclosure ....................................................29
`VIII. JESD 21-C (EXHIBIT 1006) ........................................................................36
`A. Overview of JESD 21-C ......................................................................36
`
`2.
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`IX.
`
`C.
`
`2.
`
`Limitations of the JESD 21-C Disclosure ...........................................38
`B.
`IKETANI (EXHIBIT 1007) ...........................................................................40
`A. Overview of Iketani’s Background .....................................................40
`B.
`Iketani’s Disclosure .............................................................................40
`C.
`Limitations of the Iketani’s Disclosure ...............................................43
`X. OPINIONS .....................................................................................................43
`A.
`Standard for a POSITA ........................................................................43
`B.
`Claim Construction For “Externally Applied Further Command
`Signals”................................................................................................45
`Claims 1, 9, 11, and 13 are Not Invalid under Ground 1 ....................47
`1.
`Claim Element 1.2, “said initialization circuit having a control
`circuit for controlling operations and an enable circuit receiving
`the supply voltage stable signal and externally applied further
`command signals” is not disclosed in Kocis .............................48
`Claim Element 1.3, “said enable circuit outputting an enable
`signal after a predetermined proper initialization sequence of
`the externally applied further command signals being identified
`and the enable signal effecting an unlatching of said control
`circuit” is not disclosed in Kocis ..............................................49
`Claim 9, “said control circuit has output drivers remaining
`latched during the switching-on operation until said enable
`signal is generated by said enable circuit” is not disclosed in
`Kocis .........................................................................................53
`Claim Element 11.2, “supplying, via an enable circuit of the
`initialization circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further command
`signals externally applied to the dynamic semiconductor
`memory device, after an identification of a predetermined
`proper initialization sequence of the further command signals
`the enable signal being generated and effecting an unlatching of
`a control circuit provided for a proper operation of the dynamic
`semiconductor memory device” is not disclosed in Kocis .......56
`
`3.
`
`4.
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`5.
`
`2.
`
`3.
`
`Claim 13, “maintaining a latched condition of output drivers of
`the dynamic semiconductor memory device during the
`switching-on operation until the enable signal is generated by
`the enable circuit” is not disclosed in Kocis .............................57
`Claims 2, 8, 10, and 12 are Not Invalid under Ground 2 ....................58
`1.
`Claim 2, “externally applied further command signals forming
`the predetermined proper initialization sequence to be
`identified by said enable circuit includes at least one of a
`preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command
`signal” is not disclosed in Kocis in view of JESD 21-C...........60
`Claim 8, “the identification of an initialization sequence that is
`identified as the predetermined proper initialization sequence
`by said enable circuit and generates the enable signal
`constitutes a command sequence conforming to a JEDEC
`standard” is not disclosed in Kocis in view of JESD 21-C ......62
`Claim 10, “the predetermined proper initialization sequence
`includes one of the following chronologically successive
`command sequences: a) firstly PRE, secondly ARF, thirdly
`MRS; b) firstly PRE, secondly MRS, thirdly ARF; and c) firstly
`MRS, secondly PRE, or thirdly ARF; where, PRE=the
`preparation command signal for word line activation, ARF=the
`refresh command signal, and MRS=the loading configuration
`register command signal” is not disclosed in Kocis in view of
`JESD 21-C .................................................................................63
`Claim 12, “providing at least one of a preparation command
`signal for word line activation, a refresh command signal, and a
`loading configuration register command signal as the further
`command signals” is not disclosed in Kocis in view of JESD
`21-C ...........................................................................................64
`Claims 1 and 11 are Not Invalid under Ground 3A/3B ......................64
`Claim Element 1.2, “said initialization circuit having a control
`1.
`circuit for controlling operations and an enable circuit receiving
`the supply voltage stable signal and externally applied further
`command signals” is not disclosed in Lee ................................65
`
`D.
`
`E.
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`4.
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`2.
`
`3.
`
`Claim Element 1.3, “said enable circuit outputting an enable
`signal after a predetermined proper initialization sequence of
`the externally applied further command signals being identified
`and the enable signal effecting an unlatching of said control
`circuit” is not disclosed in Lee ..................................................68
`Claim Element 11.2, “supplying, via an enable circuit of the
`initialization circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further command
`signals externally applied to the dynamic semiconductor
`memory device, after an identification of a predetermined
`proper initialization sequence of the further command signals
`the enable signal being generated and effecting an unlatching of
`a control circuit provided for a proper operation of the dynamic
`semiconductor memory device” is not disclosed in Lee ..........72
`Claims 1 and 11 are Not Invalid under Ground 4 ...............................73
`1.
`Claim Element 1.2, “said initialization circuit having a control
`circuit for controlling operations and an enable circuit receiving
`the supply voltage stable signal and externally applied further
`command signals” is not disclosed in Lee in view of Iketani ..73
`Claim Element 1.3, “said enable circuit outputting an enable
`signal after a predetermined proper initialization sequence of
`the externally applied further command signals being identified
`and the enable signal effecting an unlatching of said control
`circuit” is not disclosed in Lee in view of Iketani ....................74
`Claim Element 11.2, “supplying, via an enable circuit of the
`initialization circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further command
`signals externally applied to the dynamic semiconductor
`memory device, after an identification of a predetermined
`proper initialization sequence of the further command signals
`the enable signal being generated and effecting an unlatching of
`a control circuit provided for a proper operation of the dynamic
`semiconductor memory device” is not disclosed in Lee in view
`of Iketani ...................................................................................76
`Claims 2, 8, 10, and 12 are Not Invalid under Ground 5 ....................77
`
`2.
`
`3.
`
`F.
`
`G.
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`1.
`
`2.
`
`3.
`
`Claim 2, “externally applied further command signals forming
`the predetermined proper initialization sequence to be
`identified by said enable circuit includes at least one of a
`preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command
`signal” is not disclosed in Lee in view of JESD 21-C ..............78
`Claim 8, “the identification of an initialization sequence that is
`identified as the predetermined proper initialization sequence
`by said enable circuit and generates the enable signal
`constitutes a command sequence conforming to a JEDEC
`standard” is not disclosed in Lee in view of JESD 21-C ..........79
`Claim 10, “the predetermined proper initialization sequence
`includes one of the following chronologically successive
`command sequences: a) firstly PRE, secondly ARF, thirdly
`MRS; b) firstly PRE, secondly MRS, thirdly ARF; and c) firstly
`MRS, secondly PRE, or thirdly ARF; where, PRE=the
`preparation command signal for word line activation, ARF=the
`refresh command signal, and MRS=the loading configuration
`register command signal” is not disclosed in Lee in view of
`JESD 21-C .................................................................................80
`Claim 12, “providing at least one of a preparation command
`signal for word line activation, a refresh command signal, and a
`loading configuration register command signal as the further
`command signals” is not disclosed in Lee in view of JESD 21-C
` ...................................................................................................81
`Claims 2, 8, 10, and 12 are Not Invalid under Ground 6 ....................82
`1.
`Claim 2, “externally applied further command signals forming
`the predetermined proper initialization sequence to be
`identified by said enable circuit includes at least one of a
`preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command
`signal” is not disclosed in Lee in view of Iketani and JESD 21-
`C ................................................................................................83
`Claim 8, “the identification of an initialization sequence that is
`identified as the predetermined proper initialization sequence
`
`H.
`
`4.
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`2.
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`3.
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`4.
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`by said enable circuit and generates the enable signal
`constitutes a command sequence conforming to a JEDEC
`standard” is not disclosed in Lee in view of Iketani and JESD
`21-C ...........................................................................................84
`Claim 10, “the predetermined proper initialization sequence
`includes one of the following chronologically successive
`command sequences: a) firstly PRE, secondly ARF, thirdly
`MRS; b) firstly PRE, secondly MRS, thirdly ARF; and c) firstly
`MRS, secondly PRE, or thirdly ARF; where, PRE=the
`preparation command signal for word line activation, ARF=the
`refresh command signal, and MRS=the loading configuration
`register command signal” is not disclosed in Lee in view of
`Iketani and JESD 21-C ..............................................................86
`Claim 12, “providing at least one of a preparation command
`signal for word line activation, a refresh command signal, and a
`loading configuration register command signal as the further
`command signals” is not disclosed in Lee in view of Iketani and
`JESD 21-C .................................................................................87
`Claims 9 and 13 are Not Invalid under Ground 7 ...............................89
`1.
`Claim 9, “said control circuit has output drivers remaining
`latched during the switching-on operation until said enable
`signal is generated by said enable circuit” is not disclosed in
`Lee in view of Kocis .................................................................91
`Claim 13, “maintaining a latched condition of output drivers of
`the dynamic semiconductor memory device during the
`switching-on operation until the enable signal is generated by
`the enable circuit” is not disclosed in Lee in view of Kocis .....93
`Claims 9 and 13 are Not Invalid under Ground 8 ...............................95
`1.
`Claim 9, “said control circuit has output drivers remaining
`latched during the switching-on operation until said enable
`signal is generated by said enable circuit” is not disclosed in
`Lee in view of Iketani and Kocis ..............................................98
`Claim 13, “maintaining a latched condition of output drivers of
`the dynamic semiconductor memory device during the
`
`2.
`
`2.
`
`I.
`
`J.
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`switching-on operation until the enable signal is generated by
`the enable circuit” is not disclosed in Lee in view of Iketani and
`Kocis .......................................................................................100
`XI. CONCLUSIONS .........................................................................................103
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`LISTING OF CHALLENGED CLAIMS
`
`Claim 1
`[1.P]
`
`[1.1]
`
`[1.2]
`
`[1.3]
`
`Claim 2
`[2]
`
`Claim 8
`[8]
`
`A dynamic semiconductor memory device of a random access type,
`comprising:
`an initialization circuit controlling a switching-on operation and supplying
`a supply voltage stable signal once a supply voltage has been stabilized
`after the switching-on operation,
`said initialization circuit having a control circuit for controlling operations
`and an enable circuit receiving the supply voltage stable signal and
`externally applied further command signals,
`said enable circuit outputting an enable signal after a predetermined proper
`initialization sequence of the externally applied further command signals
`being identified and the enable signal effecting an unlatching of said
`control circuit.
`
`The semiconductor memory device according to claim 1, wherein the
`externally applied further command signals forming the predetermined
`proper initialization sequence to be identified by said enable circuit
`includes at least one of a preparation command signal for word line
`activation, a refresh command signal, and a loading configuration
`register command signal.
`
`The semiconductor memory device according to claim 1, wherein the
`identification of an initialization sequence that is identified as the
`predetermined proper initialization sequence by said enable circuit and
`generates the enable signal constitutes a command sequence conforming
`to a JEDEC standard.
`
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`Claim 9
`[9]
`
`The semiconductor memory device according to claim 1, wherein said
`control circuit has output drivers remaining latched during the switching-
`on operation until said enable signal is generated by said enable circuit.
`Claim 10
`The semiconductor memory device according to claim 1, wherein the
`[10]
`predetermined proper initialization sequence includes one of the following
`chronologically successive command sequences:
`a) firstly PRE, secondly ARF, thirdly MRS;
`b) firstly PRE, secondly MRS, thirdly ARF; and
`c) firstly MRS, secondly PRE, or thirdly ARF;
`where,
`PRE=the preparation command signal for word line activation,
`ARF=the refresh command signal, and
`MRS=the loading configuration register command signal.
`Claim 11
`[11.P] An improved method for initializing a dynamic semiconductor memory
`device of a random access type via an initialization circuit controlling a
`switching-on operation of the dynamic semiconductor memory device and
`of its circuit components, the improvement which comprises:
`supplying, via the initialization circuit, a supply voltage stable signal once
`a supply voltage has been stabilized after the switching-on operation of the
`dynamic semiconductor memory device; and
`supplying, via an enable circuit of the initialization circuit, an enable
`signal, the initialization circuit receiving the supply voltage stable signal
`and further command signals externally applied to the dynamic
`semiconductor memory device, after an identification of a predetermined
`proper initialization sequence of the further command signals the enable
`signal being generated and effecting an unlatching of a control circuit
`provided for a proper operation of the dynamic semiconductor memory
`device.
`
`[11.1]
`
`[11.2]
`
`
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`Claim 12
`The method according to claim 11, which comprises providing at least one
`[12]
`of a preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command signal as
`the further command signals.
`Claim 13
`The method according to claim 11, which comprises maintaining a latched
`[13]
`condition of output drivers of the dynamic semiconductor memory device
`during the switching-on operation until the enable signal is generated by
`the enable circuit.
`
`
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`I, Timothy D. Dorney, Ph.D., do hereby declare:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I am making this declaration (“Declaration”) at the request of Patent
`
`Owner Polaris Innovations Limited (“Polaris”) in the matter of the Inter Partes
`
`Review No. IPR2023-00516 of U.S. Patent No. 6,157,589 (“the ’589 Patent”).
`
`2.
`
`I have been asked to consider whether or not a person of ordinary skill
`
`in the art (“POSITA”) would have found the invention in the ’589 Patent as set
`
`forth by the issued claims 1, 2, 8, 9, 10, 11, 12, and 13 are anticipated and/or
`
`obvious in light of the material made available to me in this case.
`
`3.
`
`In this declaration, I set forth my opinions concerning the general
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`subject matter of the issued claims in the ’589 Patent, including the state of the art
`
`in DRAM memory design in the 1990s. My opinions are based on my knowledge,
`
`education, experience, and a review of the material provided to me in this case.
`
`4.
`
`I understand that the PTAB has instituted an Inter Partes Review of
`
`claims 1, 2, 8, 9, 10, 11, 12, and 13 of the ’589 Patent based on the arguments
`
`presented in the Petition (IPR2023-00516, Document 2) as supported by the
`
`Declaration of Dr. Stephen W. Melvin (IPR2023-00513, Ex. 1003) (“the Melvin
`
`Declaration”). Claims 1 and 11 are independent claims.
`
`5.
`
`I understand that nine grounds for challenging the patentability of the
`
`claims were presented (numbered 1 through 8 with 3A and 3B). The first ground
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`challenged claims 1, 9, 11, and 13 as anticipated over U.S. Patent No. 5,559,753 to
`
`Kocis (“Kocis”). The second ground challenged claims 2, 8, 10, and 12 as obvious
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`over Kocis in view of the JEDEC STANDARD, Configuration for Solid State
`
`Memories, Compilation of Releases 1 through 7, dated January 1997 (“JESD 21-
`
`C”). The third ground (including 3A and 3B) challenged claims 1 and 11 as
`
`anticipated or obvious over U.S. Patent No. 5,774,402 to Lee (“Lee”). The fourth
`
`ground challenged claims 1 and 11 as obvious over Lee in view of U.S. Patent No.
`
`5,703,510 to Iketani et al. (“Iketani”). The fifth ground challenged claims 2, 8, 10,
`
`and 12 as obvious over Lee in view of JESD 21-C. The sixth ground challenged
`
`claims 2, 8, 10, and 12 as obvious over Lee in view of Iketani and JESD 21-C. The
`
`seventh ground challenged claims 9 and 13 as obvious over Lee in view of Kocis.
`
`The eighth ground challenged claims 9 and 13 as obvious over Lee in view of
`
`Iketani and Kocis.
`
`6.
`
`I reserve the right to supplement or amend this Declaration based on
`
`any additional information that becomes known that affects my opinions.
`
`7.
`
`I am being compensated for my work in this matter at an hourly rate
`
`of $400 for consulting services. My compensation for this matter is neither
`
`determined by nor contingent on the outcome of this case.
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`II.
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`PROFESSIONAL BACKGROUND
`
`8.
`
`I earned a Bachelor of Science degree in Electrical Engineering from
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`Texas A&M University in College Station, Texas, in 1990.
`
`9.
`
`I earned a Master of Science degree in Electrical Engineering and
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`Applied Physics from Case Western Reserve University in Cleveland, Ohio, in
`
`1992.
`
`10.
`
`I earned a Doctor of Philosophy degree in Electrical and Computer
`
`Engineering from Rice University in Houston, Texas in 2002.
`
`11.
`
`I have extensive experience with semiconductor dynamic random
`
`access memory design and architecture. I was employed by Texas Instruments
`
`Incorporated in the Memory Products Group from 1988 to 1998. During that time,
`
`I was an engineer in the Circuits Center of Expertise, an integrated circuit design
`
`engineer, and a product development engineer.
`
`12. The goal of the Circuits Center of Expertise was to investigate issues
`
`and provide solutions for future circuit designs that would be common across
`
`multiple devices.
`
`13. As an integrated circuit design engineer, I worked on application
`
`specific memory designs for numerous devices including Video Random Access
`
`Memory (VRAM) and Synchronous Random Access Memory (SDRAM). As a
`
`DRAM memory designer, I was responsible for circuit design, circuit layout, and
`
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`pre- and post-silicon verification. Design areas included row and row redundancy,
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`column and column redundancy, design-for-test, I/O buffers, internal refresh, and
`
`data I/O. I performed full-chip schematic verification, design rule verification, and
`
`probe versus simulation comparison. I supported the lead frame design, ESD
`
`implementation, parasitic back annotation, laser repair, and device layout and
`
`routing.
`
`14.
`
`I supported the identification and solution for design issues
`
`encountered by video card/graphics processor design companies. As a product
`
`development engineer, I also used memory device testing systems to investigate
`
`memory device parameter characterization and failure mechanisms.
`
`15. While employed at Texas Instruments Incorporated (TI), I traveled to
`
`Japan (KTI) and Singapore (TECH) to provide DRAM design support and training.
`
`I also traveled to TI-Singapore for DRAM T3/batch testing support. The training
`
`educated engineers about the new design functionality and test capabilities of
`
`forthcoming devices. Also, I was tasked with leading a team to create internal
`
`training materials on the basics of DRAM operation and to provide on-site training
`
`to TI’s worldwide locations.
`
`16.
`
`In 1998, I left Texas Instruments Incorporated to pursue my Doctor of
`
`Philosophy degree full-time. During my time at Rice University, I investigated
`
`processor design and researched the effects of modifying DRAM parameters on the
`
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`processing system; I investigated improvements to wavelet-based image
`
`compression; and I investigated computed tomography and methodologies to
`
`improve imaging.
`
`17. My thesis research involved material parameter estimation and
`
`imaging using terahertz frequency waves. The terahertz frequency band is above
`
`the microwave frequency band and below the infrared frequency band. This
`
`research, using a fiber optic coupled, terahertz time-domain spectroscopy system,
`
`often centered on providing computer calculated graphical and synthetic image
`
`representations resulting from solutions of inverse problems.
`
`18. Upon completion of the Ph.D. degree requirements, I was employed
`
`by Rosenthal & Osha L.L.P., to draft and prosecute patent applications. Major
`
`clients included Sun Microsystems, which was a processor and computer
`
`manufacturer, and NASA’s Johnson Space Center. In 2003, I started working in
`
`patent licensing, first at Texas Instruments Incorporated and then at Personalized
`
`Media Communications, LLC, which has involved investigating patents and
`
`products from technical fields including DRAM and nonvolatile memory, analog
`
`circuits, image sensors, digital displays, processors, digital systems, video
`
`streaming, and Internet communications.
`
`19. Beginning during my Bachelor of Science degree, I have
`
`experimented and designed multiple systems using embedded microcontrollers,
`
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`including Motorola’s 68HC11 (BUFFALO development system), Texas
`
`Instruments MSP430, Microchip’s PIC, and ARM’s RP2040.
`
`20.
`
`In 2005, I formed a company to focus on an optical delay system that
`
`would be relevant to the terahertz systems involved in my Doctor of Philosophy
`
`research. In 2009, the name of the company was changed to Uviri, LLC, as my
`
`interests expanded to basic research, development of consumer products,
`
`photography, and consulting. Many of the consumer products designs require an
`
`embedded microcontroller to support the desired operation. During my work at
`
`Uviri, LLC, I have also been involved in 2D image editing including layering and
`
`masks using Photoshop, and 3D photo-realistic rendering using Keyshot.
`
`21.
`
`I am a member of the Institute of Electrical and Electronics Engineers
`
`(IEEE). I am a member of the IEEE honor society Eta Kappa Nu, the engineering
`
`honor society Tau Beta Pi, and the Phi Kappa Phi honor society. I passed the
`
`Texas Board of Professional Engineers and Land Surveyors: Fundamentals of
`
`Engineering exam while pursuing a Bachelor of Science degree in Electrical
`
`Engineering from Texas A&M University. In 2002, I became a registered patent
`
`agent. I am listed as an inventor on at least ten domestic or foreign patents. The
`
`subject matter of the majority of these inventions includes improvements to the
`
`performance and/or capabilities of dynamic random access memory.
`
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`22. A more complete summary of my background, qualifications, and
`
`professional experience and affiliations is set forth in my curriculum vitae, which
`
`is attached hereto as Appendix A, and includes a list of my patents and
`
`publications. Also included in my curriculum vitae is a complete list of the cases
`
`in which I have testified as an expert or have been deposed.
`
`III. MATERIALS REVIEWED AND RELIED UPON
`
`23.
`
`In the course of preparing this Declaration, I reviewed the following
`
`documents:
`
`• Petition for Inter Partes Review of U.S. Patent No. 6,157,589 (“Petition”)
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`• Ex. 1001 U.S. Patent No. 6,157,589 (“the ’589 Patent”)
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`• Ex. 1002 Prosecution history of the ’589 Patent (“Application”)
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`• Ex. 1003 Declaration of Dr. Stephen W. Melvin (“the Melvin Declaration”)
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`• Ex. 1004 U.S. Patent No. 5,559,753 to Kocis (“Kocis”)
`
`• Ex. 1005 U.S. Patent No. 5,774,402 to Lee (“Lee”)
`
`• Ex. 1006 JEDEC STANDARD, Configurations for Solid State Memories,
`Compilation of Releases 1 through 7, dated January 1997 (“JESD 21-C”)
`
`• Ex. 1007 U.S. Patent No. 5,703,510 to Iketani et al. (“Iketani”)
`
`• Patent Owner’s Preliminary Response for IPR2023-00516
`
`• Decision Granting Institution of Inter Partes Review for IPR2023-00516
`(“Institution Decision”)
`
`Declaration of Timothy D. Dorney, Ph.D.
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`7
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`IPR2023-00516
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`• Ex. 2002 Deposition of Stephen W. Melvin, Ph.D. (Nov. 21, 2023)
`
`IV. LEGAL STANDARDS
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`24.
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`I am not an attorney. I have been advised of the following general
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`principles of patent law to be considered in formulating my opinions as to whether
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`the claims of the ’589 Patent would have been obvious to a person of ordinary skill
`
`in the art (“POSITA”) at the time of the invention in view of the prior art.
`
`A. Anticipation
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`25.
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`I understand that a prior art reference anticipates a claim if every
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`limitation of the claimed invention is found in a single prior art reference, either
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`expressly or inherently, arranged as in the claim. I understand that a claim element
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`is inherent in a prior art reference if it is “necessarily present” in the disclosed
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`apparatus, system or method, not merely probably or possibly present. I understand
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`that a patent claim cannot be anticipated by a prior art reference if the allegedly
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`anticipatory disclosures in the reference are not enabled. I understand that merely
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`naming or description of the subject matter is insufficient if it cannot be produced
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`without undue experimentation.
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`B. Obviousness
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`26.
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`I understand that a prior art reference can render a patent claim
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`obvious to one of ordinary skill in the art if the differences between the subject
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`matter set forth in the patent claim and the prior art are such that the subject matter
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`Declaration of Timothy D. Dorney, Ph.D.
`
`8
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`IPR2023-00516
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`

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`of the claim would have been obvious at the time the claimed invention was made.
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`In analyzing obviousness, I understand that it is important to consider the scope of
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`the claims, the level of skill in the relevant art, the scope and content of the prior
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`art, the differences between the prior art and the claims, and any secondary
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`considerations.
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`27.
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`I understand that when the claimed subject matter involves combining
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`preexisting elements to yield no more than one would expect from such an
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`arrangement, the combination is obvious. I also understand that in assessing
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`whether a claim is obvious, one must consider whether the claimed improvement is
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`more than the predictable use of prior art elements according to their established
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`functions. I understand that there need not be a precise teaching in the prior art
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`directed to the specific subject matter of a claim because one can take account of
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`the inferences and creative steps that a person of ordinary skill in the art would
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`employ. I further understand that a person of ordinary skill is a person of ordinary
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`creativity, not an automaton. However, I understand that obviousness cannot be
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`based on the hindsight combination of components selectively culled from the
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`prior art. I also understand that a combination is not obvious if it requires
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`extensive additional problem-solving steps that are not taught in the references and
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`that