`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC.
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED
`Patent Owner
`
`Case IPR2023-00516
`U.S. Patent 6,157,589
`
`PETITIONER’S UPDATED EXHIBIT LIST
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`UPDATED EXHIBIT LIST
`
`
`Exhibit
`
`Description
`
`1001
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`1002
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`1003
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`1004
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`1005
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`1006
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`1007
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`1008
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`1009
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`1010
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`1011
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`1012
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`1013
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`1014
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`U.S. Patent No. 6,157,589 (the “’589 Patent”)
`
`U.S. Prosecution History of the ’589 Patent
`
`Declaration of Stephen W. Melvin
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`U.S. Patent No. 5,559,753 to Kocis entitled “Apparatus and
`Method for Preventing Bus Contention During Power-Up in a
`Computer System With Two or More DRAM Banks” (“Kocis”)
`
`U.S. Patent No. 5,774,402 to Lee entitled “Initialization Circuit for
`a Semiconductor Memory Device” (“Lee”)
`
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Compilation of Releases 1 through 7, dated
`January 1997 (“JESD 21-C”)
`
`U.S. Patent No. 5,703,510 to Iketani et al. entitled “Power On
`Reset Circuit For Generating Reset Signal at Power On”
`(“Iketani”)
`
`Prosecution History of EPO Patent Application No. 99 113 048.5
`(Original)
`
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (Original)
`
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (English Translation)
`
`Japanese Patent Publication No. JP 09 106668 A to Samsung
`Electronics Co. Ltd. dated April 22, 1997 (“Tetsuka”)
`
`Declaration of Julie Carson
`
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Release 7, dated January 1997
`
`Scheduling Order, Polaris Innovations Limited v. Xilinx, Inc.,
`1:22-cv-00174-RGA, Docket No. 20 (May 31, 2022)
`
`
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`Exhibit
`
`Description
`
`United States District Courts — Federal Court Management
`Statistics, National Judicial Caseload Profile (June 30, 2022),
`available at https://www.uscourts.gov/sites/
`default/files/fcms_na_distprofile0630.2022_0.pdf
`
`Motion Success for Stay Pending IPR before Judge Richard G.
`Andrews in the District of Delaware (Docket Navigator data from
`2020 to 1/20/2023)
`
`Excerpt of Micron Technology, Inc., “DRAM Data Book” (1992)
`
`Excerpt of Samsung Electronics Co., Ltd., “Data Book: DRAM”
`(Dec. 1995)
`
`Samsung Electronics, “4M x 8Bit x 4 Banks Synchronous DRAM”
`Doc. No. KM48S16030, Rev. 2 (March 1998)
`
`Patent License, Tolling Stand-Still and Settlement Agreement
`
`1015
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`1016
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`1017
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`1018
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`1019
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`1020
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`Dated: February 8, 2024
`
`
`
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`Respectfully submitted,
`
`/Brian W. Oaks/
`Brian W. Oaks (Reg. No. 44,981)
`Aashish G. Kapadia (Reg. No. 78,844)
`MCDERMOTT WILL & EMERY LLP
`300 Colorado Street, Suite 2200
`Austin, TX 78701
`TEL: 512-726-2600
`FAX: 512-532-0002
`boaks@mwe.com
`akapadia@mwe.com
`
`Attorneys for Petitioner,
`Xilinx, Inc.
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`CERTIFICATE OF SERVICE
`Pursuant to 37 C.F.R. § 42.6, the undersigned certifies that on February 8,
`
`2024, a copy of the PETITIONER’S UPDATED EXHIBIT LIST and EXHIBIT
`
`1020 was electronically served on the following counsel of record for Patent Owner:
`
`david@nelbum.com
`bbumgardner@nbclaw.net
`
`/Brian W. Oaks/
`Brian W. Oaks
`Lead Counsel for Petitioner
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