LATCH-UP IN CMOS INTEGRATED CIRCUITS*
`
`B. L. Gregory and B. D. Shafer
`Sandia Laboratories
`Albuquerque, New Mexico
`
`87115
`
`Abstract
`The parasitic transistors and pnpn paths present on
`junction-isolated CMOS circuits have been identified and
`studied quantitatively. Active SCR structures exist
`which can be triggered electrically or by a radiation
`pulse. Detailed studies of SCR paths have been per-
`to
`formed on two circuits,
`the CD4O07A and the cphokla,
`relate geometrical and materials parameters to latch-up
`sensitivity. Both normal bias conditions and bias opti-
`mum for obtaining SCR action are employed. Several tech-
`niques are proposed to eliminate radiation-induced latch-
`up in future CMOS designs.
`
`Latch-up> through the parasitic pnpn structures in
`bipolar integrated circuits has been responsible,
`in
`part, for the development of dielectric isolation as an
`important hardening technology.
`Since pnpn paths are
`again present in Complementary MOS integrated circuits,
`it is important to explore latch-up effects in this
`technology to determine if dielectric isolation is re-
`quired.
`In the present studies,
`latch-up is considered
`to be the creation of a low resistance path between
`power supply and ground on a circuit, during a radiation
`or electrical pulse, which remains low resistance after
`the pulse.
`The studies in Reference 1 explored the
`possibility of achieving circuit latch-up due to tran-
`sistor sustaining voltage breakdown or due to second
`breakdown.
`The conclusion was that only the pnpn
`mechanism was important in most bipolar IC's. This is
`certainly true in CMOS circuits.
`
`The present study will identify the pnpn paths pre-
`sent on (MOS circuits and demonstrate that active SCR's
`can result. Detailed studies on two particular circuits
`(RCA CDKOO7A and cD4O41A) relate both geometry and
`material parameters to latch-up sensitivity.
`In both
`circuits the parasitic npn and pnp transistors have
`been separately characterized and a variety of pnpn
`paths have been explored.
`The activity of pnpn paths
`is determined by attempting to induce latch-up electri-
`eally.
`The studies employ bias conditions of two types.
`First, bias conditions are used which are optimum for
`obtaining SCR action through each pnpn path.
`Second,
`bias which duplicates actual circuit operation is
`employed to provide a direct measurement of the latch-
`up susceptibility.
`The former studies provide a worst-
`ease situation for latch-up.
`If it is not observed in
`these studies, it will not be present for normal bias
`conditions,
`
`transient
`Subsequent to the electrical studies,
`radiation experiments have been performed to verify the
`electrically-detected latch-up paths and to determine
`the radiation dose rate at which latch-up occurs.
`
`Description of Latch-up Paths
`
`In CMOS circuits the n-channel transistors are
`formed in p-wells diffused into the n-type substrate,
`while the p-channel transistors are formed directly on
`the substrate material.
`The structure is complicated
`by the presence of protection diodes from each input
`gate to the substrate (ptn diode) and to the p-well
`
`*This work was supported by the U. S. Atomic Mmergy
`Commission.
`
`The structure of a typical CMOS circuit
`(ntp diode}.
`is shown schematically in cross section in Figure 1.
`Figures 2 and 3 show the layout and schematics for the
`two CMOS circuits studied most exhaustively in this
`work (4007 and 4041).
`
`It is straightforward to identify several parasitic
`npn and pnp transistors on the 4007 and 4okl by examin-
`ing the structure in Figure 1. First,
`the three-layer
`structure formed by the source, drain, or ntp protection
`diode of the n-channel transistor (n+,
`the p-well (p),
`and the substrate (n), consitutes a double-diffused npn
`device with an nt emitter. Similerly,
`the three-layer
`structure formed by either of the p+ diffusions (pt),
`the substrate (n), and the p-well (p), constitutes a
`pnp transistor.
`The pnp transistor is a wide-base
`lateral structure with relatively low gain.
`The two
`complementary pairs on the O07 can be investigated as
`separate transistors, or as inverters if the p and n
`transistor drains are tied together. For transistor
`operation,
`there is a pnpn path from each input (gate)
`to the source or drain of the n-channel device.
`Simi-
`larly, between the source or drain of the p-channel and
`the source or drain of the n-channel (or gate),
`there
`is another pnpn structure.
`
`For these pnpn paths to be active SCR structures
`which can latch-up during a transient radiation environ-
`ment, several conditions must be met. First,
`the npn
`and pnp transistor gains must be such that hp, (npn) *
`hee (pnp) > 1.
`Secondly,
`the bias conditions applied
`must allow the two end junctions of the pnpn structure
`to become forward biased. Finally,
`the Vyp and input
`bias circuits must be capable of supplying current equal
`to the holding current of the SCR.
`In an actual inverter,
`the p and n channel source diodes are shorted to the
`substrate and p-well, respectively, and do not become
`forward biased in normal operation. However, lateral
`voltage drops can exist during exposure to a transient
`radiation pulse, due primarily to p-well photocurrent,
`which can cause forward bias to appear over portions of
`the source contacts, even though they are elsewhere
`shorted to substrate or p-well.
`In Figure 4 we show
`the equivalent circuits of SCR's present on a CMOS cir-
`cuit
`(4007) for the worst-case (A) and normal
`(B) bias
`conditions.
`The same essential pnpn structures are
`active in both bias situations; however, for the normal
`bias case,
`the forward bias on the two emitter junctions
`(gates) must be provided by lateral voltage drops due to
`the p-well photocurrent (or SCR current after turn-on)
`flowing laterally through the substrate and p-well re-
`Sistances, R, and
`For this reason,
`the active SCR
`in case B will be less sensitive to radiation than in
`ease A and will be characterized by a larger holding
`current. Measurements made using the circuit elements
`wired as in case A maximize the likelihood of producing
`SCR action.
`If case A does not exhibit SCR behavior,
`case B most certainly will not.
`
`Hlectrical Measurements
`
`Parasitic Transistors
`
`The circuit topologies of the 4007 and hol permit
`direct measurement of the parasitic npn and pnp tran-
`sistor current gain. Hence, it is possible to calculate
`
`Tithe pt and nt channel-stop regions have not been show
`Since they do not enter in the latch-up paths to be
`discussed.
`
`293
`
`
`
`
`Dell Ex. 1026
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`
`

`

`the activity of. various potential SCR paths by measuring
`the current gain product for the path (i.e., SCR action
`can occur if he, (npn) * be, (pnp) >i). Current gains
`(hp.) for a variety of parasitic npn and pnp paths are
`given in Table I for both the 4007 and 4041.
`The gain
`values given correspond approximately to the peak ac
`gain for the indicated path.
`The gain values for the
`characteristic connections identified in the table are
`averaged over the different connections which yield
`similar device structures.
`
`Basic SCR Structures
`
`voltage drop across the chip. This occurs only when
`the input is high, as shown in Figure 7a.
`The holding
`current for this case is approximately 60 ma.
`If an
`external resistance (1k) is inserted in the Vpp line,
`but the input is supplied by a low impedance source
`No
`(7b),
`the SCR holding current is reduced to 28 ma.
`SCR action can be produced in the 4041 when the input
`is low,
`indicating that it is impossible to forward
`bias any portion of the p-transistor source diode due
`to lateral voltage drops. As will be shown in the next
`section, this is due to the layout of the p-transistor.
`
`Although our basic interest is in radiation-induced
`latch-up,
`the presence of SCR's on CMOS circuits can be
`observed more easily by simple electrical measurement.
`In the present work,
`the various possible SCR paths were
`studied using a Tektronix curve-tracer, with the base
`drive output providing gate current to trigger the SCR.
`Both self-triggering (no-gate current) and gate trigger-
`ing (at fixed anode-cathode voltages) have been studied.
`The two paths identified in Table II have been explored
`on the 4007 circuit.
`The self-triggering characteristics
`of both connections for the 4007 are shown in Figure 5.
`Typically,
`the holding current of Connection 2 (1.0 ma)
`is much greater than Connection 1 (300 WA) due to the
`lower gain (wider base) of the parasitic pnp for Connec-
`tion 2.
`
`Both Connection 1 and Connection 2 SCR's on the
`4007 could be triggered on by a small gate current.
`Approximately 5 pA and 50 WA were required at Gate 1,
`respectively, for these two connections (10V bias).
`
`The on-circuit wiring of the 4041 inverters pre-
`vented observation of the intrinsic SCR's formed by the
`pnp and npn transistor. However,
`the following section
`discusses SCR action which can occur in this unit due
`to lateral voltage drops caused by photocurrent during
`a radiation transient.
`
`SCR Action-Normal Bias Conditions
`
`latch-up can be observed for
`As discussed above,
`normal inverter bias conditions if the lateral voltage
`drops across ® and R,
`(Figure 4) produced by the p-well
`photocurrent are sufficient to forward bias the SCR
`gate junctions during a radiation transient. This be-
`havior can be simulated electrically by overvoltaging
`the potential SCR into breakdown to trigger SCR action.
`Figure 6 shows the SCR behavior exhibited by one in-
`verter on a 4007 circuit for two input conditions:
`(a) input high and (b)
`input low. For case (a)
`(pins
`14,6-V. p2 Pin 7-V,
`) the substrate current flows
`through R, and produces a lateral voltage drop which
`forward biases the ptn gate protection diode at pin 6.
`The current flowing laterally through the p-well pro-
`duces forward bias along a section of the n* source
`junction which allows the SCR to turn on.
`Since the
`measured substrate resistance between p-well and the
`Vpp terminal
`(on the 4007)
`is approximately 30-50 ohms,
`the holding current of 45 ma in Figure 6a is to be
`expected (I x R, = 45 ma x 30 ohms = 1.35 volts). When
`the input is low, as in 6b,
`the gate protection diode
`cannot become forward biased, hence, sufficient lateral
`voltage drop must exist under the p-channel source fin-
`gers to create a forward biased region. This can occur
`in the 4007 since the source fingers are parallel to
`the direction of current flow between V_,,
`and p-well.
`The holding current for this case is approximately 70 ma
`since a sufficient lateral voltage drop must be devel-
`oped under the source finger of the 4007, a relatively
`short distance,
`in order to forward bias these junctions.
`
`The only SCR exhibited by the 4041 when biased
`normally is that which occurs when the pt gate protec-
`tion diode becomes forward biased due to a lateral
`
`Radiation Studies
`
`Transient radiation studies have been performed on
`the above IC's at the Febetron 705 and Hermes II facil-
`ities at Sandia and at the Gulf Radiation Technology
`Linac. All the latch-up modes discussed above have
`been confirmed as being triggerable by a radiation pulse.
`For example,
`the SCR corresponding to Connection 1 on
`normal CDUOO7A circuits is triggered into latch-up at a
`dose rate of 1 x 108 rads/s (3 rads),
`from the Febetron
`705, when biased at 10 volts. Latch-up on the circuits
`biased normally did not occur until higher dose rates,
`3.x 10°
`rads/s (103 rads - Linac) for the 4007 and 3 x
`109 rads/s (90 rads ~ Febetron) for the 4041. However,
`all latch-up modes observed electrically could be stimu-
`lated by exposure to a dose of 2 x 1011 rads/s (104
`rads) from the Hermes II.
`A series of Febetron 705
`transient studies was performed on the CDJOO7A, using
`special circuits whose peak gain products (Connection 1)
`were less than.unity (0.07, 0.14, 0.15, 0.18) and
`slightly greater than unity (1.3). No latch-up was
`observed for gain products less than unity.
`The device
`whose gain product exceeded unity (1.3) did latch-up
`(holding current = 34 ma),
`in agreement with electri-
`cally-induced latch-up measurements on the same unit.
`
`Studies have been performed on a variety of other
`circuits (cD4009A, CDO]OA,
`cD4O20A, CDYO1IA-RCA) of
`varying complexity. Latch-up has been observed in the
`4007, 4009, 4010, 4011, and 4041.
`In the 4020, a typi-
`cal MSI complexity circuit, no latch-up is observed at
`i012 vads/s. This is undoubtedly related to the much
`smaller p-well areas for the individual inverters in
`the 4020, which results in reduced photocurrents and
`lateral voltage drops.
`
`Latch-up Prevention in CMOS
`
`Although the above studies demonstrate that latch-
`up is prevalent in CMOS circuits,
`there are several
`techniques which can be employed to eliminate it. These
`techniques can be grouped in three categories:
`(1) vari-
`ation in material parameters,
`(2) variation in circuit
`layout, and (3) variation in CMOS processing. These are
`discussed below.
`
`Variations in Material Parameters
`
`Lifetime. As shown above, SCR action occurs when
`the product of npn and pnp common emitter current gains
`exceeds unity.
`If this criteria is not met in the cir-
`cuit,
`the effects of any radiation pulse will die away
`soon after the pulse. Latch-up can thus be eliminated
`if the minority carrier lifetime in the CMOS circuit is
`reduced to the point where all possible gain (Hee) pro-
`ducts are less than unity. Figure 8 shows the SCR
`activity of the Connection 1 SCR on the 4007 cipenit
`for three values of substrate lifetime, 1 x 10-%s,
`2x 10-7s, and 1 x 10-7s. At the intermediate lifetime
`latch-up can bé induced, but it is characterized by a
`large holding current
`(> 10 ma).
`No latch-up is present
`at the lowest lifetime, even for very high injected
`gate current. This sequence illustrates that latch-up
`via this most susceptible path in the 4007 can be
`
`294
`
`
`
`
`Dell Ex. 1026
`
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`Dell Ex. 1026
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`
`

`

`eliminated by reducing the substrate lifetime to 1 x
`10-Ts, or lower. Transient radiation studies on the re-
`duced lifetime circuits confirmed the absence of latch-
`up in these units, even at dose levels near 1012 rads/s.
`Since CMOS characteristics are not strongly influenced
`by minority carrier lifetime,
`the transfer character-
`istics of the circuit are essentially identical for all
`three cases in Figure 3. These results demonstrate
`that latch-up can be eliminated in CMOS circuits by
`control of lifetime.
`
`3. Use isoplanar, polyplanar, or some other oxide
`isolation technique, around the p-wells in parti-
`cular, to eliminate parasitic transistor action.
`
`h. Fabricate the structures on SOS or dielectrically
`isolated substrates to eliminate parasitic tran-
`sistor structures.
`
`Lateh-up would probably be eliminated by step number 1
`and would most certainly be eliminated by steps 2-4.
`
`Variations in Circuit Layout
`
`Conclusions
`
`Several guidelines can be formulated for CMOS lay-
`out which will greatly reduce the sensitivity of CMOS
`circuits to latch-up, possibly eliminating it all to-
`gether. These guidelines are:
`
`1.
`
`Employ minimum area p-wells. This minimizes the
`p-well photocurrent during a transient radiation
`pulse.
`
`2. Position the Vpp terminal for the circuit physically
`close to the input-protection-arrays and any large
`p-wells present, or, provide a low resistance sub-
`strate path between these regions.
`
`3. Place the source fingers of the p-transistors such
`that they lie along equipotential lines when current
`flows between V..,
`and the p-wells (e.g., photo-
`current). This means that the source fingers should
`be perpendicular to the dominant direction of cur-
`rent flow, rather than parallel. This effect is
`observed in the comparison of latch-up through the
`p-transistor source for the 4007 and 4041.
`The
`source fingers of the 4007 are parallel to the
`direction of photocurrent flow; hence, @ significant
`lateral drop can oceur under a source finger causing
`it to become forward biased.
`The source fingers of
`the 4041 are perpendicular to the current flow and
`no latch-up through the p-transistor source diodes
`can be observed.
`
`4,
`
`Short the p-transistor source finger to the substrate
`with metallization along its entire length.
`Short
`the n-transistor source to the p~well with metalli-
`zation along its entire length. This effectively
`prevents either of these diodes from ever becoming
`forward biased, hence eliminates their participation
`in latch-up.
`
`5. Qperate CMOS gates from relatively high impedance
`or low capacity supplies. This reduces the gate
`current which can flow and can prevent latch-up
`through the protection array.
`
`Variations in CMOS Processing
`
`junction-isolated
`If major changes in the standard,
`CMOS processing are allowable, several changes can be
`made which could individually eliminate the problem of
`latch-up.
`These processing changes are indicated below:
`
`1. Use epitaxial silicon with an n+ buried layer for
`the CMOS starting material. This greatly reduces
`the lateral voltage drops when photocurrent flows
`and also reduces the gain of the parasitic pnp
`transistors.
`To implement this change, relatively
`shallow p-wells are required.
`
`2.
`
`Perform an n+ deep isolation diffusion around the
`p-wells to connect with the n+ buried layer. This
`reduces the parasitic pnp gains to virtually zero
`and eliminates all active four-layer paths.
`
`295
`
`Latch-up has been produced in a variety of CMOS
`circuits both by electrical and radiation triggering.
`The most susceptible pnpn path has been identified and
`explored, on several circuits, to provide a worst-case
`measure of the sensitivity of each circuit. Latch-up
`has also been studied for normal inverter bias condi-
`tions.
`In this case the p-well photocurrent produced
`by a radiation transient can create lateral voltage
`drops in the substrate and p-well which forward biases
`regions of the p- and n-transistor source diodes to
`ereate an active SCR. Several suggestions have been
`made regarding variations in material parameters,
`variations in circuit layout, and finally, variations
`in CMOS processing which can eliminate the latch-up
`mechanism as a serious radiation threat to CMOS inte-
`grated circuits.
`
`References
`
`1.
`
`J. F. Leavy and R. A. Poll, "Radiation-Induced
`Integrated Cireuit Latch-up," IEEE Trans. Nuc.
`Sci., NS-16, p. 96, December 1969.
`
`2. W. J. Dennehy, A. G. Holmes-Siedle, and W. F.
`Leopold, "Transient Radiation Response of Comple-
`mentary-Symmetry MOS Integrated Circuits,” IEEE
`Trans. Nuc. Sei., NS-16, p. 114, December 1969.
`
`Table I
`Typical Common Emitter Current Gains for
`the Parasitic npn and pnp Transistors on
`the RCA CDHOO7A and CD4O41A.
`mnitter
`Connection
`
`1,2,4,5,8,9,11,12
`
`3,6,10,4,9,5,8
`6
`3,10
`21
`1,2,4,5,8,9,11,12
`3,6,10,13
`
`Table II
`Pin Connectiona for Typical pnpn Paths on the 4007
`Pin Numbers
`oatoae
`Circuit
`4007
`4007
`
`Connection 2
`
`Connection 1
`
`
`
`
`Dell Ex. 1026
`
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`

`

`
`
`FIELD OXIDE—-GATE (p) GATE (n) GATE PROTECTION DIODES
`
`
`
`
`
`Wj
`
`
`/ae
`n-TYPE SUBSTRATE
`
`
`
`Figure 1. Cross-sectional View of a Typical CMOS Inverter Structure.
`
`TERMINAL NO. 14 = V
`TERMINAL NO. 7
`= V
`
`14
`
`
`gate input
`protection
`
`
`
`p-well (n-channel transistors)
`
`Figure 2. Layout and Schematic for the RCA CD4O07A CMOS Integrated Circuit.
`
`296
`
`
`
`
`Dell Ex. 1026
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`

`

`p-well (n-channel transistors)
`
`gate input
`protection
`
`\NPUT
`
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`Yoo
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`Yss
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`a-
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`+—————© ComPLEMENT ’
`
`Figure 3. Layout and Schematic of the RCA CD4041A CMOS IC.
`
`ANODE
`
`ee
`
`
`
`
`GATE |
`P-Well (7)
`
`GATE 2
`Substrate (14)
`
`N-Source(4)
`
`CATHODE
`-
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`Vv,
`
`DD
`
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`Diode
`
`Substrate
`
`P-Well
`
`N-Source
`
`Rp
`
`Vogl?)
`b
`
`Figure 4,
`
`Equivalent Circuits for the SCR Structures Present on
`4007 for a) Worst-Case Bias and b) Normal Inverter Bias --
`Input High.
`
`297
`
`
`
`
`Dell Ex. 1026
`
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`

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