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`5.5 Power, Energy, and Energy Delay
`
`217
`
`Example 5.12 Switching Activity
`
`Consider the waveforms in Figure 5.27, where the upper waveform represents the ideal(cid:173)
`ized clock signal, and the bottom one shows the signal at the output of the gate. Power
`consuming transitions occur 2 out of 8 times, which is equivalent to a transition probabil(cid:173)
`ity of0.25 (or25%).
`
`Clock
`
`JlJLJLJULJlj_JL
`Output signal J
`LJ
`
`Figure 5-27 Clock and signal waveforms.
`
`: Low Energr-Power Dcsig11 Techniques
`
`-
`
`:
`
`:
`
`-
`
`__
`
`\Vith the increasing complexity of digital integrated circuits, it is anticipated that the power problem will
`only worsen in future technologies. This is one of the reasons that lower supply voltages are becoming
`more and more attractive. Reducing V0 n has a quadratic effect on Pd_~n· For instance, reducing VDD from
`2.5 V to 1.25 V for our example drops the power dissipation from 5 Vi.1 to 1.25 W. This assumes that the
`same clock rate can be sustained. Figure 5-17 demonstrates that this assumption is not that unrealistic as
`long as the supply voltage is substantially higher than the threshold voltage. A large performance penalty
`occurs once V DD approaches. 2 VT·
`'When a lower limit on the supply voltage is set by external constraints (as often happens in real(cid:173)
`world designs), or when the performance degradation due to lowering the supply voltage is intolerable, the
`only means of reducing the dissipation is by lowering the effective capacitance. This can he achieved by
`addressing both of its components: the physical capacitance and the switching activity.
`A reduction in the switching activiry can only be accomplished at the logic and architectural abstrac(cid:173)
`tion levels, and will be discussed in more detail in Chapter 11. Lowering the physical capacitance is a worth(cid:173)
`while goal overall, and it also may help to improve the performance of the circuit. As most of the capacitance
`in a combinational logic circuit is due to transistor capacitances (gate and diffusion), it makes sense to keep
`those contributions to a minimum when designing for low power. This means that transistors should be kept
`to minimal size whenever possible or reasonable. This definitely affects the performance of the circuit, but the
`effect can be offset by using 1ogic or architectural speedup techniques< The only instances where transistors
`should be sized up is when the load capacitance is dominated by extrinsic capacitances (such as fan-out or
`wiring capacitance). This is contrary to common design practices used in cell libraries, where transistors are
`generally made large to accommodate a range ofloading and performance requirements.
`These observations lead to an interesting design challenge. Assume we have to minimize the energy
`dissipation of a circuit with a specified lower bound on the perfonnance. An attractive approach is to lower
`the supply voltage as much as possible, and to compensate the loss in performance by increasing the transistor
`sizes. Yet, the latter causes the capacitance to increase. It may be foreseen that at a low enough supply voltage.
`the latter factor may start to dominate and cause energy to increase with a further drop in the supply voltage.
`Ill
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`232
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`Chapter 5 • The CMOS Inverter
`
`140
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`120
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`100
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`80
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`40
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`20
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`0 " 60
`
`,;;-
`6
`>,
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`(l
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`·stage delay
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`""'">
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`Gate delay ~--"
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`·-" ·-
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`Wire delay
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`"'-•~ • "•
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`0
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`I
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`180 150130 100 70 50
`250
`Technology Min. Feature (nm)
`Figure 5-41 Evolution of wire delay-to-gate delay ratio with respect
`to technology (from [Fisher98]).
`
`5.7 Summary
`This chapter presented a rigorous and in-depth analysis of the static CMOS inverter. The key
`characteristics of the gate are summarized as follows:
`
`• The static CMOS inverter combines a pull-up PMOS section with a pull-down NMOS
`device. The PMOS is normally made wider than the NMOS due to its lower current(cid:173)
`driving capabilities.
`• The gate has an almost ideal voltage-transfer characteristic. The logic swing is equal to the
`supply voltage and is not a function of the transistor sizes. The noise margins of a symmet(cid:173)
`rical inverter (where PMOS and NMOS transistor have equal current-driving strength)
`approach V vvl2. The steady-state response is not affected by fan-out.
`• Its propagation delay is dominated by the time it takes to charge or discharge the load
`capacitor CL. To a first order, it can be approximated as follows:
`
`tp = 0.69CL
`(
`
`)
`R +R
`eqn 2 eqp
`
`Keeping the load capacitance small is the most effective means of implementing high-per(cid:173)
`formance circuits. Transistor sizing may help to improve performance as long as the delay
`is dominated by the extrinsic (or load) capacitance of fan-out and wiring.
`• The power dissipation is dominated by the dynamic power consumed in charging and dis(cid:173)
`charging the load capacitor. It is given by P 0 _, 1 CLVv/f The dissipation is proportional to
`the activity in the network. The dissipation due to the direct-path currents occurring during
`switching can be limited by careful tailoring of the signal slopes. The static dissipation
`usually can be ignored, but might become a major factor in the future as a result of sub(cid:173)
`threshold currents.
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`5.8 To Probe Further
`
`233
`
`• Scaling the technology is an effective means of reducing the area, propagation delay and
`power consumption of a gate. The impact is even more striking if the supply voltage is
`scaled simultaneously.
`• The interconnect component is gradually taking a larger fraction of the delay and perfor(cid:173)
`mance budget.
`
`5.8 To Probe Further
`The operation of the CMOS inverter has been the topic of numerous publications and textbooks.
`Virtually every book on digital design devotes a substantial number of pages to the analysis of
`the basic inverter gate. An extensive list of references \Vas presented in Chapter 1. Some refer(cid:173)
`ences of particular interest that we quoted in this chapter follow.
`
`References
`[Dally98] W. Dally and J. Poulton, Digital Sysrems Engineering, Cambridge University Press, 1998.
`[Fisher9-8J P. D. Fisher and R. Nesbitt, "The Test of Time: Clock-Cycle Estimation and Test Challenges for Future
`Microprocessors," IEEE Circuits and Devices Magazine, 14(2), pp. 37-44, 1998.
`[Hedenstierna87] N. He<lenstierna and K. Jeppson, "CMOS Circuit Speed and Buffer Optimization," IEEE Transactions
`011 CAD, vol. CAD-6, no. 2, pp. 270-281, March 1987.
`[Kuroda95] T. Kuroda and T. Sakurai, "Overview of low-power ULSI circuit techniques," JEJCETrans. 011 Electronics,
`vo!. E78-C, no. 4, pp. 334-344, Apri1 1995.
`[Uu93] D. Llu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE Jour-
`nal ofSolid-Sratc Circuits, vol. 28, no.l, pp.10-17, Jan.1993, p.I0-17.
`[Mead80J C. Mead and L. Conway, Introduction Jo VLSI Systems, Addison-Wesley, 1980.
`[Sedrn.87] A. Sedra and K. Smith, MicmE!ectmnic Circuits, Holt, Rinehart and Winston, 1987.
`[Swnnson72] R. Swanson and J. Meindl, "Ion-Implanted Complementury CMOS transistors in Low-Voltage Circuits,"
`IEEE Jounwl of Solid-State Circuits, vol. SC-7, no. 2, pp.146-152, April 1972.
`[Sylvester98l D. Sylvester and K. Kemzer, "Getting to the Bottom of Deep Submicron," Proceedings JCCAD Confer(cid:173)
`ence, pp. 203, San Jose, November 199-8.
`[Veendrick84] H. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and its 1mpact on the Design of
`Buffer Circuits," IEEE Journal of Solid-Stare Circuits, voL SC-19, no. 4, pp. 468-473, I984.
`
`Exercises and Design Problems
`REl\UNDER: Please refer to http~//bwrc.eecs.berkeley.edu/IcBook for up-to-date problem sets, design problems, and
`exercises. By making the exercises electronically available instead of ln print, we can provide a dynamic environment
`that tracks the rapid evolution of today's digital integrated circuit design technology.
`
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`CHAPTER
`6
`
`Designing Combinational Logic
`Gates in CMOS
`
`111-deptl! discussion of logic families in CMOS-
`static and dynamic, pass~transistor, 1zonratwed alld ratioed logic
`
`Optimizi.ng a logic gate for area, speed, energy, or robustness
`
`Low-power and l!igh-performallce circuit-desig11 tech11iques
`
`6.1
`6.2
`
`Introduction
`Static CMOS Design
`6.2.1 Complementary CMOS
`6.2.2 Ratioed Logic
`6.2.3 Pass-Transistor Logic
`6.3 Dynamic CMOS Design
`6.3.1 Dynamic Logic: Basic Principles
`6.3.2 Speed and Power Dissipation of Dynamic Logic
`6.3.3 Signal Integrity Issues in Dynamic Design
`6.3.4 Cascading Dynamic Gates
`Perspectives
`6.4.1 How to Choose a Logic Style?
`6.4.2 Designing Logic for Reduced Supply Voltages
`Summary
`To Probe Further
`
`6.4
`
`6.5
`6.6
`
`235
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`260
`
`Chapter 6 • Designing Combinational Logic Gates in CMOS
`
`probabilities that we presented previously fails under these circumstances. Traversing from
`inputs to outputs yields a transition probability of 3/16 for node Z, similar to the previous analy(cid:173)
`sis. This value clearly is false, as logic transfmmations show that the network can be reduced to
`Z = C · B = A · A = 0, and thus no transition will ever take place.
`To get the precise results in the progressive analysis approach, its is essential to take signal
`interdependencies into account. This can be accomplished with the aid of conditional probabili(cid:173)
`ties. For an AND gate, Z equals 1 if and only if B and C are equal to 1. Thus,
`
`Pz = p(Z = 1) = p(B = 1, C = 1)
`
`(6.25)
`
`where p(B = 1, C = 1) represents the probability that Band Care equal to 1 simultaneously. If B
`and Care independent, p(B = 1, C = l) can be decomposed into p(B = 1) · p(C = l), and this
`yields the expression for the AND gate derived earlier: pz = p(B = 1) · p(C = 1) = p 8 Pc· If a
`dependency between the two exists (as is the case in Figure 6-2lb), a conditional probability has
`to be employed, such as the following:
`
`Pz=p(C= JIB= 1) ·p(B= l)
`
`(6.26)
`
`The first factor in Eq. (6.26) represents the probability that C = 1 given that B = 1. The
`extra condition is necessary because C is dependent upon B. Inspection of the network shows
`that this probability is equal to 0, since C and B are logical inversions of each other, resulting in
`the signal probability for Z, /Jz = 0.
`Deriving those expressions in a structured way for large networks with reconvergent fan(cid:173)
`out is complex, especially when the networks contain feedback loops. Computer support is
`therefore essential. To be meaningful, the analysis program has to process a typical sequence of
`input signals, because the power dissipation is a strong function of statistics of those signals.
`
`Dynamic or Glitching Transitions When analyzing the transition probabilities of complex,
`multistage logic networks in the preceding section, we ignored the fact that the gates have a non(cid:173)
`zero propagation delay. In reality, the finite propagation delay from one logic block to the next
`can cause spurious transitions kno\VIl as glitches or dynamic hazards to occur: a node can exhibit
`multiple transitions in a single clock cycle before settling to the correct logic level.
`A typical example of the effect of glitching is shown in Figure 6-22, which displays the
`simulated response of a chain of NAND gates for all inputs going simultaneously from O to 1.
`Initially, all the outputs are I since one of the inputs was 0. For this particular transition, all the
`odd bits must transition to 0, while the even hits remain at the value of L However, due to the
`finite propagation delay, the even output bits at the higher bit positions start to discharge, and the
`voltage drops. When the correct input ripples through the network, the output goes high. The
`glitch on the even bits causes extra power dissipation beyond what is required to strictly imple(cid:173)
`ment the logic function. Although the glitches in this example are on]y partial (i.e., not from rail
`to rail), they contribute significantly to the power dissipation. Long chains of gates often occur
`in important structures such as adders and multipliers, and the glitching component can easily
`dominate the overall power consumption.
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`270
`
`
`Chapter 6 • Designing
`
`Combinational Logic Gates In CMOS
`
`Unfottunalely, as discussed earlier, an NMOS device is effective at passing a 0, but it is
`
`
`
`
`
`
`pulls a node high, the output
`only
`a node to V00. When the pass-transistor
`poor at pulling
`
`charges up to V DD -V rn-In fact,
`
`
`
`the situation is worsened by the fact that the devices experience
`
`
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`high. Consider body effect, because a significant source-to -body voltage is present when pulling
`
`
`
`
`
`set the case in which the pass-transistor is charging up a node with the gate and drain terminals
`
`
`
`
`up to be labeled x. The node x will charge at V00. Let the source of the NMOS pass-transistor
`V0 0-Vrn<Vx). We obtain
`
`(6.30)
`
`
`
`Example 6.9 Voltage Swing for Pass-Transistors Circuits
`
`
`
`
`
`The transient response of Figure 6-34 shows an NMOS charging up a capacitor. The
`
`
`
`
`
`of the NMOS is at V DD• and its gate voltage is being ramped from O V
`
`drain voltage
`to V DD
`
`
`
`· Assume that node x is initially at O V. We observe that the output initially
`
`
`
`
`charges up quickly, but the tail end of the transient is slow. The current drive of the
`
`
`
`
`(gate-to-source voltage) is reduced significantly as the output approaches
`transistor
`Man­
`
`to charg e up node x is reduced drastically.
`VDD -Vn,, and the current available
`
`
`
`
`
`ual calculation using Eq. (6.30) results in an output voltage of 1.8 V, which is close
`
`to the simulated value.
`
`3.0
`
`IN
`J_
`
`25µ,m
`V �
`DD
`2.0
`Out
`0.5 µ.m/0.25 µm
`
`> �
`0.5 µ.m/0.25 µ,m
`�
`�
`
`1.0
`
`In
`
`X
`
`0.0
`0 0.5
`
`Time,ns
`
`1.5 2
`
`Figure 6-34 Transient response of charging up a node using an N device. Notice the
`
`
`
`
`
`
`
`
`
`slow tail after an initial quick response. V00 = 2.5 V.
`
`WARNING: The preceding example demonstrates that pass-transistor
`
`
`
`gates cannot be cas-,
`
`
`cadcd by connecting the output of a pass gate to the gate input of another pass-transistor.
`of M1 (node x) drives the gate of another
`
`
`
`
`This is illustrated in Figure 6-35a, where the output
`
`
`up to V00 -Vrni· If node Chas a rail-to-rail swing, node Yonly
`
`MOS device. Node x can charge
`
`
`charges up to the voltage on node x-VTnl• which works out to V00 -Vr,,1 -Vr,,2. Figure
`6-35b,
`
`on the other hand, has the output of M1 (x) driving
`
`the junction of M2, and there is only one
`
`
`
`threshold drop. This is the proper way of cascading pass gates.
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`6.3 Dynamic CMOS Design
`
`289
`
`1t would appear that dynamic logic presents a significant advantage from a power perspec(cid:173)
`tive. There are three reasons for this. First, the physical capacitance is lower since dynamic logic
`uses fewer transistors to implement a given function. Also, the load seen for each fan-out ls one
`transistor instead of two. Second, dynamic logic gates by construction can have at most one tran(cid:173)
`sition per clock cycle. Glitching (or dynamic hazards) does not occur in dynamic logic. Finally,
`dynamic gates do not exhibit short-circuit power since the pull-up path is not turned on when the
`gate is evaluating.
`While these arguments generally are true, they are offset by other considerations: (1) the
`clock power of dynamic logic can be significant, particularly since the clock node has a guar(cid:173)
`anteed transition on every sing]e clock cycle; (2) the number of u-ansistors is greater than the
`minimal set required for implementing the logic; (3) short-circuit power may exist when leak(cid:173)
`age-combatting devices are added (as will be discussed further); and (4), most importantly,
`dynamic logic generally displays a higher switching activity due to the pe,iodic prec/zarge and
`discharge operations. Earlier, the transition probability for a static gate was shown to be p0 p 1 =
`p 0 (I - p 0 ). For dynamic logic, the output transition probability does not depend on the state
`(history) of the inputs, but rather on the signal probabilities. For an n-tree dynamic gate, the
`output makes a O -; 1 transition during the precharge phase only if the output was discharged
`during the preceding evaluate phase. Hence, the O -; l transition probability for an ,I-type
`dynamic gate is given by
`
`ao-71=Po
`
`(6.41)
`
`where Po is the probability that the output is zero. This number is always greater than or equal to
`p 0 p 1. For uniformly distributed inputs, the transition probability for an N-input gate is
`
`No
`ao-1 = N
`2
`
`(6.42)
`
`where N 0 is the number of zero entries in the truth table of the logic function.
`
`Example 6.16 Activity Estimation in Dynamic Logic
`
`To iBustrate the increased activity for a dynamic gate, consider again a two-input NOR
`gate. An n-tree dynamic implementation is shown in Figure 6-55. along with its static
`counterpart. For equally probable inputs, there is a 75% probability that the output node of
`the dynamic gate discharges immediately after the precharge phase, implying that the
`activity for such a gate equals 0.75 (i.e., PNoR = 0.75 CLV&7fc1;). The c01Tesponding activ(cid:173)
`ity is a lot smaller, 3/16, for a static implementation. For a dynamic NANO gate, the tran(cid:173)
`sition probability is 1/4 (since there is a 25% probability the output will be discharged)
`while it is 3/16 for a static implementation. Although these examples illustrate that the
`switching activity of dynamic logic is generally higher, it should be noted that dynamic
`logic has lower physical capacitance. Both factors must be accounted for when analyzing
`dynamic power dissipation.
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`6.3 Dynamic CMOS Design
`
`295
`
`to V DD during precharge, charge sharing does not occur. This solution obviously comes at the
`cost of increased area and capacitance.
`
`Capacitive Coupling
`The relatively high impedance of the output node makes the circuit very sensitive to crosstalk
`effects. A wire routed over or next to a dynamic node may couple capacitively and destroy the
`state of the floating node. Another equally important fonn of capacitive coupling is backgate (or
`output-to-input) coupling. Consider the circuit shown in Figure 6-62a, in which a dynamic two(cid:173)
`input NANO gate drives a static NANO gate. A transition in the input In of the static gate may
`cause the output of the gate (Out2) to go low. This output transition couples capacitively to the
`other input of the gate (the dynamic node 0111 1) through the gate-source and gate-drain capaci(cid:173)
`tances of transistor M4 • A simulation of this effect is shown in Figure 6-62b. It demonstrates how
`the coupling causes the output of the dynamic gate Out1 to drop significantly. This further causes
`the output of the static NANO gate not to drop all the way down to O V and a small amount of
`static power to be dissipated. If the voltage drop is large enough, the circuit can evaluate incor(cid:173)
`rectly, and the NAND output may not go low. When designing and laying out dynamic circuits,
`special care is needed to minimize capacitive coupling.
`
`Clock Feedthrough
`A special case of capacitive coupling is clock feedthrough, an effect caused by the capacitive
`coupling between the clock input of the precharge device and the dynamic output node. The cou(cid:173)
`pling capacitance consists of the gate-to-drain capacitance of the precharge device, and includes
`both the overlap and channel capacitances. This capacitive coupling causes the output of the
`dynamic node to rise above V DD on the low-to-high transition of the clock, assuming that the
`pull-down network is turned off. Subsequently, the fast rising and falling edges of the clock cou(cid:173)
`ple onto the signal node, as is quite apparent in the simulation of Figure 6-62b.
`The danger of clock feedthrough is that it may cause the normally reverse-biased junction
`diodes of the precharge transistor to become forward biased. This causes electron injection into
`the substrate, which can be collected by a nearby high-impedance node in the 1 state, eventually
`resulting in faulty operation. CMOS latchup might be another result of this injection. For all pur(cid:173)
`poses, high-speed dynamic circuits should be carefully simulated to ensure that clock
`feedthrough effects stay within bounds.
`All of the preceding considerations demonstrate that the design of dynamic circuits is
`rather tricky and requires extreme care. It should therefore be attempted only when high perfor(cid:173)
`mance is required, or high quality design-automation tools are available.
`
`6.3,4 Cascading Dynamic Gates
`Besides the signal integrity issues, there is one major catch that complicates the design of
`dynamic circuits: Straightforward cascading of dynamic gates to create multilevel logic struc(cid:173)
`tures does not work. The problem is best illustrated with two cascaded n-type dynamic
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`6.4 Perspectives
`
`303
`
`precharge phase (CLK = 0), the output of then-tree gate, Out1, is charged to VDD• while the
`output of the p-tree gate, Out,, is predischarged to O V. Since the n-tree gate connects PMOS
`pull-up devices, the PUN of the p-tree is turned off at that time. During evaluation, the output of
`then-tree gate can only make a 1 ----t O transition. conditionally turning on some transistors in the
`p-tree. This ensures that no accidental discharge of Out2 can occur. Similarly, n-tree blocks can
`follow p-tree gates without any problems, because the inputs to then-gate are precharged to 0. A
`disadvantage of the np-CMOS logic style is that the p-tree blocks are slower than the ll-tree
`modules, due to the lower current drive of the PMOS transistors in the logic network. Equalizing
`the propagation delays requires extra area. Also, the lack of buffers requires that dynamic nodes
`are routed between gates.
`
`6.4 Perspectives
`
`6.4.1 How to Choose a Logic Style?
`In the preceding sections, we have discussed several gate-implementation approaches using the
`CMOS technology. Each of the circuit styles has its advantages and disadvantages. Which one to
`select depends upon the primary requirement: ease of design, robustness, area, speed, or power
`dissipation. No single style optimizes alt these measures at the same time. Even more, the
`approach of choice may vary from logic function to logic function.
`The static approach has the advantage of being robust in the presence of noise. This makes
`the design process rather trouble free and amenable to a high degree of automation. It is clearly
`the best general-purpose logic design style. This ease of design does come at a cost: For complex
`gates with a large fan-in, complementary CMOS becomes expensive in terms of area and perfor(cid:173)
`mance. Alternative static logic styles have therefore been devised. Pseudo-NM OS is simple and
`fast at the expense of a reduced noise margin and static power dissipation. Pass-transistor logic
`is attractive for the implementation of a number of specific circuits, such as multiplexers and
`XOR-dominated logic like adders.
`Dynamic logic, on the other hand, makes it possible to implement fast and small complex
`gates. This comes at a price, however. Parasitic effects such as charge sharing make the design
`process a precarious job. Charge leakage forces a periodic refresh, which puts a lower bound on
`the operating frequency of the circuit.
`The current trend is towards an increased use of complementmy static CMOS. This ten(cid:173)
`dency is inspired by the increased use of design-automation tools at the logic design level. These
`tools emphasize optimization at the logic level, rather than at the circuit level, and they put a pre(cid:173)
`mium on robustness. Another argument is that static CMOS is more amenable to voltage scaling
`than some of the other approaches discussed in this chapter.
`
`6.4.2 Designing Logic for Reduced Supply Voltages
`In Chapter 3, we projected that the supply voltage for CMOS processes will continue to drop
`over the coming decade. and may go as low as 0.6 V by 2010. To maintain performance under
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`6.4 Perspectives
`
`305
`
`dynamic control of the threshold vo1tage of a device by exploiting the body effect of the transistor.
`Use of this approach to control individual devices requires a dual-well process (see Figure 2-2).
`Clever circuit design can also help reduce the leakage current, \vhich is a function of the
`circuit topology and the value of the inputs applied to the gate. Since VT depends on body bias
`<Vnsl, the subthreshold leakage of an MOS transistor depends not only on the gate drive (Vcsl.
`but also on the body bias. In an inverter with In = 0, the subthreshold leakage of the inverter is
`set by the NMOS transistor with its Vcs = Vns = 0 V. In more complex CMOS gates, such as the
`two-input NANO gate of Figure 6-72, the leakage current depends on tl1e input vector. The sub(cid:173)
`threshold leakage current of this gate is the least when A = B = 0. Under these conditions, the
`intermediate node X settles to
`
`Vx=V,1,ln(l +n)
`
`(6.47)
`
`The leakage cun-ent of the gate is then determined by the topmost NMOS transistor with V cs=
`V8s = -Vx- Clearly, the subthreshold leakage under this condition is smaller than that of the
`inverter. This reduction due to stacked transistors is called the stack effect. The Table in
`Figure 6-72 analyzes the leakage components for the two-input NANO gate under different
`input conditions.
`The reality is even better. In short-channel MOS transistors, the subthreshold leakage cur(cid:173)
`rent depends not only on the gate drive (V cs) and the body bias ( V85 ), but also on the drain volt(cid:173)
`age (Vos). The threshold voltage of a short-channel iviOS transistor decreases with increasing
`VDs due to drain-induced barrier lowering (DIBL). Typical values for DIBL can range from a
`20- to a 150-m V change in V r per voltage change in V DS· Because of this, the impact of the stack
`effect is even more signHicant for short-channel transistors. The intermediate vo)tage reduces the
`drain-source voltage of the topmost device, increases its threshold, and thus lowers its leakage.
`
`Example 6.19 Stack Effect in Two-Input NAND Gate
`Consider again the two-input NAND gate of Figure 6-72a, when both N 1and N2 are off
`(A = B = 0). From the simulated load lines shown in Figure 6-72c, we see that Vx settles to
`approximately 100 mV in steady state. The steady-state subthreshold leakage in the gate is
`therefore due to Vcs= V8s = -IOO mV and VDs = VDD- 100 mV, which is 20 times smaller
`than the leakage of a stand-alone NMOS transistor with Vcs= V85 = 0 mV and VDs = VDo
`[Ye98].
`
`In sum, the subthreshold leakage in complex stacked circuits can be significantly lower
`than in individual devices. Observe that the maximum leakage reduction occurs when all the
`transistors in the stack are off, and the intermediate node voltage reaches its stea.dy-state value.
`Exploiting this effect requires a careful selection of the input signals to every gate during
`standby or sleep mode.
`
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`

`

`6.6 To Probe Further
`
`307
`
`• The performance of a CMOS gate is a strong function of the fan-in. Techniques to deal
`with fan-in include transistor sizing, input reordering, and partitioning. The speed is also a
`linear function of the fan-out. Extra buffering is needed for large fan-outs.
`• The ratioed logic style consists of an active pull-down (-up) network connected to a load
`device. This results in a substantial reduction in gate complexity at the expense of static
`power consumption and an asymmetrical response. Careful transistor sizing is necessary
`to maintain sufficient noise margins. The most popular approaches in this class are the
`pseudo-NMOS techniques and differential DCVSL, which require complementary
`signals.
`• Pass-transistor logic implements a logic gate as a simple switch network. This results in
`very simple implementations for some logic functions. Long cascades of switches are to
`be avoided due to a quadratic increase in delay with respect to the number of elements in
`the chain. NMOS-only pass-u·ansistor logic produces even simpler structures. but might
`suffer from static power consumption and reduced noise margins. This problem can be
`addressed by adding a level-restoring transistor.
`• The operation of dynamic logic is based on the storage of charge on a capacitive node and
`the conditional discharging of that node as a function of the inputs. This calls for a two(cid:173)
`phase scheme, consisting of a precharge foHowed by an evaluation step. Dynamic logic
`trades off noise margin for performance. It is sensitive to parasitic effects such as 1eakage,
`charge redistribution, and clock feedthrough. Cascading dynamic gates can cause prob(cid:173)
`lems and thus should be addressed carefully.
`• The power consumption of a logic network is strongly related to the switching activity of
`the network. This activity is a function of the input statistics, the network topology, and the
`1ogic style. Sources of power consumption such as glitches and short-circuit currents can
`be minimized by careful circuit design and transistor sizing.
`• Threshold voltage sca1ing is required for low-voltage operation. Leakage control is critica1
`for low-voltage operation.
`
`6.6 To Probe Further
`The topic of (C)MOS logic styles is treated extensively in the literature. Numerous texts have
`been devoted to the issue. Some of the most comprehensive treatments can be found in
`[Weste93] and [ChandrakasanOl]. Regarding the intricacies of high-performance design,
`[Shoji96] and [Bernstein98] offer the most in-depth discussion of the optimization and analysis
`of digital MOS circuits. The topic of power minimization is relatively new, but comprehensive
`reference works are available in [Chandrakasan95], [Rabaey95], and [Pedram02].
`Innovations in the MOS logic area are typically published in the proceedings of the !SSCC
`Conference and the VLSI circuits symposium, as well as the IEEE Journal of Solid State
`Circuits (especially the November issue).
`
`Dell Ex. 1025
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`

`308
`
`Chapter 6 • Designing Combinational Logic Gates in CMOS
`
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`1995.
`[ClmndrakusanOJ]A. C-handrakasan, W. Bowhill, and F. Fox, ed., Design of High-Performance Microprocessor Circuits,
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`[Gon,;alvez831 N. Gorn;a!vez and H. De Man, "NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic
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`[Pedmm02] M. Pedrnm and J. Rabaey. ed., Power-Aware Design Methodologies, KlU'Jt"ef, 2002.
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