`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR PRODUCTS,
`INC., and MICRON TECHNOLOGY TEXAS LLC
`
`Petitioners,
`
`v.
`
`NETLIST, INC.,
`
`Patent Owner.
`
`
`Patent No. 11,016,918
`
`Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, and Jayesh Bhakta
`
`TITLE: Flash-DRAM Hybrid Memory Module
`
`
`Inter Partes Review No. IPR2023-00406
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 11,016,918
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`TABLE OF CONTENTS
`
`I.
`
`PETITIONERS’ MANDATORY NOTICES .............................................. 1
`A.
`Real Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) ................................... 1
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 1
`C.
`Counsel (37 C.F.R. § 42.8(b)(3)) ........................................................... 2
`D.
`Service Information (37 C.F.R. § 42.8(b)(4)) ........................................ 2
`INTRODUCTION ......................................................................................... 3
`II.
`III. COMPLIANCE WITH REQUIREMENTS FOR A PETITION FOR
`INTER PARTES REVIEW .......................................................................... 3
`A.
`Standing (§42.104(a)) ............................................................................ 3
`B.
`Identification of Challenge (§42.104(b)) ............................................... 3
`IV. RELEVANT INFORMATION CONCERNING THE CONTESTED
`PATENT ......................................................................................................... 4
`A.
`Effective Filing Date of the 918 Patent ................................................. 4
`B.
`The 918 Patent ....................................................................................... 5
`1.
`Technical Overview .................................................................... 5
`2.
`Prosecution History ..................................................................... 7
`Person of Ordinary Skill in the Art (“POSITA”) ................................... 7
`C.
`Construction of Terms Used in the Claims ........................................... 8
`D.
`V. OVERVIEW OF THE PRIOR ART ............................................................ 9
`A. Harris (EX1023) .................................................................................... 9
`B.
`FBDIMM Standards (EX1027-28) ...................................................... 10
`C.
`Amidi (EX1024) .................................................................................. 11
`D. Hajeck (EX1038) ................................................................................. 12
`E.
`Spiers (EX1025) .................................................................................. 13
`VI. ARGUMENT ................................................................................................ 14
`A. Ground 1 .............................................................................................. 14
`1.
`Ground 1 combination: Harris (EX1023) + FBDIMM Standards
`(EX1027-28) ............................................................................. 14
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`B.
`
`Independent Claim 1 ................................................................. 19
`2.
`Claim 2 ...................................................................................... 34
`3.
`Claim 3 ...................................................................................... 39
`4.
`Claim 8 ...................................................................................... 40
`5.
`Claim 14 .................................................................................... 45
`6.
`Claim 15 .................................................................................... 45
`7.
`Independent Claim 23 ............................................................... 49
`8.
`Ground 2 .............................................................................................. 51
`1.
`Ground 2 combination: Ground 1 + Amidi (EX1024) .............. 51
`2.
`Claims 1-3, 15, 23 ..................................................................... 55
`3.
`Claim 4 ...................................................................................... 55
`4.
`Claim 5 ...................................................................................... 59
`5.
`Claim 6 ...................................................................................... 62
`6.
`Claim 7 ...................................................................................... 62
`7.
`Claims 8, 14 ............................................................................... 65
`8.
`Claim 9 ...................................................................................... 66
`9.
`Claim 10 .................................................................................... 66
`10. Claim 11 .................................................................................... 67
`11. Claim 12 .................................................................................... 67
`12. Claim 13 .................................................................................... 68
`13. Claims 16-22, 24-30 .................................................................. 69
`Ground 3 .............................................................................................. 75
`1.
`Ground 3 combination: Ground 2 + Hajeck (EX1038) ............. 75
`2.
`Claims 1-30 ............................................................................... 76
`D. Ground 4 .............................................................................................. 77
`1.
`Ground 4 combination: Spiers (EX1025) + Amidi (EX1024) .. 77
`2.
`Independent Claim 1 ................................................................. 81
`3.
`Claim 2 ...................................................................................... 97
`4.
`Claim 3 ...................................................................................... 99
`
`C.
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Claim 4 ...................................................................................... 99
`5.
`Claim 5 ....................................................................................100
`6.
`Claim 6 ....................................................................................103
`7.
`Claim 7 ....................................................................................104
`8.
`Claim 8 ....................................................................................106
`9.
`10. Claim 9 ....................................................................................112
`11. Claim 10 ..................................................................................113
`12. Claim 11 ..................................................................................114
`13. Claim 12 ..................................................................................115
`14. Claim 13 ..................................................................................117
`15. Claim 14 ..................................................................................117
`16. Claim 15 ..................................................................................118
`17. Claims 16-30 ...........................................................................120
`Ground 5 ............................................................................................125
`1.
`Ground 5 combination: Ground 4 + Hajeck (EX1038) ...........125
`2.
`Claims 1-30 .............................................................................126
`VII. DISCRETIONARY DENIAL IS UNWARRANTED ............................127
`A. Discretionary Denial Under § 325(d) Is Unwarranted ......................127
`B.
`Discretionary Denial Under § 314(a) Is Unwarranted ......................128
`1.
`Fintiv Factors Strongly Favor Institution ................................128
`2.
`Discretionary Denial Under General Plastic Is Unwarranted 128
`VIII. CONCLUSION ..........................................................................................129
`
`
`E.
`
`
`
`iii
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Gen. Hosp. Corp. v. Sienna Biopharms., Inc.,
`888 F.3d 1368 (Fed. Cir. 2018) .......................................................................... 27
`Iron Grip Barbell Co. v. USA Sports, Inc.,
`392 F.3d 1317 (Fed. Cir. 2004) .......................................................................... 27
`Netlist, Inc. v. Micron Technology, Inc. et al.,
`No. 2:22-cv-00203 (E.D. Tex. filed June 10, 2022) ............................................. 1
`Netlist, Inc. v. Samsung Electronics Co., Ltd. et al.,
`No. 2:21-cv- 00463 (E.D. Tex. filed Dec. 20, 2021) ............................................ 1
`Samsung Electronics Co., Ltd. et al. v. Netlist, Inc.,
`No. 1:21-cv- 01453 (D. Del. filed Oct. 15, 2021) ................................................ 1
`Samsung Electronics Co., Ltd. v. Netlist, Inc.,
`IPR2022-00996 (U.S. Patent No. 11,016,918) ............................................. 1, 128
`Samsung Electronics Co., Ltd. v. Netlist, Inc.,
`IPR2022-00999 (U.S. Patent No. 11,232,054) ..................................................... 1
`SK hynix Inc. et al. v. Netlist, Inc.,
`IPR2017-00692 (U.S. Patent No. 8,874,831) ........................................................ 2
`Statutes
`35 U.S.C. § 103(a) ..................................................................................................... 3
`Other Authorities
`37 C.F.R. § 42.8(b)(1) ................................................................................................ 1
`37 C.F.R. § 42.8(b)(2) ................................................................................................ 1
`37 C.F.R. § 42.8(b)(3) ................................................................................................ 2
`37 C.F.R. § 42.8(b)(4) ................................................................................................ 2
`
`
`
`iv
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`37 C.F.R. § 42.104(a) ................................................................................................. 3
`37 C.F.R. § 42.104(b) ................................................................................................ 3
`
`
`
`
`v
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`EXHIBIT LIST
`
`
`
`Exhibit #
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`
`
`U.S. Patent No. 11,016,918
`
`File History of U.S. Patent No. 11,016,918
`
`Declaration of Dr. Andrew Wolfe
`
`Curriculum Vitae of Dr. Andrew Wolfe
`
`File History of U.S. Provisional Application No. 60/941,586
`
`File History of U.S. Patent Application No. 12/131,873
`
`File History of U.S. Patent Application No. 12/240,916
`
`File History of U.S. Provisional Application No. 61/512,871
`
`File History of U.S. Patent Application No. 13/559,476
`
`File History of U.S. Patent Application No. 14/489,269
`
`File History of U.S. Patent Application No. 14/840,865
`
`File History of U.S. Patent Application No. 15/934,416
`
`[Intentionally Omitted]
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 1 (PTAB
`June 20, 2014) (833 Patent IPR Petition)
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 8 (PTAB
`Dec. 16, 2014) (833 Patent Institution Decision)
`
`vi
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Exhibit #
`
`Description
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 8 (PTAB Sept. 22, 2014) (833 Patent IPR Corrected Petition)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 13 (PTAB Mar. 13, 2015) (833 Patent Institution Decision)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 1
`(PTAB Jan. 13, 2017) (833 Patent IPR Petition)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 7
`(PTAB July 24, 2017) (833 Patent Institution Decision)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 1
`(PTAB Jan. 17, 2017) (831 Patent IPR Petition)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 25
`(PTAB July 5, 2018) (831 Patent Final Written Decision)
`
`Micron Tech., Inc. et al. v. Netlist, Inc., IPR2022-00418, Paper No.
`2 (PTAB Jan. 14, 2022) (833 Patent IPR Petition)
`
`U.S. Patent Application Publication No. 2006/0174140 to Harris et
`al.
`
`1024
`
`U.S. Patent No. 7,724,604 to Amidi et al.
`
`1025
`
`1026
`
`1027
`
`
`
`U.S. Patent Application Publication No. 2006/0080515 to Spiers et
`al.
`
`JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B
`(January 2005) (“JESD79-2B”)
`
`JEDEC Standard, FBDIMM: Advanced Memory Buffer (AMB),
`JESD82-20 (March 2007) (“JESD82-20”)
`
`vii
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Exhibit #
`
`Description
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`JEDEC Standard, FBDIMM Specification: DDR2 SDRAM Fully
`Buffered DIMM (FBDIMM) Design Specification, JESD205
`(March 2007) (“JESD205”)
`
`Declaration of Julie Carlson for JESD82-20 and JESD205
`
`U.S. Patent No. 7,719,866 to Boldo
`
`PCI Local Bus Specification Revision 2.2 (1998)
`
`Mohan et al., Power Electronics: Converters, Applications, and
`Design (2d ed. 1995)
`
`U.S. Patent No. 7,721,130 to Prete et al.
`
`U.S. Patent No. 6,798,709 to Sim et al.
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0238536 to Hayashi
`et al.
`
`1038
`
`U.S. Patent No. 6,856,556 to Hajeck
`
`1039
`
`1040
`
`1041
`
`1042
`
`
`
`U.S. Patent Application Publication No. 2010/0257304 to Rajan et
`al.
`
`Texas Instruments, TPS51020 Datasheet (December 2003)
`
`Fairchild Semiconductor, FAN5026 Datasheet (October 2005)
`
`Murata Power Supply Reference Guide for Xilinx FPGAs
`(September 2006)
`
`viii
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Exhibit #
`
`Description
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`1048
`
`1049
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`1055
`
`1056
`
`1057
`
`
`
`Murata Power Supply Reference Guide for Altera FPGAs
`(February 2008)
`
`U.S. Patent Application Publication No. 2010/0205470 to
`Moshayedi et al.
`
`JEDEC Standard, Double Data Rate (DDR) SDRAM Specification,
`JESD79 (June 2000) (“JESD79”)
`
`JEDEC Standard, DDR3 SDRAM, JESD79-3A (September 2007)
`(“JESD79-3A”)
`
`U.S. Patent No. 7,023,187 to Shearon et al.
`
`Murata, DC-DC Converter Specification (DRAFT), MPD4S014S
`Datasheet (Jan. 21, 2008)
`
`Micron, NAND Flash Memory Datasheet (January 2006)
`
`U.S. Patent No. 7,692,938 to Petter
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0101147 to Amidi
`
`U.S. Patent No. 5,563,839 to Herdt et al.
`
`U.S. Patent No. 6,693,840 to Shimada et al.
`
`ix
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Exhibit #
`
`Description
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`1065
`
`1066
`
`1067
`
`1068
`
`1069
`
`
`
`Lenk, John D., Simplified Design of Switching Power Supplies
`(1995)
`
`U.S. Patent No. 7,061,214 to Mayega et al.
`
`U.S. Patent No. 5,630,096 to Zuravleff et al.
`
`Analog Devices, ADM1066 Datasheet (2006)
`
`Alan Moloney, Power-Supply Management—Principles, Problems,
`and Parts, Analog Dialogue (May 2006)
`
`National Semiconductor, LMC6953 PCI Local Bus Power
`Supervisor Datasheet (October 1996)
`
`U.S. Patent Application Publication No. 2007/0136523 to Bonella
`et al.
`
`U.S. Patent Application Publication No. 2009/0034354 to Resnick
`
`U.S. Patent No. 10,672,458 to Shaeffer et al.
`
`LatticeXP Family Data Sheet (March 2006)
`
`Complaint for Declaratory Judgment of Non-Infringement and
`Unenforceability; Breach of Contract, Samsung Electronics Co.,
`Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D. Del. filed Oct. 15,
`2021)
`
`First Amended Complaint for Declaratory Judgment of Non-
`Infringement and Unenforceability; Breach of Contract, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Jan. 18, 2022)
`
`x
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Exhibit #
`
`Description
`
`1070
`
`1071
`
`1072
`
`1073
`
`1074
`
`1075
`
`Netlist’s motion to dismiss the First Amended Complaint, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Feb. 16, 2022)
`
`Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al.,
`No. 2:21-cv-00463 (E.D. Tex. filed Dec. 20, 2021)
`
`Answer in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Apr. 12, 2022)
`
`Amended Complaint in Netlist, Inc. v. Samsung Electronics Co.,
`Ltd. et al., No. 2:21-cv-00463 (E.D. Tex. filed May 3, 2022)
`
`Complaint in Netlist, Inc. v. Micron Technology, Inc. et al., No.
`2:22-cv-00203 Dkt. 1 (E.D. Tex. filed June 10, 2022)
`
`Docket Control Order in Netlist, Inc. v. Micron Technology, Inc. et
`al., No. 2:22-cv-00203 Dkt. 40 (E.D. Tex. Oct. 21, 2022)
`
`
`
`xi
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
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`
`
`CLAIM LISTING
`
`Ref. #
`
`Listing of Challenged Claims
`
`1.a
`
`1.b
`
`1.c
`
`1.d
`
`1.e
`
`1.f
`
`1.g
`
`1.h
`
`1.i
`
`1. A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`
`a first buck converter configured to provide a first regulated voltage
`having a first voltage amplitude;
`
`a second buck converter configured to provide a second regulated
`voltage having a second voltage amplitude;
`
`a third buck converter configured to provide a third regulated voltage
`having a third voltage amplitude;
`
`a converter circuit configured to provide a fourth regulated voltage
`having a fourth voltage amplitude; and
`
`a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to one or more regulated voltages of
`the first, second, third and fourth regulated voltages, the plurality of
`components comprising:
`
`a plurality of synchronous dynamic random access memory (SDRAM)
`devices coupled to the first regulated voltage, and
`
`[1] at least one circuit coupled between a first portion of the plurality
`of edge connections and the plurality of SDRAM devices,
`[2] the at least one circuit operable to (i) receive a first plurality of
`address and control signals via the first portion of the plurality of edge
`connections, and (ii) output a second plurality of address and control
`
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Ref. #
`
`2
`
`3
`
`4
`
`5.a
`
`5.b
`
`6
`
`7
`
`Listing of Challenged Claims
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated
`voltage and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`
`2. The memory module of claim 1, wherein the first and third buck
`converters are further configured to operate as a dual buck converter.
`
`3. The memory module of claim 1, wherein the first voltage amplitude
`is 1.8 volts.
`
`4. The memory module of claim 1, wherein the second, third, and
`fourth voltage amplitudes are 2.5 volts, 1.2 volts, and 3.3 volts,
`respectively.
`
`5. The memory module of claim 1, further comprising:
`
`a voltage monitor circuit configured to monitor a power input voltage
`received via a second portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a trigger signal in
`response to the power input voltage having a voltage amplitude that is
`greater than a first threshold voltage.
`
`6. The memory module of claim 5, wherein the voltage monitor circuit
`is further configured to produce the trigger signal in response to the
`power input voltage having a voltage amplitude that is less than a
`second threshold voltage.
`
`7. The memory module of claim 6, wherein the second threshold
`voltage corresponds to a voltage level that is ten percent less than a
`specified operating voltage.
`
`8.a
`
`8. The memory module of claim 1, the plurality of components further
`comprising:
`
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Ref. #
`
`Listing of Challenged Claims
`
`8.b
`
`9
`
`10.a
`
`10.b
`
`11
`
`12.a
`
`12.b
`
`12.c
`
`13
`
`[1] one or more registers coupled to one of the first, second, third and
`fourth regulated voltages,
`[2] the one or more registers configured to register, in response to a
`clock, the first plurality of address and control signals,
`[3] wherein the one of the first, second, third and fourth regulated
`voltages is selectively switched off to turn power off to the one or more
`registers while one or more components of the plurality of components
`are powered on.
`
`9. The memory module of claim 5, wherein the first threshold voltage
`corresponds to a voltage level that is ten percent greater than a
`specified operating voltage.
`
`The memory module of claim 5, the plurality of components further
`comprising:
`
`a logic element including a non-volatile memory, the non-volatile
`memory is configured to store configuration information.
`
`11. The memory module of claim 10, wherein, in response to the
`trigger signal, the logic element writes information into the non-
`volatile memory.
`
`12. The memory module of claim 5, the plurality of components
`further comprising:
`
`a non-volatile memory; and
`
`a controller configured to receive the trigger signal, wherein, in
`response to the trigger signal, the controller performs a write operation
`to the non-volatile memory.
`
`13. The memory module of claim 5, wherein the power input voltage is
`coupled to the first, second, and third buck converters and the
`converter circuit.
`
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`Ref. #
`
`Listing of Challenged Claims
`
`14
`
`15.a
`
`15.b
`
`16.a
`
`16.b
`
`16.c
`
`16.d
`
`16.e
`
`14. The memory module of claim 8, wherein, in response to selectively
`switching on the one of the first, second, third and fourth regulated
`voltages to the one or more registers, the one or more registers is
`configured to output the registered first plurality of address and control
`signals to the plurality of SDRAM devices.
`
`15. The memory module of claim 1, the plurality of components
`further comprising:
`
`a logic element including one or more integrated circuits and discrete
`electrical elements, the one or more integrated circuit including an
`internal non-volatile memory, wherein the non-volatile memory is
`configured to store configuration information.
`
`A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`
`first, second, and third buck converters configured to receive a pre-
`regulated input voltage and to produce first, second and third regulated
`voltages, respectively;
`
`[1] a converter circuit configured to reduce the pre-regulated input
`voltage to provide a fourth regulated voltage,
`[2] wherein the first, second, third and fourth regulated voltages have
`first, second, third, and fourth voltage amplitudes, respectively;
`
`a plurality of components coupled to the PCB, the plurality of
`components including a plurality of synchronous dynamic random
`access memory (SDRAM) devices, each component of the plurality of
`components coupled to one or more regulated voltages of the first,
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`Ref. #
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`16.f
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`17
`
`18.a
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`18.b
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`19
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`20
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`21.a
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`21.b
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`Listing of Challenged Claims
`second, third and fourth regulated voltages; and
`
`a voltage monitor circuit configured to monitor an input voltage
`received via a first portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a signal in response to
`the input voltage having a voltage amplitude that is greater than a first
`threshold voltage.
`
`17. The memory module of claim 16, wherein the second and third
`buck converters are configured to operate as a dual buck converter.
`
`18. The memory module of claim 16, the plurality of components
`further including:
`
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein the controller executes a write operation in
`response to the signal.
`
`19. The memory module of claim 18, wherein the write operation
`includes writing data information into non-volatile memory.
`
`20. The memory module of claim 16, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`
`21. The memory module of claim 16, the plurality of components
`further including:
`
`[1] at least one circuit coupled between the interface and the plurality
`of SDRAM devices,
`[2] the at least one circuit operable to receive a first plurality of
`address and control signals via a second portion of the plurality of edge
`connections and to output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated
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`Ref. #
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`Listing of Challenged Claims
`voltage and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`
`22.a
`
`22.b
`
`23.a
`
`23.b
`
`23.c
`
`22. The memory module of claim 16, the plurality of components
`further including:
`
`a logic element including an internal non-volatile memory, wherein the
`non-volatile memory is configured to store configuration information,
`wherein the configuration information is used to program the logic
`element.
`
`A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`
`[1] a plurality of components coupled to the PCB, each component of
`the plurality of components coupled to one or more regulated voltages
`of first, second, third and fourth regulated voltages,
`[2] the plurality of components including a plurality of synchronous
`dynamic random access memory (SDRAM) devices and one or more
`registers, the plurality of SDRAM devices coupled to the first
`regulated voltage, the one or more registers coupled to (i) the second
`regulated voltage, (ii) a portion of the plurality of edge connections,
`and (iii) the plurality of SDRAM devices,
`[3] wherein a plurality of address and control signals are coupled to
`the one or more registers via the portion of the plurality of edge
`connections;
`
`23.d
`
`first, second, and third buck converters configured to provide the first,
`second and third regulated voltages, respectively; and
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
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`Ref. #
`
`Listing of Challenged Claims
`
`23.e
`
`23.f
`
`23.g
`
`23.h
`
`24.a
`
`24.b
`
`25.a
`
`25.b
`
`26
`
`27
`
`a converter circuit configured to provide the fourth regulated voltage,
`
`wherein the second regulated voltage is configured to be selectively
`switched on or off to the one or more registers while at least the
`plurality of SDRAM devices are powered on,
`
`wherein if the second regulated voltage is switched on while at least
`the plurality of SDRAM devices are powered on, the one or more
`registers are configured to couple the first plurality of address and
`control signals to the plurality of SDRAM devices, and
`
`wherein if the second regulated voltage is switched off while the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to decouple the plurality of SDRAM devices from the
`first plurality of address and control signals.
`
`24. The memory module of claim 23, further comprising:
`
`a voltage monitor circuit configured to monitor an input voltage
`received from the host system via the interface, the voltage monitor
`circuit configured to produce a signal in response to the input voltage
`having a voltage amplitude that is greater than a first threshold voltage.
`
`25. The memory module of claim 24, the plurality of components
`further including:
`
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein, in response to the signal, the controller
`executes a write operation.
`
`26. The memory module of claim 25, wherein the write operation
`includes writing data information to non-volatile memory.
`
`27. The memory module of claim 24, wherein the voltage monitor
`circuit is further configured to produce the signal in response to the
`input voltage having a voltage amplitude that is less than a second
`
`
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`Ref. #
`
`Listing of Challenged Claims
`threshold voltage.
`
`28
`
`29
`
`30
`
`28. The memory module of claim 23, wherein the second and third
`buck converters are configured to operate as a dual buck converter.
`
`29. The memory module of claim 23, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`
`30. The memory module of claim 23, wherein the first, second, and
`third buck converters are configured to receive a pre-regulated input
`voltage and to provide the first, second and third regulated voltages,
`respectively, and wherein the converter circuit is configured to reduce
`the pre-regulated voltage input to provide the fourth regulated voltage.
`
`
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`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`I.
`
`PETITIONERS’ MANDATORY NOTICES
`A. Real Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`The real parties in interest are the Petitioners, Micron Technology,
`
`Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas,
`
`LLC.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`The following judicial or administrative matters would affect, or be
`
`affected by, a decision in this proceeding concerning U.S. Patent No.
`
`11,016,918.
`
`The following proceedings are currently pending:
`
`Samsung Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-
`
`01453 (D. Del. filed Oct. 15, 2021)
`
`Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-
`
`00463 (E.D. Tex. filed Dec. 20, 2021)
`
`Netlist, Inc. v. Micron Technology, Inc. et al., No. 2:22-cv-00203
`
`(E.D. Tex. filed June 10, 2022)
`
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00999 (U.S.
`
`Patent No. 11,232,054)
`
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996 (U.S.
`
`Patent No. 11,016,918)
`
`1
`
`•
`
`•
`
`•
`
`•
`
`•
`
`
`
`

`

`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`•
`
`Application No. 17/582,797
`
`The following proceeding is no longer pending:
`
`•
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692 (U.S. Patent No.
`
`8,874,831)
`
`C. Counsel (37 C.F.R. § 42.8(b)(3))
`
`Lead Counsel for Petitioners
`Juan C. Yaquian
`Winston & Strawn LLP
`800 Capital Street, Suite 2400
`Houston, TX 77002-2925
`JYaquian@winston.com
`Tel. (713) 651-2600
`Fax. (713) 651-2700
`
`Backup Counsel for Petitioners
`Michael Rueckheim
`Winston & Strawn LLP
`255 Shoreline Drive, Suite 520
`Redwood City, CA 94065
`mrueckheim@winston.com
`Tel. (650) 858-6500
`Fax. (650) 858-6550
`(pro hac vice to be filed)
`
`D.
`Service Information (37 C.F.R. § 42.8(b)(4))
`Service information is provided in the designation of counsel above.
`
`Petitioners consent to service of all documents via electronic mail to Winston-IPR-
`
`Netlist@winston.com.
`
`
`
`
`
`2
`
`

`

`
`Petition for Inter Part