FAN5026 Dual DDR/Dual-Output PWM Controller
`
`October 2005
`
`FAN5026
`Dual DDR/Dual-Output PWM Controller
`
`Features
`■ Highly flexible dual synchronous switching PWM
`controller includes modes for:
`– DDR mode with in-phase operation for reduced
`channel interference
`– 90° phase shifted two-stage DDR Mode for reduced
`input ripple
`– Dual Independent regulators 180° phase shifted
`■ Complete DDR Memory power solution
`– VTT Tracks VDDQ/2
`– VDDQ/2 Buffered Reference Output
`■ Lossless current sensing on low-side MOSFET or
`Precision current sensing using sense resistor
`■ VCC Under-voltage Lockout
`■ Wide power input range: 3 to 16V
`■ Excellent dynamic response with Voltage
`Feed-Forward and Average Current Mode control
`■ Power-Good Signal
`■ Supports DDR-II and HSTL
`■ TSSOP28 package
`
`Applications
`■ DDR VDDQ and VTT voltage generation
`■ Desktop computer
`■ Graphics cards
`
`General Description
`The FAN5026 PWM controller provides high efficiency
`and regulation for two output voltages adjustable in the
`range from 0.9V to 5.5V that are required to power I/O,
`chip-sets, and memory banks in high-performance com-
`puters, set top boxes, and VGA cards. Synchronous rec-
`tification contributes to high efficiency over a wide range
`of loads. Efficiency is even further enhanced by using
`MOSFET’s RDS(ON) as a current sense component.
`Feed-forward ramp modulation, average current mode
`control scheme, and internal feedback compensation
`provide fast response to load transients. Out-of-phase
`operation with 180° phase shift reduces input current
` ripple. The controller can be transformed into a com-
`plete DDR memory power supply solution by activating a
`designated pin. In DDR mode of operation one of the
`channels tracks the output voltage of another channel
`and provides output current sink and source capability —
`features essential for proper powering of DDR chips. The
`buffered reference voltage required by this type of mem-
`ory is also provided. The FAN5026 monitors these out-
`puts and generates separate PGx (power good) signals
`when the soft-start is completed and the output is within
`±10% of its set point. A built-in over-voltage protection
`prevents the output voltage from going above 120% of
`the set point. Normal operation is automatically restored
`when the over-voltage conditions go away. Under-volt-
`age protection latches the chip off when either output
`drops below 75% of its set value after the soft-start
`sequence for this output is completed. An adjustable
`over-current function monitors the output current by
`sensing the voltage drop across the lower MOSFET. If
`precision current-sensing is required, an external cur-
`rent-sense resistor may optionally be used.
`
`Ordering Information
`Part Number
`FAN5026MTC
`FAN5026MTCX
`
`Temperature Range
`-40°C to 85°C
`-40°C to 85°C
`
`Package
`TSSOP-28
`TSSOP-28
`
`Packing
`Rails
`Tape and Reel
`
`©2005 Fairchild Semiconductor Corporation
`FAN5026 Rev. 1.0.5
`
`1
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 1
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Block Diagrams
`
`VCC
`
`+5
`
`FAN5026
`
`ILIM1
`
`DDR
`
`ILIM2/
`REF2
`
`PWM 1
`
`PWM 2
`
`VIN (BATTERY)
` = 3 to 16V
`
`Q1
`
`L OUT1
`
`VOUT1
`= 2.5V
`
`COUT1
`
`VIN (BATTERY)
`
`Q2
`
`Q3
`
`L OUT2
`
`VOUT2
`= 1.8V
`
`Q4
`
`COUT2
`
`Figure 1. Dual Output Regulator
`
`VCC
`
`+5
`
`FAN5026
`
`VIN (BATTERY)
` = 3 to 16V
`
`ILIM1
`
`DDR
`
`+5
`
`PG2/REF
`1.25V
`
`PWM 1
`
`PWM 2
`
`Q1
`
`L OUT1
`
`Q2
`
`Q3
`
`VDDQ
`= 2.5V
`
`COUT1
`
`R
`
`R
`
`L OUT2
`
`VTT =
`VDDQ/2
`
`Q4
`
`COUT2
`
`ILIM2/REF2
`
`Figure 2. Typical Application
`
`FAN5026 Rev. 1.0.5
`
`2
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 2
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`FAN5026
`
`28
`27
`26
`25
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`
`VCC
`LDRV2
`PGND2
`SW2
`HDRV2
`BOOT2
`ISNS2
`EN2
`GND
`VSEN2
`ILIM2/REF2
`SS2
`PG2/REF2OUT
`PG1
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`
`AGND
`LDRV1
`PGND1
`SW1
`HDRV1
`BOOT1
`ISNS1
`EN1
`GND
`VSEN1
`ILIM1
`SS1
`DDR
`VIN
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`Pin Configurations
`
`TSSOP-28
`θJA = 50°C/W; θJC = 16°C/W. See note below.
`Note: θJA and θJC values are determined using a 4 layer, 1" square PCB with 1 ounce copper.
`
`Pin Definitions
`
`
`Pin
`Number Pin Name
`1
`AGND
`
`2
`27
`3
`26
`4
`25
`5
`24
`6
`23
`7
`22
`8
`21
`
`9
`20
`10
`19
`11
`12
`17
`
`LDRV1
`LDRV2
`PGND1
`PGND2
`SW1
`SW2
`HDRV1
`
`BOOT1
`BOOT2
`ISNS1
`ISNS2
`EN1
`EN2
`
`GND
`
`VSEN1
`VSEN2
`ILIM1
`SS1
`SS2
`
`Pin Function Description
`
`
`Analog Ground. This is the signal ground reference for the IC. All voltage levels are
`measured with respect to this pin.
`
`Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of
`low-side MOSFET.
`
`Power Ground. The return for the low-side MOSFET driver. Connect to source of
`low-side MOSFET.
`
`Switching Node. Return for the high-side MOSFET driver and a current sense input.
`Connect to source of high-side MOSFET and low-side MOSFET drain.
`
`High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
`MOSFET.
`
`BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3.
`
`Current Sense Input. Monitors the voltage drop across the lower MOSFET or external
`
`sense resistor for current feedback.
`
`Enable. Enables operation when pulled to logic high. Toggling EN will also reset the
`regulator after a latched fault condition. These are CMOS inputs whose state is
`indeterminate if left open.
`
`Ground. These pins should be tied to AGND for proper operation.
`
`Output Voltage Sense. The feedback from the outputs. Used for regulation as well as
`
`PG, under-voltage and over-voltage protection and monitoring.
`
`Current Limit 1. A resistor from this pin to GND sets the current limit.
`
`Soft Start. A capacitor from this pin to GND programs the slew rate of the converter
`µ
`during initialization. During initialization, this pin is charged with a 5
`A current source.
`
`FAN5026 Rev. 1.0.5
`
`3
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 3
`
`

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`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Pin Definitions
` (Continued)
`
`Pin
`Number Pin Name
`13
`DDR
`
`14
`
`15
`
`16
`
`18
`
`28
`
`VIN
`
`PG1
`
`PG2 /
`REF2OUT
`
`ILIM2 /
`REF2
`
`VCC
`
`Pin Function Description
`
`
`DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out
`of phase.
`Input Voltage. Normally connected to battery, provides voltage feed-forward to set the
`
`amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V
`input, connect through 100K to ground, which will set the appropriate ramp gain and
`synchronize the channels 90° out of phase.
`
`Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a
`±10% range of the 0.9V reference.
`
`Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the
`VOUT is out of regulation or in a fault condition
`
`Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically
`
`used as the VDDQ/2 reference.
`
`Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current
`limit.
`Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2.
`
`
`
`VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate
`when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops
`below 4.3V (UVLO falling).
`
`Absolute Maximum Ratings
`Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired.
`Functional operation under these conditions is not implied.
`Parameter
`VCC Supply Voltage
`VIN
`BOOT, SW, ISNS, HDRV
`BOOT to SW
`All Other Pins
`Junction Temperature (T
`Storage Temperature
`Lead Soldering Temperature, 10 seconds
`
`)
`J
`
`–0.3
`–40
`–65
`
`Min.
`
`Typ.
`
`Max.
`6.5
`18
`24
`6.5
`VCC+0.3
`150
`150
`300
`
`Units
`V
`V
`V
`V
`V
`°C
`°C
`°C
`
`Recommended Operating Conditions
`Parameter
`Conditions
`Supply Voltage VCC
`Supply Voltage VIN
`)
`Ambient Temperature (T
`A
`
`note 1
`
`Min.
`4.75
`
`–40
`
`Typ.
`5
`
`Max.
`5.25
`16
`85
`
`Units
`V
`V
`°C
`
`FAN5026 Rev. 1.0.5
`
`4
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 4
`
`

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` Recommended operating conditions, unless otherwise noted.
`
`Conditions
`
`Min.
`
`Typ. Max.
`
`Units
`
`Electrical Specifications
`Parameter
`Power Supplies
`VCC Current
`
`LDRV, HDRV Open, VSEN forced
`above regulation point
`Shut-down (EN=0)
`VIN = 15V
`VIN = 0V
`
`Rising VCC
`Falling
`
`VIN = 16V
`VIN = 5V
`
`≥
`VIN
` 3V
`1V < VIN < 3V
`
`at start-up
`
`I
` from 0 to 5A,
`OUTX
`VIN from 5 to 15V
`
`µ
`as % of set point. 2
`S noise filter
`µ
`as % of set point. 2
`S noise filter
`Ω
`R
`= 68.5K
` see Figure 10.
`ILIM
`
`VIN Current – Sinking
`VIN Current – Sourcing
`VIN Current – Shut-down
`UVLO Threshold
`
`UVLO Hysteresis
`Oscillator
`Frequency
`Ramp Amplitude, pk–pk
`Ramp Amplitude, pk–pk
`Ramp Offset
`Ramp / VIN Gain
`Ramp / VIN Gain
`Reference and Soft Start
`Internal Reference Voltage
`Soft Start Current (I
`)
`SS
`Soft Start Complete Threshold
`PWM Converters
`Load Regulation
`
`VSEN Bias Current
`Under-Voltage Shutdown
`Over-Voltage Threshold
` Over-Current Threshold
`I
`SNS
`Minimum Duty Cycle
`Output Drivers
`HDRV Output Resistance
`
`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`2.2
`
`3.0
`
`–15
`
`4.55
`4.25
`300
`
`300
`2
`1.25
`0.5
`125
`250
`
`0.9
`–5
`1.5
`
`80
`75
`120
`140
`
`12
`2.4
`12
`1.2
`
`10
`
`4.3
`4.1
`
`255
`
`0.891
`
`-2
`
`50
`70
`115
`112
`10
`
`–86
`108
`
`99
`
`2
`
`30
`30
`–30
`1
`4.75
`4.45
`
`345
`
`0.909
`
`+2
`
`120
`80
`125
`168
`
`15
`4
`15
`2
`
`–94
`116
`0.5
`1
`1.01
`
`0.8
`
`mA
`
`µ
`A
`µ
`A
`µ
`A
`µ
`A
`V
`V
`mV
`
`KHz
`V
`V
`V
`mV/V
`mV/V
`
`V
`µ
`A
`V
`
`%
`
`nA
`%
`%
`µ
`A
`%
`
`Ω
`Ω
`Ω
`Ω
`
`%
`%
`V
`µ
`A
`
`% V
`REF2
`
`V
`V
`
`LDRV Output Resistance
`
`Sourcing
`Sinking
`Sourcing
`Sinking
`PG (Power Good Output) and Control pins
`µ
`Lower Threshold
`as % of set point, 2
`S noise filter
`µ
`Upper Threshold
`as % of set point, 2
`S noise filter
`PG Output Low
`IPG = 4mA
`Leakage Current
`V
` = 5V
`PULLUP
` < 10mA
`PG2/REF2OUT Voltage
`DDR = 1, 0 mA < I
`REF2OUT
`DDR, EN Inputs
`Input High
`Input Low
`
`FAN5026 Rev. 1.0.5
`
`5
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 5
`
`

`

`
`
`
`
`
`
`
`
`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`EN
`
`DDR
`
`VIN
`
`VSEN
`
`SS
`
`PGOOD
`
`REF2
`
`5V
`
`VDD
`
`DDR
`
`ADAPTIVE
`GATE
`CONTROL LOGIC
`
`VDD
`
`PWM
`
`S/H
`
`BOOT
`
`CBOOT
`
`VIN
`
`Q1
`
`Q2
`
`L OUT
`
`VOUT
`
`COUT
`
`HDRV
`
`SW
`
`LDRV
`
`PGND
`
`POR/UVLO
`
`OSC
`CLK
`
`OVP
`
`RAMP
`
`Q
`
`S R
`
`PWM
`
`
`
`RAMP
`
`ILIM det.
`
`EA
`
`CURRENT PROCESSING
`IOUT
`
`?
`
`ISNS
`
`ILIM
`
`RSENSE
`
`R ILIM
`
`Reference and
`Soft Start
`
`VREF
`
`DDR
`
`Figure 3. IC Block Diagram
`
`FAN5026 Rev. 1.0.5
`
`6
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 6
`
`

`

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`Typical Applications
`
`VIN = 3 to 16V
`
`+5
`
`C4
`
`R3
`
`+5
`
`C2
`
`R4
`
`VCC
`
`28
`
`ILIM1
`
`EN1
`
`SS1
`
`11
`
`8
`
`12
`
`PG1
`
`15
`
`VIN
`14
`
`PWM 1
`
`6
`
`5
`
`4
`
`2
`
`3
`
`7
`
`BOOT1
`
`Q1A
`HDRV1
`
`SW1
`
`Q1B
`LDRV1
`
`PGND2
`ISNS1
`
`VSEN1
`
`C1
`
`C9
`
`D1
`
`+5
`
`C5
`
`L1
`
`VDDQ = 2.5V
`
`C6
`
`R7
`
`R5
`
`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`DDR
`
`EN2
`
`SS2
`
`+5
`
`C3
`
`1.25V@10mA
`PG2/REF
`
`AGND
`
`13
`
`21
`
`17
`
`16
`
`9
`
`20
`
`1
`
`PWM 2
`
`10
`
`23
`
`24
`
`25
`
`27
`
`26
`
`22
`
`19
`
`18
`
`BOOT2
`
`Q2A
`
`HDRV2
`
`SW2
`
`Q2B
`
`LDRV2
`
`PGND2
`
`ISNS2
`
`VSEN2
`
`ILIM2/REF2
`
`R1
`
`R6
`
`D2
`
`+5
`
`C7
`
`L2
`
`VTT = VDDQ/2
`
`R2
`
`C8
`
`R8
`
`Figure 4. DDR Regulator Application
`
`Table 1. DDR Regulator BOM
`
`Description
`Ω
`Capacitor 68µF, Tantalum, 25V, ESR 150m
`Capacitor 10nF, Ceramic
`Ω
`Capacitor 68µF, Tantalum, 6V, ESR 1.8
`Capacitor 150nF, Ceramic
`Ω
`Capacitor 180µF, Specialty Polymer 4V, ESR 15m
`Ω
`Capacitor 1000µF, Specialty Polymer 4V, ESR 10m
`Capacitor 0.1µF, Ceramic
`Ω
`1.82K
`, 1% Resistor
`Ω
`56.2K
`, 1% Resistor
`Ω
`10K
`, 5% Resistor
`Ω
`3.24K
`, 1% Resistor
`Ω
`, 1% Resistor
`1.5K
`Schottky Diode 30V
`Ω
`Inductor 6.4µH, 6A, 8.64m
`Ω
`Inductor 0.8µH, 6A, 2.24m
`Dual MOSFET with Schottky
`DDR Controller
`
`Qty
`1
`2
`1
`2
`2
`1
`1
`3
`1
`1
`1
`2
`2
`1
`1
`2
`1
`
`Ref.
`
`C1
`C2, C3
`C4
`C5, C7
`C6A, C6B
`C8
`C9
`R1, R2, R6
`R3
`R4
`R5
`R7, R8
`D1, D2
`L1
`L2
`Q1, Q2
`U1
`
`TAJB686*006
`
`Part Number
`TPSV686*025#0150
`
`Vendor
`AVX
`Any
`AVX
`Any
`Panasonic EEFUE0G181R
`Kemet
`T510E108(1)004AS4115
`Any
`Any
`Any
`Any
`Any
`Any
`BAT54
`Fairchild
`Panasonic ETQ-P6F6R4HFA
`Panasonic ETQ-P6F0R8LFA
`Fairchild
`FDS6986S (note 1)
`Fairchild
`FAN5026
`
`Notes:
`
`1. Suitable for applications of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required use single SO-8
`Ω
`packages for Q1A (FDS6612A) and Q1B (FDS6690S) respectively. Using FDS6690S, change R7 to 1200
`. Refer to Power
`MOSFET Selection, page 14 for more information.
`µ
`2. C6 = 2 X 180
`F in parallel.
`
`FAN5026 Rev. 1.0.5
`
`7
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 7
`
`

`

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`Typical Applications
`
`
` (Continued)
`
`VIN = 3 to 16V
`
`+5
`
`VCC
`
`28
`
`C4
`
`R2
`
`C2
`
`+5
`
`R3
`
`ILIM1
`
`EN1
`
`SS1
`
`11
`
`8
`
`12
`
`PG1
`
`15
`
`VIN
`14
`
`PWM 1
`
`BOOT1
`
`Q1A
`HDRV1
`
`SW1
`
`Q1B
`LDRV1
`
`PGND2
`
`6
`
`5
`
`4
`
`2
`
`3
`
`ISNS1
`
`7
`10 VSEN1
`
`C1
`
`D1
`
`C9
`
`+5
`
`C5
`
`L1
`
`2.5V@4A
`
`C6
`
`R5
`
`R6
`
`R4
`
`VIN
`
`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`D2
`
`+5
`
`C7
`
`L2
`
`1.8V@2A
`
`R7
`
`C8
`
`R8
`
`R9
`
`R1
`
`C3
`
`EN2
`
`PG2
`
`SS2
`
`AGND
`
`DDR
`
`GND
`
`GND
`
`21
`
`16
`
`17
`
`1
`
`13
`
`20
`
`9
`
`PWM 2
`
`23
`
`24
`
`25
`
`BOOT2
`
`Q2A
`
`HDRV2
`
`SW2
`
`Q2B
`
`LDRV2
`
`27
`26 PGND2
`ISNS2
`
`22
`19 VSEN2
`ILIM2
`
`18
`
`Figure 5. Dual Regulator Application
`
`Table 2. Dual Regulator BOM
`
`Description
`Ω
`Capacitor 68µF, Tantalum, 25V, ESR 95m
`Capacitor 10nF, Ceramic
`Capacitor 68µF, Tantalum, 6V, ESR 1.8Ω
`Capacitor 150nF, Ceramic
`Capacitor 330µF, Poscap, 4V, ESR 40mΩ
`Capacitor 0.1µF, Ceramic
`56.2KΩ, 1% Resistor
`10KΩ, 5% Resistor
`3.24KΩ, 1% Resistor
`1.82KΩ, 1% Resistor
`1.5KΩ, 1% Resistor
`Schottky Diode 30V
`Inductor 6.4µH, 6A, 8.64mΩ
`Dual MOSFET with Schottky
`DDR Controller
`
`Qty
`1
`2
`1
`2
`2
`2
`1
`1
`1
`3
`2
`2
`2
`1
`1
`
`Ref.
`
`C1
`C2, C3
`C4
`C5, C7
`C6, C8
`C9
`R1, R2
`R3
`R4
`R5, R8, R9
`R6, R7
`D1, D2
`L1, L2
`Q1
`U1
`
`Vendor
`AVX
`Any
`AVX
`Any
`Sanyo
`Any
`Any
`Any
`Any
`Any
`Any
`Fairchild
`Panasonic
`Fairchild
`Fairchild
`
`Part Number
`TPSV686*025#095
`
`TAJB686*006
`
`4TPB330ML
`
`BAT54
`ETQ-P6F6R4HFA
`FDS6986S (note 1)
`FAN5026
`
`Note:
`
`1.
`If currents above 4A continuous required, use single SO-8 packages for Q1A/Q2A (FDS6612A) and Q1B/Q2B (FDS6690S)
`respectively. Using FDS6690S, change R6/R7 as required. Refer to Power MOSFET Selection, page 14 for more information.
`
`FAN5026 Rev. 1.0.5
`
`8
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 8
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Circuit Description
`Overview
`The FAN5026 is a multi-mode, dual channel PWM con-
`troller intended for graphic chipset, SDRAM, DDR DRAM
`or other low output voltage power applications in PC’s,
`VGA Cards and set top boxes. The IC integrates a con-
`trol circuitry for two synchronous buck converters. The
`output voltage of each controller can be set in the range
`of 0.9V to 5.5V by an external resistor divider.
`
`The two synchronous buck converters can operate from
`either an unregulated DC source (such as a notebook
`battery) with voltage ranging from 5.0V to 16V, or from a
`regulated system rail of 3.3V to 5V. In either mode of
`operation the IC is biased from a +5V source. The PWM
`modulators use an average current mode control with
`input voltage feed-forward for simplified feedback loop
`compensation and improved line regulation. Both PWM
`controllers have integrated feedback loop compen-
`sation that dramatically reduces the number of external
`components.
`
`The FAN5026 can be configured to operate as a com-
`plete DDR solution. When the DDR pin is set high, the
`second channel can provide the capability to track the
`output voltage of the first channel. The PWM2 converter
`is prevented from going into hysteretic mode if the DDR
`pin is set high. In DDR mode, a buffered reference volt-
`age (buffered voltage of the REF2 pin), required by DDR
`memory chips, is provided by the PG2 pin.
`
`Converter Modes and Synchronization
`
`Table 3. Converter Modes and Synchronization
`
`PWM 2 w.r.t.
`DDR
`PWM1
`Pin
`VIN Pin
`Mode VIN
`HIGH IN PHASE
`DDR1 Battery VIN
`DDR2
`+5V
`R to GND HIGH + 90°
`DUAL ANY
`VIN
`LOW + 180°
`
`When used as a dual converter (as in Figure 5), out-of-
`phase operation with 180 degree phase shift reduces
`input current ripple.
`
`For the “2-step” conversion (where the VTT is converted
`from VDDQ as in Figure 4) used in DDR mode, the duty
`cycle of the second converter is nominally 50% and the
`optimal phasing depends on VIN. The objective is to
`keep noise generated from the switching transition in one
`converter from influencing the “decision” to switch in the
`other converter.
`
`When VIN is from the battery, it’s typically higher than
`7.5V. As shown in Figure 6, 180° operation is undesir-
`able since the turn-on of the VDDQ converter occurs
`very near the decision point of the VTT converter.
`
`CLK
`
`VDDQ
`
`VTT
`
`Figure 6. Noise-Susceptible 180° Phasing for
`DDR1
`In-phase operation is optimal to reduce inter-converter
`interference when VIN is higher than 5V, (when VIN is
`from a battery), as can be seen in Figure 7. Since the
`duty cycle of PWM1 (generating VDDQ) is short, its
`switching point occurs far away from the decision point
`for the VTT regulator, whose duty cycle is nominally 50%.
`
`CLK
`
`VDDQ
`
`VTT
`
`Figure 7. Optimal In-Phase Operation for DDR1
`When VIN ≈ 5V, 180° phase shifted operation can be
`rejected for the same reasons demonstrated Figure 6.
`In-phase operation with VIN ≈ 5V is even worse, since
`the switch point of either converter occurs near the
`switch point of the other converter as seen in Figure 8. In
`this case, as VIN is a little higher than 5V it will tend to
`cause early termination of the VTT pulse width. Con-
`versely, VTT’s switch point can cause early termination
`of the VDDQ pulse width when VIN is slightly lower than
`5V.
`
`CLK
`
`VDDQ
`
`VTT
`
`Figure 8. Noise-Susceptible In-Phase Operation
`for DDR2
`These problems are nicely solved by delaying the 2nd
`converter's clock by 90° as shown in Figure 9. In this
`way, all switching transitions in one converter take place
`far away from the decision points of the other converter.
`
`FAN5026 Rev. 1.0.5
`
`9
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 9
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Current Processing Section
`The following discussion refers to Figure 10.
`The current through RSENSE resistor (ISNS) is sampled
`shortly after Q2 is turned on. That current is held, and
`summed with the output of the error amplifier. This effec-
`tively creates a current mode control loop. The resistor
`connected to ISNSx pin (RSENSE) sets the gain in the
`current feedback loop. For stable operation, the voltage
`induced by the current feedback at the PWM comparator
`input should be set to 30% of the ramp amplitude at
`maximum load current and line voltage. The following
`expression estimates the recommended value of RSENSE
`as a function of the maximum load current (ILOAD(MAX))
`and the value of the MOSFET’s RDS(ON):
`•
`•
`) RDS ON(
`ILOAD MAX
`) 4.1K
`(
`
`•
`•
`30% 0.125 VIN MAX
`(
`)
`
`=
`
`----------------------------------------------------------------------------- 100–
`
`(2a)
`
`RSENSE
`
`RSENSE must, however, be kept higher than:
`•
`) RDS ON(
`ILOAD MAX
`)
`(
`
`150µA
`
`=
`
`----------------------------------------------------------- 100–
`
`RSENSE MIN(
`
`)
`
`(2b)
`
`CLK
`
`VDDQ
`
`VTT
`
`Figure 9. Optimal 90° Phasing for DDR2
`
`Initialization and Soft Start
`Assuming EN is high, FAN5026 is initialized when VCC
`exceeds the rising UVLO threshold. Should VCC drop
`below the UVLO threshold, an internal Power-On Reset
`function disables the chip.
`
`The voltage at the positive input of the error amplifier is
`limited by the voltage at the SS pin which is charged with
`a 5µA current source. Once CSS has charged to VREF
`(0.9V) the output voltage will be in regulation. The time it
`takes SS to reach 0.9V is:
`
`(1)
`
`× 5
`
`0.9 CSS
`-------------------------
`
`T0.9
`
`=
`
`where T0.9 is in seconds if CSS is in µF.
`When SS reaches 1.5V, the Power Good outputs are
`enabled and hysteretic mode is allowed. The converter is
`forced into PWM mode during soft start.
`
`0.17pF
`
`17pF
`
`1.5M
`
`300K
`
`VSEN
`
`4.14K
`
`V to I
`
`TO PWM COMP
`
`I1A =
`ISNS
`
`SS
`
`CSS
`
`Reference and
`Soft Start
`
`ILIM det.
`
`2.5V
`
`I2 =
`
`RSENSE
`
`ISNS
`
`LDRV
`
`PGND
`
`ILIM
`
`RILIM
`
`S/H
`
`in +
`
`in –
`
`I1B =
`ISNS
`9
`
`0.9V
`
`4 * ILIM
`3
`
`ILIM mirror
`
`Figure 10. Current Limit / Summing Circuits
`
`FAN5026 Rev. 1.0.5
`
`10
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 10
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Gate Driver Section
`The adaptive gate control logic translates the internal
`PWM control signal into the MOSFET gate drive signals
`providing necessary amplification, level shifting and
`shoot-through protection. Also, it has functions that help
`optimize the IC performance over a wide range of oper-
`ating conditions. Since MOSFET switching time can vary
`dramatically from type to type and with the input voltage,
`the gate control logic provides adaptive dead time by
`monitoring the gate-to-source voltages of both upper and
`lower MOSFETs. The lower MOSFET drive is not turned
`on until the gate-to-source voltage of the upper MOSFET
`has decreased to less than approximately 1 volt. Simi-
`larly, the upper MOSFET is not turned on until the gate-
`to-source voltage of the lower MOSFET has decreased
`to less than approximately 1 volt. This allows a wide vari-
`ety of upper and lower MOSFETs to be used without a
`concern for simultaneous conduction, or shoot-through.
`
`There must be a low-resistance, low-inductance path
`between the driver pin and the MOSFET gate for the
`adaptive dead-time circuit to work properly. Any delay
`along that path will subtract from the delay generated by
`the adaptive dead-time circuit and shoot-through may
`occur.
`
`Frequency Loop Compensation
`Due to the implemented current mode control, the modu-
`lator has a single pole response with -1 slope at fre-
`quency determined by load
`
`(5)
`
`FPO
`
`=
`
`1
`------------------------
`2πROCO
`where RO is load resistance and CO is load capacitance.
`For this type of modulator, Type 2 compensation circuit is
`usually sufficient. To reduce the number of external com-
`ponents and simplify the design task, the PWM controller
`has an internally compensated error amplifier. Figure 12
`shows a Type 2 amplifier and its response along with the
`responses of a current mode modulator and of the con-
`verter. The Type 2 amplifier, in addition to the pole at the
`origin, has a zero-pole pair that causes a flat gain region
`at frequencies between the zero and the pole.
`
`Setting the Current Limit
`A ratio of ISNS is also compared to the current
`established when a 0.9 V internal reference drives the
`ILIM pin. The threshold is determined at the point when
`ILIM 4×
`the
`. Since
`ISNS
`>
`---------------
`----------------------
`9
`3
`×
`ILOAD RDS ON(
`)
`--------------------------------------------
`100 R+ SENSE
`
`ISNS
`
`=
`
` therefore,
`
`(3a)
`
`(3b)
`
`×
`)
`(
`100 RSENSE
`9
`+
`----------------------------------------------------
`RDS ON(
`)
`
`×
`
`43---
`
`×
`
`0.9V
`--------------
`RILIM
`
`=
`
`10.8
`---------------
`ILIMIT
`
`×
`
`)
`(
`100 RSENSE
`+
`-------------------------------------------
`RDS ON(
`)
`
`ILIMIT
`or
`
`RILIM
`
`=
`
`Since the tolerance on the current limit is largely depen-
`dent on the ratio of the external resistors, it is fairly accu-
`rate if the voltage drop on the Switching Node side of
`RSENSE is an accurate representation of the load current.
`When using the MOSFET as the sensing element, the
`variation of RDS(ON) causes proportional variation in the
`ISNS. This value not only varies from device to device,
`but also has a typical junction temperature coefficient of
`about 0.4%/°C (consult the MOSFET datasheet for
`actual values), so the actual current limit set point will
`decrease proportional to increasing MOSFET die tem-
`perature. A factor of 1.6 in the current limit setpoint
`should compensate for all MOSFET RDS(ON) variations,
`assuming the MOSFET’s heat sinking will keep its oper-
`ating die temperature below 125°C.
`
`Q2
`
`R1
`
`LDRV
`
`ISNS
`
`RSENSE
`
`PGND
`
`Figure 11. Improving Current Sensing Accuracy
`More accurate sensing can be achieved by using a resis-
`tor (R1) instead of the RDS(ON) of the FET as shown in
`Figure 11. This approach causes higher losses, but
`yields greater accuracy in both VDROOP and ILIMIT. R1 is
`a low value (e.g. 10mΩ) resistor.
`Current limit (ILIMIT) should be set sufficiently high as to
`allow inductor current to rise in response to an output
`load transient. Typically, a factor of 1.3 is sufficient. In
`addition, since ILIMIT is a peak current cut-off value, we
`will need to multiply ILOAD(MAX) by the inductor ripple cur-
`rent (we'll use 25%). For example, in Figure 5 the target
`for ILIMIT would be:
`ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈ 14A
`
`(4)
`
`FZ
`
`=
`
`1
`----------------------
`2πR2C1
`
`=
`
`6kHz
`
`FP
`
`=
`
`1
`----------------------
`2πR2C2
`
`=
`
`600kHz
`
`(6a)
`
`(6b)
`
`This region is also associated with phase ‘bump’ or
`reduced phase shift. The amount of phase shift reduction
`depends the width of the region of flat gain and has a
`maximum value of 90 degrees. To further simplify the
`converter compensation, the modulator gain is kept inde-
`pendent of the input voltage variation by providing feed-
`forward of VIN to the oscillator ramp.
`
`FAN5026 Rev. 1.0.5
`
`11
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 11
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`The optimal value of C(Z) is:
`
`C Z(
`
`)
`
`=
`
`
`)
`) C OUT× (
`
`(
`L OUT
`-------------------------------------------------------
`R5
`
`(7)
`
`Protection
`The converter output is monitored and protected against
`extreme overload, short circuit, over-voltage and under-
`voltage conditions.
`
`A sustained overload on an output sets the PGx pin low
`and latches-off the whole chip. Operation can be
`restored by cycling the VCC voltage or by toggling the
`EN pin.
`
`If VOUT drops below the under-voltage threshold, the
`chip shuts down immediately.
`
`Over-Current Sensing
`If the circuit’s current limit signal (“ILIM det” as shown in
`Figure 10) is high at the beginning of a clock cycle, a
`pulse-skipping circuit is activated and HDRV is inhibited.
`The circuit continues to pulse skip in this manner for the
`next 8 clock cycles. If at any time from the 9th to the 16th
`clock cycle, the “ILIM det” is again reached, the over-
`current protection latch is set, disabling the chip. If “ILIM
`det” does not occur between cycle 9 and 16, normal oper-
`ation is restored and the over-current circuit resets itself.
`
`PGOOD
`
`8 CLK
`
`IL
`
`VOUT
`
`SHUTDOWN
`
`1
`
`2
`
`3
`
`CH1 5.0V
`CH3 2.0AΩ
`
`CH2 100mV
`
`M 10.0µs
`
`Figure 14. Over-Current Protection Waveforms
`
`Over-Voltage / Under-Voltage Protection
`Should the VSNS voltage exceed 120% of VREF (0.9V)
`due to an upper MOSFET failure, or for other reasons,
`the overvoltage protection comparator will force LDRV
`high. This action actively pulls down the output voltage
`and, in the event of the upper MOSFET failure, will even-
`tually blow the battery fuse. As soon as the output volt-
`age drops below the threshold, the OVP comparator is
`disengaged.
`
`This OVP scheme provides a ‘soft’ crowbar function
`which helps to tackle severe load transients and does
`not invert the output voltage when activated — a com-
`mon problem for latched OVP schemes.
`
`C2
`
`C1
`
`R2
`
`VIN
`
`R1
`
`REF
`
`EA Out
`
`Converter
`
`error amp
`
`modulator
`
`18
`
`14
`
`0
`
`F P0
`
`F Z
`
`FP
`
`Figure 12. Compensation
`The zero frequency, the amplifier high frequency gain
`and the modulator gain are chosen to satisfy most typical
`applications. The crossover frequency will appear at the
`point where the modulator attenuation equals the ampli-
`fier high frequency gain. The only task that the system
`designer has to complete is to specify the output filter
`capacitors to position the load main pole somewhere
`within one decade lower than the amplifier zero fre-
`quency. With this type of compensation plenty of phase
`margin is easily achieved due to zero-pole pair phase
`‘boost’.
`
`Conditional stability may occur only when the main load
`pole is positioned too much to the left side on the fre-
`quency axis due to excessive output filter capacitance. In
`this case, the ESR zero placed within the 10kHz...50kHz
`range gives some additional phase ‘boost’. Fortunately,
`there is an opposite trend in mobile applications to keep
`the output capacitor as small as possible.
`
`If a larger inductor value or low ESR values are called for
`by the application, additional phase margin can be
`achieved by putting a zero at the LC crossover fre-
`quency. This can be achieved with a capacitor across the
`feedback resistor (e.g. R5 from Figure 5) as shown
`below.
`
`L(OUT)
`
`VOUT
`
`R5
`
`C(Z)
`
`C(OUT)
`
`VSEN
`
`R6
`
`Figure 13. Improving Phase Margin
`
`FAN5026 Rev. 1.0.5
`
`12
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 12
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`Similarly, if an output short-circuit or severe load tran-
`sient causes the output to droop to less than 75% of its
`regulation set point. Should this condition occur, the reg-
`ulator will shut down.
`
`Over-Temperature Protection
`The chip incorporates an over temperature protection
`circuit that shuts the chip down when a die temperature
`of about 150°C is reached. Normal operation is restored
`at die temperature below 125°C with internal Power On
`Reset asserted, resulting in a full soft-start cycle.
`
`Design and Component Selection
`Guidelines
`As an initial step, define operating input voltage range,
`output voltage, minimum and maximum load currents for
`the controller.
`
`Setting the Output Voltage
`The internal reference is 0.9V. The output is divided
`down by a voltage divider to the VSEN pin (for example,
`R5 and R6 in Figure 4). The output voltage therefore is:
`
`0.9V
`------------
`R6
`
`=
`
`VOUT 0.9V
`–
`---------------------------------
`R5
`
`(8a)
`
`To minimize noise pickup on this node, keep the resistor
`to GND (R6) below 2K. We selected R6 at 1.82K. Then
`choose R5:
`
`where ∆I is the inductor ripple current and ∆VOUT is the
`maximum ripple allowed.
`
`L
`
`=
`
`VIN VOUT
`–
`------------------------------
`∆I×
`FSW
`
`×
`
`VOUT
`--------------
`VIN
`
`(10)
`
`for this example we’ll use:
`VIN = 12V, VOUT = 2.5V
`∆I = 25% × 6A = 1.5A
`FSW = 300KHz.
`therefore
`L ≈ 4.4µH
`Output Capacitor Selection
`The output capacitor serves two major functions in a
`switching power supply. Along with the inductor it filters
`the sequence of pulses produced by the switcher, and it
`supplies the load transient currents. The output capacitor
`requirements are usually dictated by ESR, Inductor rip-
`ple current (∆I) and the allowable ripple voltage (∆V).
`
`ESR
`
`<
`
`∆V
`--------
`∆I
`
`(11)
`
`In addition, the capacitor’s ESR must be low enough to
`allow the converter to stay in regulation during a load
`step. The ripple voltage due to ESR for the converter in
`Figure 5 is 120mV P-P. Some additional ripple will
`appear due to the capacitance value itself:
`
`R5
`
`=
`
`)
`(
`×
`)
`(
`VOUT 0.9–
`1.82K
`-------------------------------------------------------------
`0.9
`
`=
`
`3.24K
`
`(8b)
`
`∆V
`
`=
`
`∆I
`------------------------------------------
`COUT 8×
`×
`FSW
`
`(12)
`
`For DDR applications converting from 3.3V to 2.5V, or
`other applications requiring high duty cycles, the duty
`cycle clamp must be disabled by tying the converter’s
`FPWM to GND. When converter’s FPWM is GND, the
`converter's maximum duty cycle will be greater than
`90%. When using as a DDR converter with 3.3V input,
`set up the converter for In-Phase synchronization by
`tying the VIN pin to +5V.
`
`which is only about 1.5mV for the converter in Figure 5
`and can be ignored.
`
`The capacitor must also be rated to withstand the RMS
`current which is approximately 0.3 X (∆I), or about
`400mA for the converter in Figure 5. High frequency
`decoupling capacitors should be placed as close to the
`loads as physically possible.
`
`Input Capacitor Selection
`The input capacitor should be selected by its ripple cur-
`rent rating.
`
`Two-Stage Converter Case
`In DDR mode (Figure 4), the VTT power input is powered
`by the VDDQ output, therefore all of the input capacitor
`ripple current is produced by the VDDQ converter. A con-
`servative estimate of the output current required for the
`2.5V regulator is:
`
`IREG1
`
`=
`
`IVDDQ
`
`+
`
`IVTT
`-----------
`2
`
`(9)
`
`Output Inductor Selection
`The minimum practical output inductor value is the one
`that keeps inductor current just on the boundary of con-
`tinuous conduction at some minimum load. The industry
`standard practice is to choose the minimum current
`somewhere from 15% to 35% of the nominal current. At
`light load, the controller can automatically switch to hys-
`teretic mode of operation to sustain high efficiency. The
`following equations help to choose the proper value of
`the output filter inductor.
`∆VOUT
`------------------
`ESR
`
`∆I
`
`=
`
`×
`2 IMIN
`
`=
`
`FAN5026 Rev. 1.0.5
`
`13
`
`www.fairchildsemi.com
`
`Petitioners
`Ex. 1041, p. 13
`
`

`

`FAN5026 Dual DDR/Dual-Output PWM Controller
`
`fore is also representative of gate charge (QG). CISS =
`CGD + CGS, and it controls t1, t2, and t4 timing. CGD
`receives the current from the gate driver during t3 (as
`VDS is falling). The gate charge (QG) parameters on the
`lower graph are either specified or can be derived from
`MOSFET datasheets.
`
`Assuming switching losses are about the same for both
`the rising edge and falling edge, Q1’s switching losses,
`occur during the shaded time when the MOSFET has
`voltage across it and current through it.
`
`These losses are gi