`Hajeck
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`USOO6856556B1
`US 6,856,556 B1
`Feb. 15, 2005
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`(10) Patent No.:
`(45) Date of Patent:
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`STORAGE SUBSYSTEM WITH EMBEDDED
`CIRCUIT FOR PROTECTING AGAINST
`ANOMALIES IN POWER SIGNAL FROM
`HOST
`
`Inventor: Michael J. Hajeck, San Juan
`Capistrano, CA (US)
`Assignee: Siliconsystems, Inc., Hawthorne, CA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 1 day.
`
`Notice:
`
`Appl. No.: 10/406,805
`Filed:
`Apr. 3, 2003
`Int. Cl................................................... G11C 7700
`U.S. Cl. ................... 365/189.11; 365/191; 36.5/226
`Field of Search ............................ 365/189.11, 191,
`365/226, 189.01, 229, 185.33, 212, 200,
`189.07, 225.7, 203, 189.08, 158, 171; 307/43–46,
`48, 64, 66, 85-87
`
`References Cited
`
`U.S. PATENT DOCUMENTS
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`5,596,532 A *
`5,693,570 A
`5,706.239 A *
`5,781,473 A
`5,798.961. A *
`5,873,112 A *
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`1/1997
`12/1997
`1/1998
`7/1998
`8/1998
`2/1999
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`Cernea et al. ......... 365/185.18
`Cernea et al.
`Brys . . . . . . . . . . . . . . . . . . . . . . . . . . 365/226
`Javanifard et al.
`Heyden et al. ............... 365/52
`Norman ...................... 711/103
`
`5,880,622 A * 3/1999 Evertt et al. ................ 327/535
`6.424,570 B1
`7/2002 Le et al.
`6,515.903 B1
`2/2003 Le et al.
`6,532,178 B2 * 3/2003 Taub ..................... 365/189.11
`6,552,933 B2 * 4/2003 Roohparvar ........... 365/185.18
`6,678,189 B2
`1/2004 Tran ........................... 365/171
`2002/0114184 A1 * 8/2002 Gongwer et al. ...... 365/185.11
`2003/0048673 A1
`3/2003 Naso et al. ................. 365/200
`* cited by examiner
`Primary Examiner Richard Elms
`ASSistant Examiner-Dang Nguyen
`(74) Attorney, Agent, or Firm- Knobbe, Martens, Olson &
`Bear LLP
`ABSTRACT
`(57)
`A Storage Subsystem, Such as a flash memory card, includes
`a charge pump that receives a power Signal from a host
`System, and generates a regulated power Signal that is
`provided to the storage subsystem's controller. When the
`power Signal from the host is interrupted, the charge pump
`additionally acts as a backup power Supply Such that the
`Storage Subsystem can continue to operate temporarily. The
`Storage Subsystem also includes a Voltage detection circuit
`that monitors the power Signal from the host System to detect
`anomalies therein. The Voltage detection circuit responds to
`detection of an anomaly by asserting a busy signal to block
`the host System from performing write operations to the
`Storage Subsystem. By asserting the busy signal, the Voltage
`detection circuit Substantially ensures that the backup, regu
`lated power provided by the charge pump will be Sufficient
`for the controller to complete all outstanding operations.
`
`38 Claims, 2 Drawing Sheets
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`HOST
`SYSTEM
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`WOTAGE
`DETECTION
`CIRCU
`READY/BUSY CC
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`52
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`OPTONAL
`BATTERY OR
`CAPACTIVE
`ARRAY
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`NON-WOAILE MEMORY SUBSYSTEM
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`R/B
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`CONTROLLER
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`MEMORY
`(E.G. FLASH)
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`Petitioners
`Ex. 1038, p. 1
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`U.S. Patent
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`Feb. 15, 2005
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`Sheet 1 of 2
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`US 6,856,556 B1
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`DETECTION
`CIRCUIT
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`50
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`READY/BUSYC£
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`HOST
`SYSTEM
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`iy CHARGE guy
`PUMP
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`MEMORY
`(E.G. FLASH)
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` OPTIONAL
`BATTERY OR
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`CAPACITIVE
`ARRAY
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`Petitioners
`Ex. 1038, p. 2
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`U.S. Patent
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`Feb. 15, 2005
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`Sheet 2 of 2
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`US 6,856,556 B1
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`CHARGEoy
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`PUMP
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`DISK DRIVE
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`VOLTAGE
`DETECTION
`CIRCUIT
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`BUFFER
`(RAM)
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`Petitioners
`Ex. 1038, p. 3
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`US 6,856.556 B1
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`2
`By asserting the busy signal, the voltage detection circuit
`Substantially ensures that backup power provided by the
`charge pump (and by the battery and/or capacitive array, if
`provided) will be sufficient for the controller to complete all
`outstanding operations. The likelihood that data will be lost
`as the result of the power signal anomaly is therefore
`significantly reduced.
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`1O
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`BRIEF DESCRIPTION OF THE DRAWINGS
`Specific embodiments of the invention will now be
`described with reference to the following drawings, which
`are intended to illustrate and not limit the invention:
`FIG. 1 illustrates the design of a non-volatile solid state
`memory Subsystem according to one embodiment of the
`invention; and
`FIG. 2 illustrates the design of a hard disk drive sub
`System according to another embodiment of the invention.
`
`1.
`STORAGE SUBSYSTEM WITH EMBEDDED
`CIRCUIT FOR PROTECTING AGAINST
`ANOMALIES IN POWER SIGNAL FROM
`HOST
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to circuits from protecting
`Storage Subsystems, Such as but not limited to flash memory
`cards, from damage and data loss caused by irregularities in
`a power signal provided by a host.
`2. Description of the Related Art
`A Significant problem in the area of storage subsystems
`relates to data loss, data corruption, and circuitry damage
`caused by interruptions and other irregularities in the power
`Signal Supplied by the host system. For example, in the
`context of a flash memory Subsystem, an unexpected power
`loSS can cause a sector write operation to terminate
`prematurely, resulting in a mismatch between a sector's data
`and ECC portions. In addition to losing the write data, the
`memory Subsystem's controller may thereafter respond to
`the ECC mismatch condition by treating the sector as
`defective, and unnecessarily replacing the sector with a
`Spare Sector. Incomplete Sector write operations can also
`result in data loss and Sector replacement in disk drives that
`Store data on a rotating medium. Other types of power signal
`anomalies, Such as power Surges and spikes, can additionally
`cause permanent damage to the circuitry of the storage
`Subsystem.
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`SUMMARY OF THE INVENTION
`The present invention provides a circuit and associated
`method for protecting a storage Subsystem from irregulari
`ties in a power signal Supplied by a host system. The
`invention may be embodied within a variety of different
`types of storage Subsystems, including but not limited to
`non-volatile Solid state memory cards (such as but not
`limited to those that comply with the CompactFlash,
`PCMCIA, SmartMedia, MultiMediaCard, Secure.Digital and
`Memory Stick card specifications), volatile and non-volatile
`Solid-state storage products in disk drive form factors,
`electro-mechanical disk drives, and volatile and non-volatile
`Solid-State storage products in a variety of industry standard
`and custom form factors. No modifications are needed to the
`host System.
`In one embodiment, the storage Subsystem includes a
`charge pump circuit that receives the power signal from a
`host System, and generates a regulated power signal that is
`provided to the storage Subsystem's controller (and possibly
`to other active components of the storage subsystem). When
`the power signal from the host is interrupted, the charge
`pump circuit acts as a backup power Source such that the
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`Storage Subsystem can continue to operate temporarily. A
`rechargeable battery and/or a capacitive array may also be
`provided as additional Sources of backup power. In addition
`to providing backup power, the charge pump circuit protects
`the controller from potential damage caused by power
`Surges and Spikes.
`The storage Subsystem in the preferred embodiment also
`includes a Voltage detection circuit that monitors the power
`Signal from the host system to detect anomalies. The voltage
`detection circuit responds to detection of a power signal
`anomaly by asserting a busy signal to block the host system
`from performing write operations to the storage subsystem.
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`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`FIG. 1 illustrates a solid state memory subsystem 30
`according to one embodiment of the invention. The memory
`Subsystem 30 may, for example, be a flash memory card that
`conforms to one of the aforementioned card specifications,
`although the invention is not so limited. The memory
`Subsystem plugs into a slot of, or otherwise attaches to, a
`host system 32 (hereinafter “host”). The host may be any
`type of conventional System or device that accepts the
`memory Subsystem, and need not include any special hard
`Ware or Software for implementing the present invention.
`The interface between the memory subsystem 30 and the
`host 32 includes the following conventional signal lines: a
`Set of address/data/control lines 34 for transferring data; at
`least one power line 36 over which the host provides a power
`Signal to the memory Subsystem; and a ready/busy signal
`line 38 that is driven by the memory subsystem to notify the
`host of the Subsystem's current status. In implementations in
`which the particular interface does not include an actual
`“ready/busy' signal, a different signal or combination of
`Signals may be used to notify the host of the memory
`Subsystem's ready/busy status.
`AS is conventional, the memory Subsystem 30 includes a
`controller 40 that controls, an array of Solid state, non
`volatile memory 42, which may be flash memory or another
`type of EEPROM memory. A conventional flash memory
`controller 40 may be used, as no special controller circuitry
`or functionality is needed in the illustrated embodiment. In
`accordance with the invention, the memory subsystem 30
`also includes the following components to protect against
`anomalies in the power signal Supplied by the host: a charge
`pump circuit 46, a Voltage detection circuit 48, and a logic
`gate or Switch 50. The Switch is shown for illustrative
`purposes as an OR gate, although other types of gates and
`Switches may be used. The charge pump circuit 46 (“charge
`pump"), voltage detection circuit 48, and switch 50 may be
`integrated within a single analog ASIC (application specific
`integrated circuit), possibly together with other components
`of the memory subsystem. As depicted by block 52 in the
`drawing, an optional battery or capacitive array may also be
`included to provide an additional level of protection against
`power anomalies.
`As illustrated in FIG. 1, the charge pump 46 receives the
`power Signal Viv from the host 32, and Supplies a regulated,
`Substantially-constant power signal V to the controller
`40- and possibly to other active components of the
`
`Petitioners
`Ex. 1038, p. 4
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`US 6,856.556 B1
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`memory Subsystem, Such as a volatile memory used as a
`buffer (not shown). Preferably, the charge pump is designed
`Such that the Voltage V. Supplied to the controller 40 is
`maintained at the ideal level (e.g., 5.4 volts) in the event of
`a brief interruption, drop, increase, or Spike in the Voltage
`V. Supplied by the host 32. In addition, the charge pump is
`preferably designed to protect against Sustained Voltage
`drops, for example, in one embodiment, the charge pump is
`capable of maintaining V at 5.4 Volts indefinitely as long
`as V, exceeds 0.7 volts. The charge pump 46 thus allows
`the memory Subsystem 30 to continue to operate during
`certain types of power anomalies, including brief power
`interruptions, Spikes and Sustained voltage drops. In
`addition, the charge pump 46 protects the controller 40 from
`being damaged by Spikes and Surges in the power Signal
`provided by the host.
`The charge pump 46 preferably is or comprises a DC-to
`DC Step-up/step-down converter. Examples of commer
`cially available charge pump devices that may be used
`include the ILC6363CIR50 and ILC6383CIRADJ from
`Fairchild and the MAX849, MAX1705 from Maxim. As is
`known in the art, the charge pump may optionally include or
`be followed by a low drop-out (LDO) voltage regulator (not
`shown) to provide greater output voltage stability. This LDO
`Voltage regulator may be provided in-line between the
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`charge pump's output and the controller's power input,
`downstream from the optional battery or capacitive array 52
`if provided. One example of a Voltage regulator device that
`may be used is a Seiko Epson S80827C.
`The voltage detection circuit 48 is responsible for detect
`ing anomalies in the power Signal V. Supplied by the host
`on line 36, and for driving the ready/busy signal to the
`"busy State when Such anomalies are detected. A conven
`tional Voltage detection circuit may be used. The Voltage
`detection circuit 48 may be designed to generate a "busy
`Signal whenever Vy falls below a certain level, Such as 2.6
`or 2.7 volts. The voltage detection circuit may also be
`designed to generate a busy signal when the Voltage exceeds
`a certain level, and/or when other types of anomalies are
`detected. To inhibit rapid transitions between the “ready”
`and “busy States, the Voltage detection circuit may be
`designed to provide a degree of hysteresis, and/or to hold its
`output for a particular time period after a State transition.
`The logic switch 50 logically combines (e.g., ORs) the
`ready/busy Signals generated by the Voltage detection circuit
`48 and the controller 40 to generate the ready/busy signal
`provided to the host 32 on line 38. Specifically, if a busy
`Signal is generated by the Voltage detection circuit 48, the
`controller 40, or both the voltage detection and the
`controller, a busy Signal is provided to the host 32. AS is
`known in the art and defined by various interface
`Specifications, the host will not perform new write opera
`tions to the memory subsystem when the “busy state is
`asserted. Thus, the host 32 is prevented from performing
`write operations to the memory Subsystem when Voltage
`anomalies are detected and Signaled by the Voltage detection
`circuit 48. AS mentioned above, in implementations in which
`the particular host-Subsystem interface does not include a
`“ready/busy Signal, the ready/busy status of the memory
`Subsystem 30 may be communicated to the host using a
`different Signal line or combination of Signal lines.
`The illustrated memory subsystem 30 responds to power
`Signal anomalies generally as follows. Upon detecting the
`anomaly, the Voltage detection circuit 48 generates a busy
`Signal on line 36, causing the host to refrain from writing or
`reading data to/from the memory subsystem 30. Despite the
`anomaly in the power input Signal, the charge pump 46
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`continues to provide a near-constant Voltage V to the
`controller 40 (for at least a minimum time period T, as
`described below). Because new write operations are
`inhibited, and because the charge pump continues to provide
`a regulated power Signal to the controller 40, the possibility
`of data corruption (e.g., as the result of incomplete write
`operations) is significantly reduced. The charge pump also
`serves to protect the controller 40 and other circuitry from
`damage caused by Voltage Surges and Spikes.
`Even if the anomaly is in the form of a complete inter
`ruption or termination of power from the host 32, the charge
`pump 46 continues to provide power to the controller 40
`(and possibly to other active components, as mentioned
`above) for at least the minimum time period, T., needed
`to complete all outstanding operations. For example, if a
`write operation is in progreSS and the memory Subsystem 30
`has write data stored in its volatile RAM buffer (not shown),
`backup power will be provided for a time period sufficient
`for the controller 40 to finish writing this data to the
`EEPROM memory 42, and if necessary, to back up any
`configuration data Stored in Volatile memory. The memory
`Subsystem 30 may also use the backup power to perform a
`shut down Sequence. The value of T. needed to protect
`against data loSS will typically be in the range of Several
`milliseconds to Several Seconds, depending upon the design
`and type of the memory subsystem 30.
`As depicted by block 52 in FIG. 1, a battery or a
`capacitive array may be connected between ground and the
`output of the charge pump 46 to extend the time duration for
`which backup power is provided. If a battery is used, the
`battery may be a Small, rechargeable, watch-type battery that
`is embedded within the memory Subsystem's housing.
`Typically, a battery of this type can provide Several minutes
`of backup power to the controller 40. If a capacitive array is
`provided, the capacitive array may consist of a bank or array
`of capacitors, and may provide tens to thousands of micro
`farads of capacitance. The battery or capacitive array, if
`provided, is connected So as to become or remain charged
`from the output of the charge pump 46.
`The protection circuitry illustrated in FIG. 1 is particu
`larly useful for protecting against power interruptions
`caused by the removal or movement of the memory Sub
`system 30 by the user. The protection circuitry also protects
`against power anomalies emanating from or experienced by
`the host, and may therefore also find utility in memory
`Subsystems that are not intended to be removed by the user.
`FIG. 2 illustrates an embodiment in which the power
`anomaly protection circuitry is included within a hard disk
`drive subsystem 30, such as an ATA, Serial ATA, SCSI, or
`Serial-Attached SCSI disk drive. In this embodiment, the
`controller 40 is a conventional disk drive controller that
`controls reads and writes of data to/from a rotating magnetic
`disk 60. In the illustrated embodiment, the controller 40'
`accesses a buffer or cache 62 formed from volatile Solid State
`RAM. The design and operation of the power anomaly
`protection circuitry in this disk drive embodiment may be
`substantially the same as described with reference to FIG. 1,
`except that the charge pump (and the optional battery or
`capacitive array 52) also provide backup power to the
`spindle and actuator motors 64, 66 of the disk drive 30'.
`The protection circuitry and methods of the present inven
`tion may also be incorporated into other types of Storage
`Subsystems, including volatile Storage Subsystems that Store
`data within DRAM or SRAM.
`Although this invention has been described in terms of
`certain preferred embodiments and applications, other
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`Petitioners
`Ex. 1038, p. 5
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`S
`embodiments and applications that are apparent to those of
`ordinary skill in the art, including embodiments which do
`not provide all of the features and advantages Set forth
`herein, are also within the Scope of this invention.
`Accordingly, the Scope of the present invention is intended
`to be defined only by reference to the appended claims.
`What is claimed is:
`1. A Storage Subsystem, comprising:
`a controller that writes data to, and reads data from, a
`non-volatile Storage medium;
`a charge pump circuit that receives a power signal from a
`host System, and generates a regulated power Signal
`that is provided to the controller, wherein the charge
`pump circuit is capable of maintaining the regulated
`power signal to the controller when the power Signal
`from the host System is interrupted, Such that the charge
`pump circuit acts as a backup power Supply when
`power from the host System is interrupted; and
`a Voltage detection circuit that monitors the power Signal
`from the host System to detect anomalies therein, and
`responds to detection of Such an anomaly by asserting
`a signal to the host System to block the host System
`from performing write operations to the Storage Sub
`System.
`2. The Storage Subsystem as in claim 1, wherein the
`Voltage detection circuit, by asserting the Signal to block the
`host System, Substantially ensures that backup power pro
`vided by the charge pump circuit will be sufficient for the
`controller to complete all outstanding operations.
`3. The Storage Subsystem as in claim 1, further comprising
`a logic circuit that generates the Signal to the host System
`when either or both of the following occur: (a) a busy signal
`is generated by the Voltage detection circuit; (b) a busy
`Signal is generated by the controller.
`4. The Storage Subsystem as in claim 1, further comprising
`a rechargeable battery that acts as an additional Source of
`backup power to the controller, Said battery coupled to the
`charge pump Such that the battery is charged when power is
`Supplied by the host System.
`5. The Storage Subsystem as in claim 1, further comprising
`a capacitive array that acts as an additional Source of backup
`power to the controller, Said capacitive array coupled to the
`charge pump Such that the capacitive array is charged when
`power is Supplied by the host System.
`6. The Storage Subsystem as in claim 1, wherein the
`non-volatile Storage medium comprises flash memory.
`7. The Storage Subsystem as in claim 1, wherein the
`non-volatile Storage medium comprises a magnetic medium.
`8. The Storage Subsystem as in claim 1, wherein the
`Storage Subsystem is a flash memory card.
`9. The storage subsystem as in claim 1, wherein the
`charge pump and the Voltage detection circuit are integrated
`within a common analog application-specific integrated cir
`cuit (ASIC).
`10. The storage subsystem as in claim 1, wherein the
`charge pump circuit comprises a step-up/step-down DC-to
`DC converter.
`11. The Storage Subsystem as in claim 1, further compris
`ing a Voltage regulator connected between the charge pump
`circuit and the controller to further regulate the regulated
`power Signal provided to the controller.
`12. A method of responding to an anomaly in a power
`Signal provided by a host System to a Storage Subsystem, the
`method comprising, within the Storage Subsystem:
`receiving the power Signal from the host System, said host
`System being Separate from the Storage Subsystem and
`pluggably connecting to the Storage Subsystem;
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`detecting the anomaly in the power Signal with a detection
`circuit of the Storage Subsystem;
`while the anomaly is detected by the detection circuit,
`asserting a signal to the host System to inhibit the host
`System from writing data to the Storage Subsystem; and
`during the anomaly, providing power to a controller of the
`Storage Subsystem from at least one Source of backup
`power contained within Storage Subsystem, to allow the
`Storage Subsystem to complete operations that were in
`progreSS when the anomaly was detected.
`13. The method of claim 12, wherein the at least one
`Source of backup power comprises a charge pump circuit.
`14. The method of claim 12, wherein the at least one
`Source of backup power further comprises a rechargeable
`battery embedded within the Storage Subsystem.
`15. The method of claim 12, wherein the at least one
`Source of backup power further comprises a capacitive array
`embedded within the Storage Subsystem.
`16. The method of claim 12, wherein the charge pump
`circuit comprises a step-up/step-down DC-to-DC converter.
`17. The method of claim 12, wherein the step of providing
`power to a controller of the Storage Subsystem from at least
`one Source of backup power is performed for a Sufficient
`time period to Substantially ensure that the Storage Sub
`System will complete all outstanding operations.
`18. The method of claim 12, wherein the storage Sub
`System is a Solid State nonvolatile memory card.
`19. The method of claim 12, wherein the storage Sub
`System is a disk drive.
`20. The method of claim 12, wherein the signal is a busy
`Signal used to notify the host System that the Storage
`Subsystem is currently in a busy State.
`21. The method of claim 12, wherein the signal is pro
`Vided to the host System on a ready/busy Signal line of a
`Standard card interface that interconnects the host System
`and the Storage Subsystem.
`22. The method of claim 12, wherein the Signal is gen
`erated by a logic circuit that generates the Signal when either
`or both of the following occur: (a) a busy signal is generated
`by the detection circuit; (b) a busy signal is generated by the
`controller.
`23. The method of claim 12, wherein the anomaly is a
`termination of power from the host System.
`24. The method of claim 23, wherein the method further
`comprises the Storage Subsystem using the power from the
`at least one Source of backup power to perform a shut down
`Sequence following completion of Said operations.
`25. The method of claim 12, wherein, by asserting the
`Signal to the host System, the Storage Subsystem additionally
`inhibits the host System from reading data from the Storage
`Subsystem.
`26. The Storage Subsystem as in claim 1, wherein the
`charge pump circuit is responsive to termination of the
`power Signal from the host System by continuing to provide
`power to the controller for at least a time period needed to
`complete all outstanding operations.
`27. The storage subsystem as in claim 1, wherein the
`Storage Subsystem is responsive to termination of the power
`Signal from the host System by using backup power provided
`by the charge pump circuit to, at least, complete an out
`Standing write operation.
`28. The storage subsystem as in claim 1, wherein the
`Storage Subsystem is responsive to termination of the power
`Signal from the host System by using backup power provided
`by the charge pump circuit to, at least, perform a shut down
`Sequence.
`29. The storage subsystem as in claim 1, wherein the
`Storage Subsystem is a Solidstate memory card that plugs
`into a slot of the host System.
`
`Petitioners
`Ex. 1038, p. 6
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`30. The storage subsystem as in claim 29, wherein the
`controller writes data to, and reads data from, the non
`Volatile Storage medium in response to commands received
`from the host system.
`31. The storage subsystem as in claim 29, wherein the
`memory card complies with at least one of the following
`card specifications: CompactFlash, PCMCIA, SmartMedia,
`MultiMediaCard, SecureDigital, Memory Stick.
`32. The Storage Subsystem as in claim 1, wherein the
`Signal asserted by the Voltage detection circuit is provided
`on a ready/busy Signal line used to inform the host System
`of whether the Storage Subsystem in ready to receive a next
`command.
`33. A Solid State memory Subsystem, comprising:
`a Solid State, non-volatile memory array;
`a controller that writes data to, and reads data from, the
`non-volatile memory array in response to operations
`initiated by a host System;
`a power regulation circuit that receives a power Signal
`from the host System and generates a regulated power
`Signal that is provided to the controller, wherein the
`power regulation circuit is capable of maintaining the
`regulated power Signal to the controller when the power
`Signal from the host System is interrupted, Such that the
`power regulation circuit acts as a backup power Supply
`when power from the host System is interrupted;
`a Voltage detection circuit that monitors the power Signal
`from the host System to detect anomalies therein; and
`
`15
`
`25
`
`US 6,856.556 B1
`
`8
`a signal generation circuit that generates a busy Signal to
`the host system when either or both of the following
`occur: (a) an anomaly is detected by the Voltage detec
`tion circuit, (b) the controller is in a busy State.
`34. The Solid state memory Subsystem as in claim 33,
`wherein the busy Signal is a signal that, when asserted, Stops
`the host System from instructing the memory Subsystem to
`perform memory access operations.
`35. The Solid state memory Subsystem as in claim 33,
`further comprising a housing that houses the non-volatile
`memory array, the controller, the power regulation circuit,
`the Voltage detection circuit, and the Signal generation
`circuit, Said housing configured for insertion into a slot of
`the host System.
`36. The Solid state memory Subsystem as in claim 33,
`wherein the memory Subsystem is a memory card that
`complies with a CompactFlash, PCMCIA, SmartMedia,
`MultiMediaCard, SecureDigital or Memory Stick card
`Specification.
`37. The Solid state memory Subsystem as in claim 33,
`wherein the power regulation circuit comprises a charge
`pump circuit.
`38. The Solid state memory Subsystem as in claim 33,
`wherein the busy signal is provided to the host System on a
`ready/busy Signal line of an industry-Standard interface.
`
`Petitioners
`Ex. 1038, p. 7
`
`