JEDEC
`STANDARD
`
`FBDIMM:
`Advanced Memory Buffer (AMB)
`
`JESD82-20
`
`MARCH 2007
`
`SPECIAL DISCLAIMER: JEDEC has received information that
`certain patents or patent applications may be relevant to this
`standard, and, as of the publication date of this standard, no
`statements regarding an assurance or refusal to license such
`patents or patent applications have been provided.
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective
`users of the standard should act accordingly.
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Petitioners
`Ex. 1027, p. Cover
`
`

`

`NOTICE
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`
`Petitioners
`Ex. 1027, p. Notice
`
`

`

`PLEA SE!
`
`D O N ’T V IO LA TE
`TH E
`LA W !
`
`This docum ent is copyrighted by the JED EC Solid State Technology A ssociation
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`
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`or call (703) 907-7559
`
`Petitioners
`Ex. 1027, p. Copyright
`
`

`

`Special Disclaimer
`
`JEDEC has received information that certain patents or patent
`applications may be relevant to this standard, and, as of the
`publication date of this standard, no statements regarding an
`assurance or refusal to license such patents or patent applications
`have been provided.
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective users
`of the standard should act accordingly.
`
`§
`
`Petitioners
`Ex. 1027, p. Disclaimer
`
`

`

`JEDEC Standard No. 82-20
`
` Table of Contents
`Table of Contents ............................................................................................................................. i
`
`List of Tables ................................................................................................................................... v
`
`List of Figures ................................................................................................................................ vii
`
`1
`
`2
`
`3
`
`Introduction.........................................................................................................................1
`Advanced Memory Buffer Overview.............................................................................1
`Advanced Memory Buffer Functionality .......................................................................1
`1.2.1
`Advanced Memory Buffer ......................................................................................1
`1.2.2
`Transparent Mode for DRAM Test Support...........................................................1
`1.2.3 Debug and Logic Analyzer Interface .....................................................................2
`1.2.4 DDR SDRAM.........................................................................................................2
`Advanced Memory Buffer Block Diagram ....................................................................2
`Interfaces .....................................................................................................................4
`1.4.1
`FBD High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces ..................4
`1.4.2 DDR2 Channel ......................................................................................................4
`1.4.3
`SMBus Slave Interface ..........................................................................................4
`References...................................................................................................................5
`Glossary .......................................................................................................................5
`FBD Channel Interface .......................................................................................................9
`Advanced Memory Buffer Support for FBD Operating Modes .....................................9
`Channel Initialization ....................................................................................................9
`Channel Protocol..........................................................................................................9
`2.3.1 General..................................................................................................................9
`2.3.2
`Timeouts during TS0 .............................................................................................9
`2.3.3 Recalibrate state considerations ...........................................................................9
`2.3.4
`Address Mapping of DDR Commands to DRAMs ...............................................11
`2.3.5
`FBD L0s State .....................................................................................................11
`Reliability, Availability, and Serviceability...................................................................12
`2.4.1 General................................................................................................................12
`2.4.2 Channel Error Detection and Logging .................................................................12
`Channel Configuration ...............................................................................................12
`2.5.1 Re-sync and Resample Modes ...........................................................................12
`2.5.2 Other Channel Configuration Modes ...................................................................13
`2.5.3
`Lane to Lane Skew on a Channel .......................................................................13
`Repeater Mode ..........................................................................................................13
`Performance...............................................................................................................14
`2.7.1
`Idle Memory Read Latency..................................................................................14
`AMB Components of Channel Latency ......................................................................15
`2.8.1 Command to Data Delay Calculation...................................................................15
`2.8.2 Channel Throughput............................................................................................18
`DDR Interface...................................................................................................................19
`Advanced Memory Buffer DDR Interface Overview...................................................19
`Data Mapping.............................................................................................................19
`3.2.1 Data Mask ...........................................................................................................19
`Command / Address Outputs.....................................................................................20
`3.3.1 CKE Output Control.............................................................................................21
`3.3.2 Memory Controller / BIOS requirements..............................................................21
`DQS IO and DM Outputs ...........................................................................................21
`
`1.1
`1.2
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`1.3
`1.4
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`1.5
`1.6
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`2.1
`2.2
`2.3
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`2.4
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`2.5
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`2.6
`2.7
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`2.8
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`3.1
`3.2
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`3.3
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`3.4
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`-i-
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`Petitioners
`Ex. 1027, p. i
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`

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`JEDEC Standard No. 82-20
`
`3.5
`
`3.6
`3.7
`
`3.8
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`3.9
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`4.1
`
`4.2
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`4.3
`4.4
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`4.5
`4.6
`4.7
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`5.1
`
`5.2
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`5.3
`5.4
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`6.1
`
`Refresh.......................................................................................................................22
`3.5.1
`Self-Refresh During Channel Reset ....................................................................22
`3.5.2
`Automatic Refresh ...............................................................................................23
`Back to Back Turnaround Time..................................................................................23
`DDR Calibration .........................................................................................................24
`3.7.1 DRAM Initialization and (E)MRS..........................................................................24
`3.7.2
`Automatic DDR Bus Calibration...........................................................................25
`3.7.3
`S3 Recovery Configuration Registers..................................................................25
`3.7.4 Receive Enable Calibration .................................................................................26
`3.7.5 DQS Delay Calibration ........................................................................................26
`DDR MEMBIST ..........................................................................................................26
`3.8.1 MEMBIST Features .............................................................................................27
`DIMM Organization ....................................................................................................29
`Electrical, Power, and Thermal.........................................................................................31
`Electrical DC Parameters...........................................................................................31
`4.1.1
`Absolute maximum ratings ..................................................................................31
`4.1.2 Normal Mode .......................................................................................................32
`4.1.3
`S3 current Specification.......................................................................................39
`FBD Channel Interface...............................................................................................40
`4.2.1
`FBD Electrical Timing Specifications...................................................................40
`4.2.2
`AMB Latency Parameters....................................................................................40
`DDR2 DRAM Interface Electrical Specifications ........................................................45
`DDR2 Electrical Output Timing Specifications ...........................................................46
`4.4.1 Description of DQ/DQS Alignment.......................................................................46
`4.4.2 Description of ADD/CMD/CNTL Outputs.............................................................46
`4.4.3
`Test Load Specification .......................................................................................46
`4.4.4
`tDVA and tDVB Parameter Description ...............................................................46
`4.4.5
`tjit and tjitHP Parameter Description....................................................................47
`4.4.6
`tCVA, tCVB, tECVA and tECVB Parameter Description......................................47
`4.4.7
`tDQSCK Timing Parameter Description ..............................................................48
`4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS (Read Operation) ....48
`4.4.9 Write Preamble Duration .....................................................................................49
`4.4.10 Write Postamble Duration....................................................................................49
`4.4.11 Advance Memory Buffer Component Electrical Timing Summary.......................50
`4.4.12 Reference DDR2 Interface Package Trace Lengths ...........................................52
` SMBUS Interface ......................................................................................................53
`Misc I/O (1.5 CMOS Driver) .......................................................................................53
`Thermal Diode and Analog to Digital Converter (ADC)..............................................53
`4.7.1
`Thermal Sensor Effects on the Advanced Memory Buffer’s Functional Behavior54
`Error Handling ..................................................................................................................55
`Types of Errors and Responses.................................................................................55
`5.1.1
`FBD Link Errors ...................................................................................................55
`5.1.2 DDR Errors ..........................................................................................................56
`5.1.3 Host Protocol Errors ............................................................................................56
`5.1.4 Other Errors.........................................................................................................57
`Error Logging .............................................................................................................58
`5.2.1
`Error Logging Procedure .....................................................................................58
`Fail Over Mode Support .............................................................................................58
`Failback to Pass-Thru ................................................................................................58
`Transparent Mode ............................................................................................................59
`Transparent Mode......................................................................................................59
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`4
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`5
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`6
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`-ii-
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`Petitioners
`Ex. 1027, p. ii
`
`

`

`JEDEC Standard No. 82-20
`
`6.2
`
`7.1
`
`8.1
`8.2
`8.3
`8.4
`8.5
`8.6
`8.7
`8.8
`
`8.9
`
`9.1
`
`Block Diagram .....................................................................................................59
`6.1.1
`Transparent Mode Signal Definitions ..................................................................60
`6.1.2
`Transparent Mode to FBD Pin Mapping ..............................................................60
`6.1.3
`6.1.4 Clock Frequency and Core Timing ......................................................................61
`6.1.5
`Transparent mode timing.....................................................................................61
`6.1.6
`Error reporting .....................................................................................................66
`6.1.7
`Transparent mode IO specifications....................................................................68
`6.1.8
`IO implementation guidelines ..............................................................................69
`Transparent Mode Control and Status Registers.......................................................70
`SMBus Interface ...............................................................................................................71
`System Management Access.....................................................................................71
`7.1.1
`SMBus 2.0 Specification Compatibility ................................................................71
`7.1.2
`Supported SMBus Commands ............................................................................71
`7.1.3
`FBD AMB Register Access Protocols..................................................................72
`7.1.4
`SMBus Error Handling.........................................................................................75
`7.1.5
`SMBus Resets.....................................................................................................75
`Clocking............................................................................................................................77
`Advanced Memory Buffer Clock Domains .................................................................77
`PLL Clocks .................................................................................................................77
`Reference Clock.........................................................................................................77
`FBD Lane Frame Clocks............................................................................................77
`Clock Ratios ...............................................................................................................77
`DDR DRAM Clock Support ........................................................................................78
`Clock Pins ..................................................................................................................78
`. PLL Requirements ...................................................................................................78
`8.8.1
`Jitter.....................................................................................................................78
`8.8.2
`PLL Bandwidth Requirements .............................................................................79
`8.8.3
`External Reference..............................................................................................79
`8.8.4
`Spread Spectrum Support ...................................................................................79
`Analog Power Supply Pins.........................................................................................79
`Pin Descriptions................................................................................................................81
`Pin Description ...........................................................................................................81
`Reset ................................................................................................................................85
`10.1
`Introduction ................................................................................................................85
`10.2
`Platform Reset Functionality ......................................................................................85
`10.2.1 Platform RESET# Requirements.........................................................................85
`10.2.2 Advanced Memory Buffer RESET# Requirements..............................................85
`10.2.3 Power-Up and Suspend-to-RAM Considerations ................................................86
`10.3
`Reset Types ...............................................................................................................86
`10.4
`Pads Controlling Reset ..............................................................................................86
`10.4.1 RESET# Pad .......................................................................................................86
`10.4.2 Primary FBD Link ................................................................................................86
`10.5
`Details ........................................................................................................................86
`10.5.1 Cold Power-Up Reset Sequence.........................................................................86
`10.6
`Timing Diagrams ........................................................................................................88
`10.7
`I/O Initialization...........................................................................................................88
`10.7.1 FBD Channel Initialization ...................................................................................88
` Registers .........................................................................................................................89
`11.1
`Access Mechanisms ..................................................................................................89
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`7
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`8
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`9
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`10
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`11
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`-iii-
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`Petitioners
`Ex. 1027, p. iii
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`

`

`JEDEC Standard No. 82-20
`
`11.1.1 Conflict Resolution and Usage Model Limitations ...............................................89
`11.1.2 FBD Data on Configuration Read Returns ..........................................................89
`11.1.3 Non-Existent Register Bits...................................................................................89
`11.1.4 Register Attribute Definition.................................................................................90
`11.1.5 Binary Number Notation ......................................................................................90
`11.1.6 Function Mapping ................................................................................................90
`11.2
`PCI Standard Header Identification Registers (Function 0) .......................................99
`11.2.1 VID: Vendor Identification Register .....................................................................99
`11.2.2 DID: Device Identification Register....................................................................100
`11.2.3 RID: Revision Identification Register .................................................................100
`11.2.4 CCR: Class Code Register................................................................................100
`11.2.5 HDR: Header Type Register..............................................................................101
`11.3
`FBD Link Registers (Function 1) ..............................................................................101
`11.3.1 FBD Link Control and Status .............................................................................101
`11.3.2 Error Registers ..................................................................................................115
`11.3.3 PERSONALITY BYTES loaded from the SPD ..................................................117
`11.3.4 Advanced Memory Buffer Hardware Configuration Registers...........................119
`11.4
`Implementation Specific FBD Registers (Function 2) ..............................................121
`11.5
`DDR and Miscellaneous Registers (Function 3) ......................................................121
`11.5.1 Memory BIST Registers ....................................................................................121
`11.5.2 Memory Registers .............................................................................................130
`11.5.3 Thermal Sensor Registers.................................................................................136
`11.6
`Implementation Specific DDR Initialization and Calibration Registers (Function 4).139
`11.6.1 DDR Calibration.................................................................................................139
`11.7
`DFX Registers (Function 5)......................................................................................142
`11.7.1 Transparent Mode Registers .............................................................................142
`11.7.2 Logic Analyzer Interface (LAI) Registers ...........................................................143
`11.7.3 Error Injection Registers ....................................................................................154
`11.8
`Bring-up and Debug Registers (Function 6).............................................................154
`11.8.1 Southbound FBD IBIST registers ......................................................................154
`11.8.2 Northbound FBD IBIST registers.......................................................................160
`Ballout and Package Information....................................................................................167
`12.1
`655-ball FBGA (23x29 Array, 19.5x24.5 mm Body Size, 0.8 mm Pitch, MO-261A Variation AA/
`BA) Pin configuration 179
`Pin Assignments for the Advanced Memory Buffer (AMB) ......................................168
`Package Information ................................................................................................176
`
`12.2
`12.3
`
`12
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`-iv-
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`Petitioners
`Ex. 1027, p. iv
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`

`

`JEDEC Standard No. 82-20
`
` List of Tables
`Example FBD-667 Channel Idle Memory Read Latencies............................................................... 14
`
`DQS association with DQ/CB pins in x8 and x4 mode..................................................................... 22
`
`MEMBIST Feature Summary ........................................................................................................... 27
`
`Absolute maximum ratings over operating free-air temperature range (see Note 1) ....................... 31
`
`Advanced Memory Buffer Normal Mode DC Electrical Parameters................................................. 32
`
`AMB Power Specification Parameters and Test Conditions ............................................................ 32
`
`Advanced Memory Buffer FBD Timing/Electrical ............................................................................. 40
`
`Recommended operating conditions for DRAM Interface................................................................ 45
`
`tDVA and tDVB Timing Diagram ...................................................................................................... 47
`
`tjit and tjitHP Timing Diagram........................................................................................................... 47
`
`tCVA and tCVB Timing Diagram ...................................................................................................... 47
`
`tECVA and tECVB Timing Diagram ................................................................................................. 48
`
`TDQSCK Timing Diagram................................................................................................................ 48
`
`DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram..................................... 49
`
`Write Preamble Duration Timing Diagram........................................................................................ 49
`
`Write Postamble Duration Timing Diagram...................................................................................... 50
`
`Advance Memory Buffer Component DDR2 Electrical Timing Specifications.................................. 50
`
`Advance Memory Buffer DDR2 Package Lengths ........................................................................... 52
`
`Recommended operating conditions for SMBUS Interface.............................................................. 53
`
`Recommended operating conditions for RESET and BFUNC pins.................................................. 53
`
`Link Errors in Initialization ................................................................................................................ 55
`
`Link Errors in Normal Operation....................................................................................................... 55
`
`DDR Errors....................................................................................................................................... 56
`
`Host Protocol Errors......................................................................................................................... 57
`
`Other Errors ..................................................................................................................................... 57
`
`Additional Signals in Transparent Mode .......................................................................................... 60
`
`Mapping of FBD Pins in Transparent Mode ..................................................................................... 61
`
`Mapping of burst position bits to error capture................................................................................. 67
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`2
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`3
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`4
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`5
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`6
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`7
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`8
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`9
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`10
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`11
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`12
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`13
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`14
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`15
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`16
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`17
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`18
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`19
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`20
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`21
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`22
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`23
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`24
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`25
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`26
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`27
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`28
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`-v-
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`Petitioners
`Ex. 1027, p. v
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`

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`JEDEC Standard No. 82-20
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`29
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`30
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`31
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`32
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`33
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`34
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`35
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`38
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`39
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`40
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`41
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`42
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`43
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`44
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`45
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`46
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`47
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`48
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`49
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`50
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`51
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`52
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`53
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`54
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`55
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`Selection of 8 bit data paths when ENDOUT is set.......................................................................... 68
`
` Transparent mode FB-DIMM interface signaling specifications...................................................... 68
`
`SMBus command Encoding............................................................................................................. 72
`
`SMBus Protocol Addressing fields ................................................................................................... 72
`
`Status Field Encoding for SMBus Reads ......................................................................................... 73
`
`Advanced Memory Buffer Clock Ratios............................................................................................ 78
`
`Clock Pins ........................................................................................................................................ 78
`
`Access to “Non-existent” Register Bits............................................................................................. 89
`
`Register Attributes Definitions.......................................................................................................... 90
`
`Function Mapping Legend................................................................................................................ 91
`
`Function 0: PCI Standard Header Identification Registers............................................................... 92
`
`Function 1: FBD Link Registers ....................................................................................................... 93
`
` Function 2: Implementation Specific FBD Registers....................................................................... 94
`
`Function 3: DDR and Miscellaneous Registers................................................................................ 95
`
`Function 4: Implementation Specific DDR Initialization and Calibration Registers .......................... 96
`
`Function 5: DFX Registers ............................................................................................................... 97
`
`Function 6: IBIST, Bring-up and Debug Registers ........................................................................... 98
`
`Functions 7: FBD DFX/Defeature Registers .................................................................................... 99
`
`Functional mapping of MemBIST data fields by test mode............................................................ 126
`
`MBDATA Failure Address register correspondence to DRAM address......................................... 127
`
`BL4 Column and Chunk correspondence to DRAM address......................................................... 127
`
`BL8 Column and Chunk correspondence to DRAM address......................................................... 127
`
`Functional Characteristics of DCALADDR ..................................................................................... 140
`
`Bit Locations for SB Match and Mask ........................................