( 12 ) United States Patent
`Chen et al .
`
`US 11,016,918 B2
`( 10 ) Patent No .:
`( 45 ) Date of Patent :
`May 25 , 2021
`
`US011016918B2
`
`( 54 ) FLASH - DRAM HYBRID MEMORY MODULE
`( 71 ) Applicant : Netlist , Inc. , Irvine , CA ( US )
`( 72 ) Inventors : Chi - She Chen , Walnut , CA ( US ) ;
`Jeffrey C. Solomon , Irvine , CA ( US ) ;
`Scott H. Milton , Irvine , CA ( US ) ;
`Jayesh Bhakta , Cerritos , CA ( US )
`( 73 ) Assignee : Netlist , Inc. , Irvine , CA ( US )
`Subject to any disclaimer , the term of this
`( * ) Notice :
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`( 21 ) Appl . No .: 17 / 138,766
`( 22 ) Filed :
`Dec. 30 , 2020
`( 65 )
`
`Prior Publication Data
`Apr. 29 , 2021
`US 2021/0124701 A1
`Related U.S. Application Data
`( 63 ) Continuation of application No. 15 / 934,416 , filed on
`Mar. 23 , 2018 , which is a continuation of application
`( Continued )
`
`( 51 ) Int . Ci .
`G06F 13/36
`G06F 13/28
`
`( 52 ) U.S. CI .
`CPC
`
`( 2006.01 )
`( 2006.01 )
`( Continued )
`G06F 13/28 ( 2013.01 ) ; G06F 1/185
`( 2013.01 ) ; G06F 3/0613 ( 2013.01 ) ;
`( Continued )
`( 58 ) Field of Classification Search
`CPC .. GOOF 13/28 ; GO6F 13/4027 ; G06F 13/1694 ;
`G06F 13/4223 ; G06F 12/0638 ;
`( Continued )
`
`( 56 )
`
`EP
`KR
`
`References Cited
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`2,043,099 A
`3,562,555 A
`
`6/1936 Hanna
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`( Continued )
`FOREIGN PATENT DOCUMENTS
`
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`2737383 A2
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`0130873 B1
`( Continued )
`
`OTHER PUBLICATIONS
`Exhibit , Decision Denying Institution of Inter Partes Review , Smart
`Modular Technologies , Inc. v . Netlist , Inc. , Case No. 4 : 13 - cv - 05889
`YGR Document 309-3 , filed Mar. 17 , 2015 , 23 pages .
`( Continued )
`Primary Examiner Hashem Farrokh
`( 74 ) Attorney , Agent , or Firm
`Shami Messinger PLLC
`( 57 )
`ABSTRACT
`In certain embodiments , a memory module includes a
`printed circuit board ( PCB ) having an interface that couples
`it to a host system for provision of power , data , address and
`control signals . First , second , and third buck converters
`receive a pre - regulated input voltage and produce first ,
`second and third regulated voltages . A converter circuit
`reduces the pre - regulated input voltage to provide a fourth
`regulated voltage . Synchronous dynamic random access
`memory ( SDRAM ) devices are coupled to one or more
`regulated voltages of the first , second , third and fourth
`regulated voltages , and a voltage monitor circuit monitors an
`input voltage and produces a signal in response to the input
`voltage having a voltage amplitude that is greater than a
`threshold voltage .
`30 Claims , 22 Drawing Sheets
`
`1010
`
`1020
`
`1042
`
`1040
`
`INAND NAND NAND NAND
`12BWX 1281X 128MX 128x
`8
`8
`8
`8
`
`1030
`
`1032
`---
`DDR2 DDR2 DDR2 DOR2 ODR2 DDR2 DDR2 DDR2
`64x6MXC 64MX8 64MX854MX884NXB 64MX864MX8
`
`FPGA
`
`1062
`
`1070
`
`1060
`
`DATA
`
`ADDR / CONT
`
`SWICH
`
`1052
`
`POWER
`OUTPUT
`
`1090
`
`SWITCH
`
`STEP
`STEP UP
`CAPACITOR
`DOWN
`VOLTAGE
`BANK
`VOLTAGE
`1084 1080 1086
`
`1082
`
`NCU
`
`ADDRICONT
`
`-1050
`
`VOLTAGE
`MONITORI
`
`DATA AODR / CONT
`
`-1022
`
`Standard DIMM interface
`
`Petitioners
`Ex. 1001, p. 1
`
`

`

`US 11,016,918 B2
`Page 2
`
`Related U.S. Application Data
`No. 14 / 840,865 , filed on Aug. 31 , 2015 , now Pat . No.
`9,928,186 , which is a continuation of application No.
`14 / 489,269 , filed on Sep. 17 , 2014 , now Pat . No.
`9,158,684 , which is a continuation of application No.
`13 / 559,476 , filed on Jul . 26 , 2012 , now Pat . No.
`8,874,831 , which is a continuation - in - part of appli
`cation No. 12 / 240,916 , filed on Sep. 29 , 2008 , now
`Pat . No. 8,301,833 , which is a continuation of appli
`cation No. 12 / 131,873 , filed on Jun . 2 , 2008 , now
`abandoned .
`( 60 ) Provisional application No. 60 / 941,586 , filed on Jun .
`1 , 2007 , provisional application No. 61 / 512,871 , filed
`on Jul . 28 , 2011 .
`( 51 ) Int . CI .
`G06F 12/02
`G06F 13/16
`G06F 1/18
`G06F 12/06
`G06F 13/42
`GIIC 7/10
`GIIC 14/00
`G06F 3/06
`G06F 13/40
`( 52 ) U.S. Ci .
`CPC
`
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`G06F 3/0659 ( 2013.01 ) ; G06F 3/0685
`( 2013.01 ) ; G06F 12/0246 ( 2013.01 ) ; G06F
`12/0638 ( 2013.01 ) ; G06F 13/1694 ( 2013.01 ) ;
`G06F 13/4027 ( 2013.01 ) ; G06F 13/4243
`( 2013.01 ) ; GIIC 7/1072 ( 2013.01 ) ; G11C
`14/0018 ( 2013.01 ) ; G06F 2212/205 ( 2013.01 ) ;
`G06F 2212/7208 ( 2013.01 )
`( 58 ) Field of Classification Search
`CPC ... GOOF 12/0246 ; G06F 1/185 ; G06F 3/0613 ;
`G06F 3/0685 ; G06F 3/0659 ; G06F
`2212/7208 ; G06F 2212/205 ; G11C
`7/1072 ; G11C 14/0018
`711/103 , 104 , 105 ; 710/138
`USPC
`See application file for complete search history .
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`
`

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`Ex. 1001, p. 3
`
`

`

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`Mar. 31 , 2019 , 7 pages .
`Restriction Requirement in U.S. Appl . No. 12 / 240,916 , dated Mar.
`31 , 2011 .
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`Global Patent Solutions , Nov. 24 , 2020 , 179 pages .
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`
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`Dec. 18 , 2017 , 1 page .
`Advisory Action in U.S. Appl . No. 12 / 240,916 , dated Mar. 13 , 2012 .
`Amendment and Reply to Office Action , SanDisk Corporation v .
`Netlist , U.S. Appl . No. 13 / 536,173 , IPR2014-00982 ( PTAB ) , dated
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`Amendment and Response to Election Restriction , SanDisk Cor
`poration v . Netlist , Inc. , U.S. Pat . No. 8,301,833 , IPR2014-00994
`1004 ( PTAB ) , dated May 20 , 2011 , 9 pages .
`American Heritage Dictionary of the English Language , Third Ed . ,
`Houghton Mifflin Company , Boston , MA , 1996 , 7 pages .
`Appeals from the USPTO , PTAB in Nos . IPR2014-00882 , IPR2014
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`Charles C. , Multiplexers and Demultiplexers , Ex . 1035 , IPR No.
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`Corrected Petition for Inter Partes Review of Claims 1-30 of U.S.
`Pat . No. 8,301,833 , Declaration of Michael F. Heafey , IPR2014
`01370 ( PTAB ) , filed Sep. 22 , 2014 , 4 pages .
`Corrected Petition for Inter Partes Review of Claims 1-32 of U.S.
`Pat . No. 8,516,187 , IPR2014-01371 ( PTAB ) , Sep. 22 , 2014 , 67
`pages .
`Corrected Petition for Inter Partes Review of Claims 1-32 of U.S.
`Pat . No. 8,516,187 , Declaration of Dr. Nader Bagherzadeh , IPR 2014
`01371 ( PTAB ) , filed Sep. 22 , 2014 , 306 pages .
`Decision Denying Institution of Inter Partes Review , U.S. Pat . No.
`8,516,187 , IPR2014-01371 ( PTAB ) , Paper 12 , entered Mar. 13 ,
`2015 , 22 pages .
`Decision Denying Institution of Inter Partes Review , SanDisk
`Corporation v . Netlist , Inc. , U.S. Pat . No. 8,301,833 , IPR2014
`00994 ( PTAB ) , Paper 8 , dated Dec. 16 , 2014 , 16 pages .
`Decision Denying Institution of Inter Partes Review , SanDisk
`Corporation v . Netlist , U.S. Pat . No. 8,516,187 , IPR2014-00982
`( PTAB ) , Paper 9 , dated Dec. 22 , 2014 , 16 pages .
`Decision Denying Institution of Inter Partes Review , Smart Modular
`Tech v Netlist Inc. , U.S. Pat . No. 8,301,833 , IPR2014-01370 ( PTAB ) ,
`Paper 13 , entered Mar. 13 , 2015 , 19 pages .
`Decision Instituting Inter Partes Review , U.S. Pat . No. 8,671,243 ,
`Case No. IPR2017-00587-7 ( PTAB ) , Paper No. 7 , entered Jun . 22 ,
`2017 , 40 pages .
`Declaration of R. Jacob Baker , U.S. Pat . No. 8,874,831 , Case
`IPR2017-00692-2016 ( PTAB ) , filed Nov. 10 , 2017 , 72 pages .
`Declaration of R. Jacob Baker , U.S. Pat . No. 8,671,243 , Case
`IPR2017-00587-2016 ( PTAB ) , filed Oct. 13 , 2019 , 109 pages .
`Declaration of Jeff McMullen , Netlist , Inc. v . Diablo Technologies ,
`Inc. , Case No. 4 : I 3 - CV - 05889 - YGR ( NDCA ) , Document 362-1 ,
`filed Sep. 5 , 2018 , 3 pages .
`Declaration of Paul Min , In Inter Partes Review of U.S. Pat . No.
`8,301,833 , IPR2014-00994-1020 ( PTAB ) , filed Sep. 29 , 2008 , 215
`pages .
`
`Petitioners
`Ex. 1001, p. 4
`
`

`

`US 11,016,918 B2
`Page 5
`
`( 56 )
`
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`behalf of SanDisk , Corp. ) , filed Jun . 19 , 2014 .
`* cited by examiner
`
`Petitioners
`Ex. 1001, p. 5
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 1 of 22
`
`US 11,016,918 B2
`
`data
`
`CPU
`
`DRAM DIMM
`
`SSD / HD
`
`Data flow path
`
`FIG . 1
`( PRIOR ART )
`
`Non - Volatile DIMM
`data DRAM Memory data
`304
`
`MCH
`
`Control
`
`300
`
`Flash Memory
`302
`
`308
`Controller ]
`
`306
`
`FIG . 3A
`
`Petitioners
`Ex. 1001, p. 6
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 2 of 22
`
`US 11,016,918 B2
`
`DRAM
`DIMMS
`
`Spansion EcoRAM Configurations
`Single Accelerator
`256GB Spansion ECORAM Solution
`Server Motherboard
`Socket F
`Socket F
`Sponsin ?
`Spansion
`M
`ECORAW
`HT / Accelerator OOR2
`ECORAM
`Up to 256 GB
`DIMMS
`256GB Single Accelerator Spansion ECORAM Solution
`
`DOR2
`
`Duol Accelerator
`
`256GB Spansion ECORAM Solution
`Server Motherboard
`Socket
`
`DRAM
`DIMMS
`
`ODR2
`
`PIA
`
`A
`
`Socket F
`Sponsion ?
`ECORAM
`HT / Accelerator / ODR2
`
`Up to 256 GB
`
`Te
`
`Spansion
`ECORAM
`ECORAW
`DIMMS
`HT Accelerator DDR2
`D002
`Socket
`Socket
`Up to 256 GB
`256GB Single Accelerator Spansion ECORAM Solution
`FIG . 2
`( PRIOR ART )
`
`Control 408
`
`MCH
`
`dato DRAM Memory data
`402 '
`410
`
`Flash Memory
`404 '
`
`FDHDIMM
`
`400 '
`
`FIG . 4B
`
`Petitioners
`Ex. 1001, p. 7
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 3 of 22
`
`US 11,016,918 B2
`
`300 '
`
`306 ' 2
`
`NVDIMM
`
`NVDIMM
`
`DRAM
`304 "
`
`Flash
`302
`
`MCH
`FIG . 3B
`
`FDHDIMM
`ctri
`
`DRAM
`406
`
`400
`
`FDHDIMM
`
`Flash
`402
`
`MCH
`
`FIG . 4A
`
`Petitioners
`Ex. 1001, p. 8
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 4 of 22
`
`US 11,016,918 B2
`
`Dato
`
`550
`??
`
`FDHDIMM 556
`
`555
`
`DRAM
`
`508
`
`DMOR
`
`504
`
`Flash
`
`506
`
`FIG . 5A
`
`MCH / CPU
`
`C / A
`560
`
`DRAMA
`5081
`
`DRAM - B
`508 ( 2 )
`
`608
`
`611
`
`612
`
`621
`
`622
`
`Flash
`
`606
`
`Data Format
`Buffer
`604
`602
`
`CDC
`502
`
`Register
`
`610
`
`504 DMgr
`
`690
`
`FIG . 6
`
`Petitioners
`Ex. 1001, p. 9
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 5 of 22
`
`US 11,016,918 B2
`
`Example embodiment
`
`DRAM - B
`50812 )
`
`Flash
`506
`
`DRAM - A
`508-11
`
`DMgr . 1 ?
`
`500
`
`CDC
`502
`
`MCH
`
`FIG . 5B
`
`Petitioners
`Ex. 1001, p. 10
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 6 of 22
`
`US 11,016,918 B2
`
`Flash
`
`Flash Ciri
`
`DRAM *
`
`DMgr
`
`702
`
`DMgrCtrl
`710
`
`502
`
`Scheduler
`708
`
`FIG . 7
`
`502
`
`508
`
`506
`
`controls
`data interface
`MCH - controls DRAM
`Commend and address
`
`MCH - controls Flash
`Commend and address
`
`FIG . 8A
`
`Petitioners
`Ex. 1001, p. 11
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 7 of 22
`
`US 11,016,918 B2
`
`502
`
`CDC
`
`DMgr
`
`504
`
`FDHDIMM
`
`Flash
`506
`
`DRAM
`508
`
`MCH commond
`control
`
`MCH - Dota
`interface
`
`DRAM address
`space
`
`CDC - address
`mapping DRAM
`to Flash
`FIG . 8B
`
`Flash Address
`Space
`
`Petitioners
`Ex. 1001, p. 12
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 8 of 22
`
`US 11,016,918 B2
`
`Stort ( power up )
`
`Initialization
`
`922
`
`*
`
`*
`
`7 .
`
`mramor
`
`Lood DRAM WRC
`Copy data from Flash to DRAM
`& Erose the Flash Block ?
`
`MCH Opens Block ( pages )
`and DRAM Access
`912
`
`Any Block
`
`902
`
`906
`908
`
`910
`
`918
`
`??
`
`$
`
`I
`
`Copy / write doto
`back to Flash
`
`a 2 -914
`
`Any page
`rempage
`
`CDC control
`
`Finish doto write
`
`920
`
`FIG . 9
`
`Petitioners
`Ex. 1001, p. 13
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 9 of 22
`
`US 11,016,918 B2
`
`1004
`
`1002
`/
`RC ( X )
`RC ( X + 1 )
`24 bit extended memory page address
`Mapping MCH DDR DIMM page
`address to Flash memory
`
`1041
`A9
`A23
`AX + 1 AXAI A8
`LUN Address Block Address
`Page Address
`
`1031
`
`1021
`
`1061
`
`1051
`
`Plane
`address
`
`Flash
`Transfer
`size
`
`FIG . 10
`
`Petitioners
`Ex. 1001, p. 14
`
`

`

`U.S. Patent
`
`May 25 , 2021
`
`Sheet 10 of 22
`
`US 11,016,918 B2
`
`#or
`Flash
`DRAM blocks Wwtime to
`density per
`rom time
`( GB ) bank
`ratio
`250
`1
`250
`250
`250
`
`1
`
`1
`
`2
`2
`2
`2
`4
`
`500
`500
`1000
`
`55
`
`55
`55
`55
`55
`55