(12) United States Patent
`Kopera
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8.264,205 B2
`Sep. 11, 2012
`
`US008264205B2
`
`(54) CIRCUIT FOR CHARGE AND/OR
`DISCHARGE PROTECTION IN AN
`ENERGYSTORAGE DEVICE
`(75) Inventor: John Joseph Christopher Kopera, Vail,
`AZ (US)
`
`(73) Assignee: Sion Power Corporation, Tucson, AZ
`US
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 548 days.
`(21) Appl. No.: 12/069,335
`TNO.
`pp
`9
`(22) Filed:
`Feb. 8, 2008
`
`(65)
`
`Prior Publication Data
`US 2009/O2O0986 A1
`Aug. 13, 2009
`
`(2006.01)
`
`(51) Int. Cl.
`H02. 7/00
`32O/136
`(52) U.S. Cl
`(58) Field of Classification Search ................... 32Of 136
`See application file for complete search history.
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`5,278,000 A
`1/1994 Huang et al.
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`7, 1998 Mao et al.
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`2/2003 Iwaizono et al.
`6,524,739 B1
`826. R 838. RA tal
`6,784,642 B2
`8/2004 Yugo et al.
`6,940,256 B2
`9, 2005 Sakurai
`7,085,338 B2
`8, 2006
`al
`... 320,134
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`... 320,134
`2005, OO77878 A1* 4, 2005 Carrier et al. ......
`2005/O127879 A1* 6/2005 Sato et al. ..................... 320,134
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`7/2005 Sato et al.
`2005/0208345 A1
`9, 2005 Yoon et al.
`2007/O1264.03 A1
`6, 2007 Chen
`2007/O128505 A9
`6, 2007 Yahnker et al.
`2007/0152637 A1
`7/2007 Cherng et al.
`2008/0018304 A1* 1/2008 Litingtun et al. ............. 320,134
`FOREIGN PATENT DOCUMENTS
`133.9154
`8, 2003
`(Continued)
`
`EP
`
`OTHER PUBLICATIONS
`International Search Report and Written Opinion from PCT/US2009/
`000783, mailed Aug. 21, 2009.
`
`- - -
`-
`Primary Examiner — Arun Williams
`(74) Attorney, Agent, or Firm — Wolf, Greenfield & Sacks,
`P.C.
`ABSTRACT
`(57)
`A method and apparatus for protecting an energy-storage
`device (ESD), such as a rechargeable battery, is provided. A
`protective circuit protects an ESD from adverse charging and
`loading conditions including overcharging, overdischarging,
`charging at an excessive rate and discharging at an excessive
`rate. The protective circuit selectively disables charging and
`discharging based on the present terminal conditions. A plu
`rality ofESDs and protective circuits can be interconnected to
`protect a multi-cell ESD device. Embodiments of the protec
`tive circuit are adapted to protect a lithium cell operating
`around 2 volts. The protective circuit may also protect the
`ESD from adverse temperature conditions.
`23 Claims, 8 Drawing Sheets
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`3.
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`r14
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`24
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`1
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`EP
`GB
`JP
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`FOREIGN PATENT DOCUMENTS
`1507 306 A1
`2/2005
`2433 359 A
`6, 2007
`O7023532 A
`1, 1995
`
`2000-152516
`JP
`399,
`E
`* cited by examiner
`
`5, 2000
`1938
`
`2
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`NOCO Ex. 1011
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`U.S. Patent
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`Sep. 11, 2012
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`U.S. Patent
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`Sep. 11, 2012
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`Sheet 2 of 8
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`US 8,264.205 B2
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`Protective
`Circuit
`24-1
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`Protective
`Circuit
`24-i
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`20-1
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`20-i
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`20-N
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`22-N
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`Protective
`Circuit
`24-N
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`Fig. 2A T6
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`Fig. 5
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`3
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`Region 54
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`Voc=2.65
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`Operating
`Range
`(52)
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`Overdischarge
`Region 56
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`US 8,264,205 B2
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`1.
`CIRCUIT FOR CHARGE AND/OR
`DISCHARGE PROTECTION IN AN
`ENERGYSTORAGE DEVICE
`
`BACKGROUND
`
`15
`
`The present invention relates to a circuit and method for
`protecting an energy-storage device.
`Energy-storage devices (ESDs) are used in numerous
`applications, particularly in portable electronic devices. A
`10
`variety of types of ESDS have been developed to meet the
`energy density and power density requirements of various
`applications. These types include conventional batteries, fuel
`cells, conventional capacitors, and ultracapacitors.
`In many applications, it is desirable to be able to recharge
`an ESD. Recharging the ESD places the device back in a state
`from which it can continue to power electronic devices, even
`after its stored energy has been used. Examples of recharge
`able energy-storage devices include lead acid, nickel cad
`mium (NiCd), lithium polymer (Li-poly), lithium iron phos
`phate, lithium ion (Li-ion), and nickel-metal hydride (NiMH)
`batteries.
`ESDS may be damaged if operated under extreme condi
`tions. Either improper charging or discharging conditions
`may lead to damage of an ESD. Operation at excessive tem
`25
`peratures may also cause damage. For example, overcharging
`may cause electrolytic decomposition of a lithium-based
`rechargeable battery. Over discharging caused by a short cir
`cuit across the ESD may cause a large current to be drawn
`from the ESD, causing damage to the ESD. For some ESDs,
`even excessive discharging under normal loading conditions,
`resulting in a slow drop of the energy stored in the ESD, may
`deplete the ESD below a level at which it can be fully
`recharged. Operation of an ESD at an excessive temperature
`may also damage the ESD or be a signal of excessive load,
`which, in turn, may damage the ESD.
`To protect an ESD during adverse operating conditions,
`protective circuits have been used to prevent adverse charg
`ing, discharging or temperature conditions from impacting
`the ESD.
`
`30
`
`35
`
`40
`
`SUMMARY
`
`50
`
`An improved apparatus and method are provided for pro
`tecting an energy-storage device (ESD) during adverse con
`45
`ditions.
`In some aspects, the invention relates to a protective circuit
`having a charge protection circuit and discharge protection
`circuit. The charge protection circuit disables current flow
`into the energy-storage device while simultaneously allowing
`current to flow out of the energy-storage device while a volt
`age corresponding to an overcharge state of the energy-stor
`age device is detected. The discharge protection circuit allows
`current to flow into the energy-storage device but disables
`current flow out of the energy-storage device when a Voltage
`corresponding to an overdischarge state of the energy-storage
`device is detected. Current flow out of the energy-storage
`device is disabled until a Voltage corresponding to an operat
`ing range of the energy-storage device is detected, at which
`point current is again allowed to flow both into or out of the
`energy-storage device.
`In some embodiments, the protective circuit includes a
`p-channel FET. The p-channel FET may be adapted to disable
`current flow out of the energy-storage device. In addition to a
`p-channel FET, the protective circuit may also include an
`n-channel FET adapted to disable current flow into the
`energy-storage device.
`
`55
`
`60
`
`65
`
`2
`In some embodiments, the energy-storage device is a
`rechargeable battery cell such as a lithium cell. The protective
`circuit may be adapted to protect a cell or battery having an
`operating range from 1.50 to 2.5 volts. The overcharge state is
`entered when the voltage exceeds 1.65 V and the overdis
`charge sate is entered when the voltage falls below 1.40 V.
`In another aspect, the invention relates to a plurality of
`energy-storage devices and a plurality of protective circuits.
`Each of the plurality of energy-storage devices has a corre
`sponding protective circuit. A first terminal of the energy
`storage device is coupled to a first terminal of the protective
`circuit. Similarly, a second terminal of the energy-storage
`device is coupled to a second terminal of the protective cir
`cuit. The protective circuit further comprises a third terminal
`and fourth terminal. A first directional element is coupled
`between the first and third terminals of the protective circuit
`and is configured to allow current to flow in a first direction
`between the first terminal and the third terminal. A first switch
`is coupled between the first and third terminals in parallel
`with the first directional element. The first switch has a con
`trol input and is adapted and configured to selectively block
`current flow in response to a value in a first state at the control
`input of the first switch. An overdischarge detector is coupled
`between the third and fourth terminals of the protective cir
`cuit. The overdischarge detector has an output coupled to the
`control input of the first switch. The output of the overdis
`charge detector has a value in the first state when the Voltage
`at the input of the overdischarge detector drops below a value
`corresponding to an overdischarge State and a value other than
`in the first state when the voltage rises to a level correspond
`ing to an operating range. A second directional element is
`coupled between the second and fourth terminals of the pro
`tective circuit and is configured to allow current to flow in a
`second direction between the second terminal and the fourth
`terminal. A second Switch is coupled between the second and
`fourth terminals in parallel with the second direction element.
`The second switch has a control input and selectively blocks
`current flow in response to a value in a second state at the
`control input of the second Switch. An overcharge detector is
`coupled between the second and fourth terminals of the pro
`tective circuit. The overcharge detector has an output coupled
`to the control input of the second switch. The output of the
`overcharge detector has a value in the second state when the
`Voltage at the input of the overcharge detector increases above
`a value corresponding to an overcharge state.
`Some embodiments further comprise an over-temperature
`detector coupled to the control input of the first switch and the
`control input of the second switch. The over-temperature
`detector provides a value in the first state to the control input
`of the first switch and a value in the second state to the control
`input of the second Switch when the temperature is outside an
`acceptable range.
`In some embodiments, the protective circuit includes a
`p-channel FET. In addition to a p-channel FET, the protective
`circuit may also include an n-channel FET adapted to disable
`current flow into the energy-storage device.
`In some embodiments the protective circuits are connected
`in parallel. In some embodiments the protective circuits are
`connected in series.
`In some embodiments the plurality of the energy-storage
`devices comprise lithium cells.
`Some embodiments further comprise a package. At least
`one of the plurality of energy-storage devices and one of the
`plurality of protective circuits is disposed within the package.
`In a further aspect, this invention relates to a method of
`operating a protective circuit for an energy-storage device.
`The Voltage applied across terminals coupled to an energy
`
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`3
`storage device is sensed. Current flow into the energy-storage
`device is disabled and current flow out of the energy-storage
`device is allowed when a Voltage corresponding to an over
`charge state of the energy-storage device is sensed. Current
`flow out of the energy-storage device is disabled and current 5
`flow into the energy-storage device is allowed when a Voltage
`corresponding to an overdischarge state is sensed.
`In some embodiments, the method further comprises
`monitoring the temperature and disconnecting the energy
`storage device when the monitored temperature is outside an 10
`allowed temperature range.
`In some embodiments, disabling current flow out of the
`energy-storage device comprises placing a p-channel FET in
`a non-conductive state. In some embodiments, disabling cur
`rent flow into the energy-storage device comprises placing a 15
`n-channel FET in a non-conductive state.
`In Some embodiments, the energy-storage device is a
`lithium battery. The lithium battery may have an operating
`range from 1.5V to 2.5V. The overcharge state may comprise
`voltages over 1.65 V, and the overdischarge state may com- 20
`prise voltages under 1.40 V.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`4
`charging and/or discharging based on the detection of adverse
`or propitious ESD terminal conditions. Additionally, the pro
`tective circuit may include circuitry for enabling or disabling
`ESD charging and/or discharging based on the temperature of
`the ESD.
`The protective circuit may include an overcharge detector
`for detecting a Voltage corresponding to an overcharge state.
`A Voltage corresponding to an overcharge State may occur, for
`example, if the ESD is charging at an excessive rate or exces
`sively charged. The overcharge detector may control a circuit
`having a charging enabled mode and a charging disabled
`mode. While in the charging enabled mode, a charging cur
`rent is permitted to reach the ESD. By changing to the charg
`ing disabled mode in response to a detected over-charge con
`dition, damage caused by over-charging may be prevented.
`While in the charging disabled mode, the ESD may not
`receive a Substantial charging current.
`The protective circuit may include an overdischarge detec
`tor for detecting a Voltage corresponding to an overdischarge
`state. A Voltage corresponding to an overdischarge state may
`occur, for example, if the ESD is discharging at an excessive
`rate or is excessively discharged. The overdischarge detector
`may control a circuit having a discharging enabled mode and
`a discharging disabled mode. While in the discharging
`enabled mode, a discharging current is permitted to be drawn
`from the ESD. While in the discharging disabled mode, the
`ESD may not provide a substantial current. By changing the
`mode in response to a detected over-discharge condition,
`discharging may be disabled to prevent damage to the ESD.
`Additionally the protective circuit may include a tempera
`ture detector for determining if the ESD is at a safe operating
`temperature. The temperature detector is able to control the
`circuits adapted to enable and disable charging and discharg
`ing. By changing the modes of these circuits in response to a
`detected over-temperature condition, both charging and dis
`charging may be disabled to prevent operation of the ESD
`under temperature conditions that could damage the ESD.
`An example of an electronic system that may incorporate
`such a protective circuit is shown in FIG. 1. FIG. 1 shows an
`embodiment in which a protected ESD 10, a charger 12, and
`a load 14 are electrically connected in parallel. Protected ESD
`10 has terminals T5 and T6. The charger 12 is capable of
`providing a charging current to the protected ESD 10 and, for
`example, may be a power Supply connected to an AC outlet.
`The load 14 can represent any form of impedance. The load
`14, for example, may be an electronic device.
`Under normal operating conditions, the ESD will supply
`current to load 14 to power the load. The amount of current
`drawn by load 14 will be in a range that allows the ESD to
`maintain a Voltage in the normal operating range for that ESD.
`Likewise, under normal operating conditions, charger 12 will
`Supply a currentata Voltage level within the normal operating
`range of ESD 10. However, events can occur that create
`adverse operating conditions. For example, the load 14 may
`increase the amount of current it draws from ESD 10 and
`cause the Voltage measured by the overdischarge detector to
`correspond to an overdischarged State.
`Also the charger 12, for example, may output spikes and
`irregularities in the charging Voltage that may cause the Volt
`age measured by the overcharge detector to correspond to an
`overcharged State.
`In some embodiments, an ESD, such as a battery may be
`made of multiple cells. The entire battery may be protected
`with a protective circuit. However, in some embodiments,
`each cell may have a separate protective circuit. Each protec
`tive circuit and cell may be packaged together with the cells,
`with associated protected circuits, may then be assembled
`
`30
`
`35
`
`The invention and embodiments thereof will be better 25
`understood when the following detailed description is read in
`conjunction with the accompanying drawing figures. In the
`figures, elements are not necessarily drawn to scale. In gen
`eral, like elements appearing in multiple figures are identified
`by a like reference designation. In the drawings:
`FIG. 1 is a circuit diagram showing an operating environ
`ment for an ESD with a protective circuit according to
`embodiments of the invention;
`FIG. 2A is a circuit diagram showing N series connected
`ESDs, each with an associated protective circuit;
`FIG. 2B is a circuit diagram showing N parallel connected
`ESDs, each with an associated protective circuits;
`FIG. 3 is a simplified block diagram of an illustrative
`embodiment of the protective circuit according to some
`40
`embodiments of the invention;
`FIG. 4 is a circuit diagram of an illustrative embodiment of
`the invention;
`FIG. 5 is a plot of the operating Voltage range, over-dis
`charge threshold, and over-charge threshold for an illustrative
`embodiment of the protective circuit;
`FIG. 6 is a flow chart of a process of operating a protective
`circuit providing over-charge and over-discharge protection
`according to some embodiments of the invention; and
`FIG. 7 is a flow chart of a process of operating a protective
`circuit with temperature protection according to some 50
`embodiments of the invention.
`
`45
`
`DETAILED DESCRIPTION
`
`The inventors have appreciated that an improved protective 55
`circuit for energy-storage devices (ESDs) is desirable. A
`method and apparatus for protecting an ESD is provided that
`protects ESDs from adverse conditions and is easily adapt
`able to many different types of ESDs. These adverse condi
`tions may include over-charging, over-discharging and/or 60
`over-temperature. An embodiment of the invention is a pro
`tective circuit applicable even to ESDs operating at very low
`Voltages. For example, an embodiment provides a protective
`circuit that is adapted for a lithium battery having an operat
`ing range from about 1.5 to 2.5 V.
`According to embodiments of the invention, a protective
`circuit maybe provided to selectively disable and enable
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`into a multi-cell ESD. FIG. 2A is a block diagram of an
`embodiment of a multi-cell protected ESD 10 comprising N
`series connected protected ESD cell packages 20-1 to 20-N.
`Taking cell package 20-i as illustrative, each protected ESD
`cell package 20-i comprises an ESD cell 22-i and a protective
`circuit 24-i. The protective circuit 24-i may be implemented
`on a printed circuit board or other suitable substrate. The
`circuit board may then be attached to the ESD cell 22-i and
`both the protective circuit 24-i and ESD cell 22-i may be
`enclosed in a package. Any Suitable type of packaging may be
`used, including shrink wrap or other material to enclose the
`components of the ESD cell package.
`FIG. 2B is a block diagram of an embodiment of a multi
`cell protected ESD 10 comprising N parallel connected pro
`tected ESD cell packages 20-1 to 20-N. The ESD cell pack
`ages 20-1 to 20-N may be implemented as in the embodiment
`of FIG. 2A but interconnected to form a protected ESD with
`different voltage and current characteristics than the ESD of
`FIG. 2A. Though FIGS. 2A and 2B show ESD cells con
`nected only in series and only in parallel, embodiments are
`also possible wherein protected ESD 10 comprises both par
`allel and series connected protected ESD cells.
`In the embodiments illustrated in FIGS. 2A and 2B, ESD
`cell 22-i may be a battery although any type of ESD may be
`25
`used.
`FIG.3 is a block diagram of a representative protected ESD
`cell 20. Protected ESD cell 20 may be representative of any of
`the protective ESD cell packages 20-1 to 20-N in FIGS.
`2A-2B. Protected ESD cell 20 comprises ESD 22 and protec
`tive circuit 24. In this example, the protective circuit 24 is a
`four terminal device. Terminals T1 and T2 are connected to
`the positive and negative terminals of ESD 22 respectively.
`Terminals T3 and T4 are the positive and negative connec
`tions respectively to the protected ESD cell 20. If protected
`ESD 10 comprised only one protected ESD cell 20, terminals
`T3 and T4 correspond to terminals T5 and T6 (FIG. 1),
`respectively, which may be connected to a load and a charger
`in an electric device.
`The protective circuit 24 protects ESD 22 during adverse
`Voltage conditions. Adverse Voltage conditions may indicate
`ESD 22 is discharging at an excessive rate, charging at an
`excessive rate, discharged below a safe minimum energy
`level, or charged beyond a safe maximum energy level. The
`protective circuit 24 may also provide protection for the ESD
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`22 during adverse temperature conditions.
`Under normal operating conditions, both current control
`lers 32 and 33 may allow current to flow freely back and forth
`of the terminals T1 and T2 of ESD 22. In this state, ESD 22
`may either Supply a current to drive a load or receive a current
`50
`to recharge itself. Under adverse conditions, either or both of
`current controllers 32 and 33 may restrict current flow to or
`from ESD 22, selectively disabling charging and/or discharg
`ing of ESD 22. In the embodiment illustrated, in an over
`charge state, current controller 32 prevents current from flow
`ing from terminal T2 to terminal T4, thereby stopping
`charging current flow in ESD 22. During an overdischarge
`state, current controller 33 prevents ESD 22 from providing a
`current to a load by interrupting the discharge path through
`terminal T1 to terminal T3. During an over-temperature con
`dition, current controllers 32 and 33 may restrict both a charg
`ing and a discharging current from reaching/leaving ESD 22.
`To provide overcharge protection for ESD 22, the protec
`tive circuit 24 includes a overcharge detection circuit 34a,
`latch 34b and current controller 32. Current controller 32
`permits current flow in two directions or in only one direction,
`depending on a control input. In some embodiments, current
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`controller 32 comprises a switch 32a and a directional ele
`ment 32b connected in parallel.
`A control input for current controller 32 may be derived
`from an output of overcharge detector circuit 34a. The over
`charge detection circuit 34a compares the Voltage between
`terminals T1 and T4 to a threshold defining an overcharge
`state. If the Voltage corresponds to an overcharged state over
`discharge detection circuit 34a asserts an output that sets latch
`34b. Latch 34b is in turn connected to switch 32a within
`current controller 32. In this state, latch 34b disables switch
`32a. When switch 32a is disabled, current flow is restricted
`through the switch. In the embodiment illustrated, when
`switch 32a is disabled, current flow through switch 32a is
`effectively blocked. However, in other embodiments, dis
`abling switch 32a may reduce the current flow 32a to an
`appropriate level that reduces the risk of damage to ESD 22
`through overcharging.
`As shown, Switch 32a is in parallel with directional ele
`ment 32b. Directional element 32b permits current to flow
`from T4 to T2, but restricts current flow from T2 to T4. Here
`and throughout, currents assigned a direction are taken to flow
`from high potential to low potential. Thus, during an over
`charge condition, current may flow from T4 to T2 allowing
`the ESD 22 to discharge, but not from T2 to T4, preventing
`further charging.
`When the overcharge condition is removed, the output of
`overcharge detection circuit 34a will return to a state that does
`not set latch 34b. However, latch 34b will already be set and
`will remain set until a signal indicating Voltage in a normal
`operating range for ESD 22 is present. A circuit to generate
`the normal operating range signal is not expressly shown in
`FIG.3 for simplicity, but any suitable circuit to generate that
`signal may be used.
`As shown, Switch 32a is enabled when latch 34b is reset.
`Once enabled, switch 32a allows a charge current to flow into
`ESD cell 22. As a result, latch 34b allows protective circuit 24
`to disable charging of ESD 22 in response to an overcharge
`condition and not re-enable charging until operating condi
`tions return to a normal operating range. The Voltage charac
`teristic of an overcharge condition may be higher than the
`upper limit of the normal operating range for ESD 22.
`The protective circuit 24 further includes an overdischarge
`detection circuit 35a, latch 35b and current controller 33 to
`protect ESD 22 during an overdischarge condition. Current
`controller 33 permits current flow in two directions or in only
`one direction depending on a control input. In some embodi
`ments, current controller 33 comprises a switch 33a and a
`directional element 33b. The overdischarge detection circuit
`35a compares the voltage between terminals T3 and T4 to a
`threshold defining an overdischarge state. If the Voltage cor
`responds to an overdischarged State, over discharge detection
`circuit 35a outputs a value that sets latch 35b. When latch 35b
`is set, latch 35b disables switch 33a. When switch 33a is
`disabled, current flow through the switch is restricted. Switch
`33a is in parallel with directional element 33b. Directional
`element 33b permits current to flow from T3 to T1, but
`restricts current flow from T1 to T3. Thus, during an overdis
`charge condition, current may flow from T3 to T1 allowing
`the ESD 22 to charge, but not from T1 to T3, preventing
`further discharging.
`Switch33a is enabled when latch35b is reset. As with latch
`34b, latch 35b may be reset when the voltage on ESD 22
`returns to a normal operating range.
`The protective circuit 24 may further comprise a tempera
`ture detector circuit 31. The temperature detector circuit 31
`monitors the temperature and can disable switches 32a and/or
`33a when the temperature is outside an acceptable range.
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`NOCO Ex. 1011
`Page 13
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`US 8,264,205 B2
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`When the temperature returns to an acceptable range, the
`temperature detector circuit can re-enable switches 32a and/
`or 33a.
`The protected ESD cell 20 shown in FIG. 3 can be imple
`mented in numerous ways. FIG. 4 is a circuit diagram illus
`trating an embodiment of the protective circuit 24 connected
`to an ESD 22. In this embodiment, the ESD 22 may be a
`battery having one or more cells or any type of ESD. In FIG.
`4, resistors are labeled R1 to R15, capacitors are labeled C1 to
`C4, Schottky diodes are labeled D1 and D3, and transistors
`with diodes are labeled Q1 to Q4. Additionally, RT1 is a
`thermistor, U1 is a dual comparator integrated circuit, and U2
`is an op-amp. U1 contains a reference Voltage, V, a first
`comparator, U1-A, and a second comparator, U1-B.
`In this embodiment Q1 to Q4 are metal-oxide-semiconduc
`tor field-effect transistors. Q1 is a p-channel MOSFET
`(PMOS), and Q2, Q3, and Q4 are n-channel MOSFETs
`(NMOS). When a MOSFET is “ON”, a current may pass with
`only a small Voltage drop between the Source and drainter
`minals. When a MOSFET is “OFF' the impedance between
`the source and drain terminals is very large and current flow
`between the source and drain is restricted. Each NMOS has a
`diode connected from its source terminal to its drainterminal.
`Each PMOS has a diode connected from its drain terminal to
`its source terminal. Each of the foregoing components is
`known in the art and the circuit illustrated in FIG. 4 may be
`constructed using Such known components according to
`known circuit design and manufacturing techniques. Specific
`value of the components may be selected to enable and dis
`able charging and discharging at Voltage levels that are appro
`priate for ESD 22. Similarly, value may be selected to enable
`and disable charging and/or discharging in response to tem
`perature levels appropriate for ESD 22. In the embodiment
`illustrated, transistor Q3 and its associated diode perform the
`functions of current controller32. Transistor Q1 and its asso
`ciated diode perform the functions of current controller 33.
`The functions of overdischarge detection 34a and its associ
`ated latch 34d are performed by comparator U1-D. The func
`tions of overdischarge detection circuit 35a and its associated
`latch 35b are performed by comparator U1-A. The functions
`oftemperature detector are performed by thermistor RT1 and
`associated components, including amplifier U2 and resistors
`R5, R6 and R11. Other components within the circuit of FIG.
`4 perform ancillary functions. Such as coupling signals
`between these components and ensuring that they receive
`Voltages at an appropriate level.
`During normal operation when the voltage of the ESD 22 is
`within the operating range and the temperature is in the
`acceptable range, transistor Q1, Q2, and Q3 are ON, and
`transistor Q4 is OFF.
`When the voltage between terminals T1 and T4 corre
`sponds to an overcharge state, the protective circuit 24 enters
`an overcharge protection state. This state may indicate that
`the ESD 22 is charging at an excessive rate or has been
`charged to an excessive level and is at risk of being damaged.
`The overcharge detection circuit 34a (FIG.3) may include the
`voltage divider provided by resistors R4 and R9, which scales
`the voltage between terminalsT1 and T4. This voltage is input
`to the negative terminal of comparator U1-B. During over
`charge, the Voltage exceeds V, forcing the output of com
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`parator U1-B low. This level in turn forces the gate electrode
`of NMOS transistor Q3 low, turning transistor Q3 OFF. The
`combination of the Q3 being OFF and the diode in parallel
`with transistor Q3, restricts a charging current from flowing
`into ESD 22 while still allowing ESD 22 to discharge.
`In order for Q3 to be re-enabled, the Voltage at the negative
`terminal of comparator U1-B must drop sufficiently to send
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`the comparator output back to high. Notice that comparator
`U1-B is illustrated with a hysteresis loop. Because of the
`presence of hysteresis in comparator U1-B, the output
`switches from low to high at a different voltage than it
`Switches from high to low. This operation provides latching
`that provides functionality of latch 34b (FIG. 3). It should be
`noted and appreciated that resistors R4 and R9, as well as
`V and the hysteresis properties of comparator U1-B define
`the overcharge state. For a given comparator and reference
`Voltage, the overcharge state can be determined by the selec
`tion of the resistance values of R4 and R9.
`When the voltage between terminals T3 and T4 corre
`sponds to an overdischarge state, the protective circuit enters
`an overdischarge protection state