Paper No. ___
`Filed: February 10, 2023
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________
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`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
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`v.
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`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`_____________________________
`
`Case No. IPR2023-00130
`Patent No. 7,116,710
`_____________________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107
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`TABLE OF CONTENTS
`Introduction ....................................................................................................... 1
`I.
`II. Claim Construction ........................................................................................... 3
`III. The Petition is Founded on a Distortion of Kobayashi .................................... 5
`IV. Ground 1 Fails ................................................................................................... 9
`A. Kobayashi Does Not Disclose Irregular Repetition (All Claims) ............ 10
`1. Petitioner misinterprets the claims’ construction ...............................11
`2. Kobayashi does not expressly disclose irregular repetition ...............13
`3. Petitioner fails to show Kobayashi’s first encoder inherently performs
`irregular repetition ..............................................................................15
`4. Petitioner’s arguments are fatally inconsistent ...................................19
`B. Kobayashi Does Not Disclose a First Encoded Data Block Formed
`of Irregularly Repeated Bits (Claim 11) ................................................... 27
`C. Kobayashi Does Not Disclose Scrambling Irregularly Repeated
`Bits (Claims 15 & 25) ............................................................................... 29
`V. Ground 2 Fails ................................................................................................. 33
`VI. Ground 3 Fails ................................................................................................. 33
`VII. Institution Should be Denied under 35 U.S.C. §314(a) .................................. 36
`A. Fintiv Applies to This Proceeding ............................................................ 37
`B. The Fintiv Factors Weigh in Favor of Denying Institution ...................... 39
`1. Factor 1 favors denial .........................................................................39
`2. Factor 2 favors denial .........................................................................40
`3. Factor 3 favors denial .........................................................................42
`4. Factor 4 does not favor institution ......................................................45
`5. Factor 5 favors denial .........................................................................46
`6. Factor 6 favors denial .........................................................................47
`VIII. Conclusion ...................................................................................................... 50
`IX. Appendix ......................................................................................................... 52
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`-i-
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`I.
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`INTRODUCTION
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`This is the sixth IPR petition challenging the claims of U.S. Patent No.
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`7,116,710 (“the ’710 patent”). Despite five prior petitions1 and two instituted trials,
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`the Board has never found a single claim of the ’710 patent unpatentable.2 The
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`present petition does not warrant a different outcome.
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`Petitioner Samsung Electronics Co., Ltd. advances a challenge premised on
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`anticipation by Kobayashi, yet various aspects of the challenged claims are simply
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`missing from Kobayashi. Rather than meeting its burden to show that Kobayashi
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`discloses each limitation, Petitioner seeks to avoid the claims’ requirements by
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`misreading limitations or simply assuming that Kobayashi meets the claims despite
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`its silence on the issue. For example, each independent claim includes a limitation
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`directed to irregular repetition—expressed either as repeating received bits “a
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`different number of times,” as recited in claim 11, or simply as “repeat[ing] said
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`stream of bits irregularly,” as recited in claims 15 and 25. Kobayashi does not
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`disclose irregular repetition as recited, and Petitioner fails to show that it is
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`1 IPR2017-00210; IPR2017-00211; IPR2017-00219; IPR2015-00067; IPR2015-
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`00068.
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`2 The Federal Circuit summarily affirmed the final written decisions upholding
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`all claims. Apple Inc. v. Cal. Inst. of Tech., 796 F. App’x 743 (Fed. Cir. 2020).
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`-1-
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`inherent. In fact, Petitioner actually provides examples of encoding techniques that
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`undermine the logic on which Petitioner grounds its inherency argument.
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`The petition is similarly deficient with respect to other limitations.
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`Independent claim 11 recites that a first encoded data block is formed by repeating
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`bits of a received data block different numbers of times. Yet what Petitioner
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`identifies in Kobayashi for this element is not a block formed by irregularly
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`repeating bits, but a block consisting of one copy of each original bit plus parity
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`bits that are not repeated bits at all. As for independent claims 15 and 25, each
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`requires scrambling of irregularly repeated bits, yet Kobayashi never scrambles
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`irregularly repeated bits. Petitioner points instead to an interleaving of a single
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`copy of each original bit with a group of parity bits, not to a scrambling of a
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`collection of irregularly repeated bits.
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`In addition to these deficiencies, Petitioner’s late filing of this petition
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`warrants discretionary denial in light of the co-pending litigation in the Eastern
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`District of Texas in which Petitioner is a defendant. Petitioner filed the present
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`case less than a year before the scheduled trial. Under even generous estimates, the
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`district court trial will be completed many months before a final written decision
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`would be due in this case. Given the substantial costs that will arise due to
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`duplication of efforts, Petitioner’s unexplained and unexcused delay, and the weak
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`merits of the petition’s grounds, the Board should not institute trial.
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`-2-
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`Accordingly, institution of inter partes review of claims 11-17 and 19-33 of
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`U.S. Patent No. 7,116,710 (“the ’710 patent”) should be denied.
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`II. CLAIM CONSTRUCTION
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`In an inter partes review, a claim is given its ordinary and customary
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`meaning in light of the specification. 37 C.F.R. §42.100(b); Phillips v. AWH Corp.,
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`415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc). Petitioner asserts that the term
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`“repeat” should be construed to mean “generation of additional bits, where
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`generation can include, for example, duplication or reuse of bits,” in accordance
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`with a district court construction affirmed by the Federal Circuit. Pet., 8 (citing
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`Cal. Inst. of Tech. v. Broadcom Ltd., 25 F.4th 976, 986 (Fed. Cir. 2022)
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`(“Broadcom litigation”)).
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`However, Petitioner extends this construction in an unreasonable way and
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`mischaracterizes the Federal Circuit’s construction. Petitioner first asserts that (1)
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`the Federal Circuit held that “passing an input information bit through an AND
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`gate when the other input is a ‘1’ bit comprises ‘repeating’ the information bit”; (2)
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`“[m]ultiplying a binary information bit by a “1” bit is equivalent to passing the
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`information bit through an AND gate with a ‘1’ bit”, and (3) therefore,
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`“multiplying an information bit by a “1” bit comprises ‘repeating’ the information
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`bit.” Pet., 14-15. The Federal Circuit never said this—its claim construction never
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`discussed either multiplication or AND gates. See Broadcom, 25 F.4th at 986.
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`-3-
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`Certainly it never said anything about multiplying by “1” being equivalent to a
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`device that uses an AND gate, let alone whether that would constitute, by itself, a
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`repeat under the claims. To the extent Petitioner implies otherwise, that is a
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`mischaracterization of the Federal Circuit’s decision.
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`Even taking as true Petitioner’s assertion that the Federal Circuit considered
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`whether passing an input bit through an AND gate where the other bit is a “1”
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`comprises repeating the information bit, the Federal Circuit’s discussion related to
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`infringement, not claim construction. See id., 986-88. The Federal Circuit made it
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`clear that it was addressing a very specific system implemented in infringing
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`products, and that the relevant analysis considered the system’s “overall
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`architecture,” not just an individual component. Id., 988. That system involved a
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`device that physically connected input bits via wires to 972 separate AND gates
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`and simultaneously transmitted duplicates of the bits via a number of selected gates
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`ranging from 3 to 12 to be used in forming parity bits. See id., 986-88 (“[T]he
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`physical connection of the first inputs of all 972 AND gates for simultaneous
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`receipt of the information bit stream and the connection of the parity-bit system to
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`the other inputs of the AND gates to selectively enable 3 to 12 of those gates at any
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`time together implement irregular repetition.” (emphases original)). In other
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`words, the Federal Circuit merely agreed that a device could be found to
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`“irregularly repeat” if its overall configuration for encoding was arranged to make
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`-4-
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`multiple simultaneous duplicate copies of input bits (in irregular amounts) and to
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`transmit the copied bits via separate wires through a selected set of a varying
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`number of parallel AND gates. The Federal Circuit said nothing about multiplying
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`a bit by “1”.
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`Moreover, as discussed below in §IV.A, the petition’s invalidity case falls
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`apart because its fundamental premise—that Kobayashi’s outer encoder
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`necessarily multiplies bits by “1” in a pattern determined by its generator matrix—
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`is unfounded, fatally undermining Petitioner’s inherency case. Even if Petitioner’s
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`interpretation of the Federal Circuit’s construction were accepted, Petitioner’s case
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`fails, as it requires reading the claims’ recited irregular repetition into Kobayashi
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`despite the reference neither teaching nor requiring such repetition.
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`III. THE PETITION IS FOUNDED ON A DISTORTION OF KOBAYASHI
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`The ’710 patent is one of four Caltech patents that resulted from research
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`performed by the inventors, Hui Jin, Aamod Khandekar, and Robert J. McEliece,
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`in 1999-2000. The patents claim inventions directed to a revolutionary class of
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`error-correction codes, dubbed “irregular repeat and accumulate codes,” or “IRA
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`codes,” which rivaled and surpassed the performance of the best known codes at
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`that time. No other code known at the time could boast linear encoding, linear
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`decoding, and performance near the theoretical Shannon limit. See EX1001, 2:6-10
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`-5-
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`(linear time decoding), 6:24-60 (performance near theoretical Shannon limit);
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`EX2005, 7 (linear time encoding).
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`As the Board has previously found, the field of error correction coding is
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`complex and highly unpredictable. IPR2017-00219, Paper 76 at 18. The
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`development of IRA codes in spite of this unpredictability represented a significant
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`advancement in encoding technology. Accordingly, the specification and claims
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`focus strongly on precise details of encoding processes that allow the realization of
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`IRA codes’ improved performance.
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`By contrast, Kobayashi focuses almost exclusively on decoding. Its title
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`describes error-correction decoding of a received data stream. Its abstract focuses
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`on its “decoding procedure,” and discusses encoding schemes only to emphasize
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`their unimportance, due to the broad applicability of its decoders, which it says can
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`be “applied to many existing systems” without modifying “the transmitter side.”
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`EX1005, Abstract. The field of invention describes “error correction of a received
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`data stream” and never once mentions encoding. EX1005, 1:7-11. The summary
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`likewise describes decoding, not encoding. EX1005, 4:28-59. Where the
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`specification describes encoding steps, the specification uses simple examples with
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`scant detail. See, e.g., EX1005, 7:46-8:2 (describing a “simple packet transmission
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`system” performing a Hamming encoding of just 4 bits at a time).
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`-6-
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`Petitioner takes advantage of Kobayashi’s sparse encoder description by
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`latching onto a single example encoder and reading in features that are simply not
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`there. Petitioner describes Kobayashi’s outer encoder as performing repetitions,
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`and in particular of multiplying input bits by “1” based on the entries in a generator
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`matrix G. Pet., 14-15. However, as discussed below in §IV.A, Kobayashi discloses
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`neither repetition nor multiplying for its outer encoder. Petitioner provides an
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`illustration of the purported multiplications and sums that Kobayashi performs
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`(Pet., 16), but this illustration is derived from Petitioner’s imagination, not
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`Kobayashi’s disclosure. Due to Petitioner’s misinterpretation of Kobayashi,
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`Petitioner repeatedly concludes that the outer encoder practices claim elements that
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`are neither expressly disclosed nor inherent. See infra §§IV.A-C.
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`Petitioner similarly mischaracterizes Kobayashi’s inner encoder. Petitioner
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`claims that “[w]hile duobinary signaling is depicted in Figure 8 as part of the
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`‘inner encoder,’ Kobayashi discloses that duobinary signaling is simply a
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`transmission technique, and thus the precoder is the inner encoder component that
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`performs the ‘second encoding’ step as claimed.” Pet., 17-18 n.7 (original
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`emphasis). This flatly contradicts Kobayashi. Kobayashi expressly states that there
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`are exactly two codes used on Fig. 8’s transmission side: the “outer code[ is] a
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`(7,4) Hamming code,” and “the inner code is duobinary signaling with a precoder.”
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`EX1005, 7:8-11. Thus, far from being simply a transmission technique, duobinary
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`-7-
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`signaling is a part of the inner code, just as much as the precoder is. Kobayashi
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`confirms this by illustrating the “inner encoder” as being both components
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`together, not just one taken alone. See EX1005, Fig. 8. Kobayashi also provides the
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`encoded sequence that results from the duobinary encoding, labeling it as “I5.” See
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`EX1005, 8:28-33. This duobinary sequence is easily distinguished from earlier
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`binary sequences because it contains “2”s in addition to “1”s and “0”s.
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`Kobayashi’s decoder subsequently uses duobinary sequences [interspersed with
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`error symbols] throughout much of its decoding process, confirming that the
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`duobinary sequence is the inner encoding, just as Kobayashi says it is. See
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`EX1005, 8:55-10:45. This is consistent with Kobayashi’s selection of the word
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`precoder to characterize that component of the inner encoder, suggesting it is a
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`first component that is used prior to forming a code via the operation of a second
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`component.
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`Petitioner’s citations to Kobayashi do not support its position that the
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`precoder alone functions as an encoder. The first citation (EX1005, 7:30-31)
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`simply states that duobinary signaling is used for transmission, not that duobinary
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`is not also an encoding step. The second citation is even worse for Petitioner’s
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`argument: it expressly describes duobinary signaling as a type of “partial-response
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`-8-
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`channel coding.”3 EX1005, 7:43-45. Kobayashi’s description of such coding as “a
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`bandwidth-efficient transmission technique” (EX1005, 2:21-25) does not mean that
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`Kobayashi’s duobinary signaling module is not also performing an encoding as an
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`essential part of the inner encoder—Kobayashi is simply describing that encoding
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`in that manner makes for bandwidth-efficient transmission. Lastly, the cited
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`footnote in the Valenti declaration adds nothing, merely parroting the petition
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`while adding the phrase “in my opinion.” EX1002, ¶69 n.3.
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`In sum, the petition’s discussion of Kobayashi is replete with
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`mischaracterization and inaccuracies. As discussed in §§IV-VI, these defects are
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`fatal to all of the petition’s grounds.
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`IV. GROUND 1 FAILS
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`Petitioner fails to show that Kobayashi anticipates claims 11-12, 14-17, 19,
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`21-22, 24-27, 29, and 32-33 of the ’710 patent. Yet as discussed below, Petitioner
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`fails to show that Kobayashi discloses multiple limitations in independent claims
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`11, 15, and 25. These limitations include the irregular repetition recited in each
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`independent claim, the first encoded data block formed of repeated bits as recited
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`in claim 11, and the scrambling of irregularly repeated bits as recited in claims 15
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`3 All emphasis added unless otherwise indicated.
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`-9-
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`and 25. Because Kobayashi has not been shown to disclose any of these
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`limitations, Ground 1 fails.
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`A. Kobayashi Does Not Disclose Irregular Repetition (All Claims)
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`The petition fails to show that Kobayashi discloses irregular repetition of
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`bits as recited in independent claims 11, 15, and 25. Claim 11 recites that “said
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`plurality of bits are repeated a different number of times,” and claims 15 and 25
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`each recite a “first coder operative to repeat said stream of bits irregularly.” None
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`of these limitations has been shown to be present in Kobayashi, either expressly or
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`inherently.
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`Broadly speaking, Petitioner asserts that Kobayashi’s outer (Hamming)
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`encoder discloses this limitation. See Pet., 12-17. As explained below, Kobayashi
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`does not describe irregular repetition or disclose any details of how the outer
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`encoder operates; it only provides the parity-check and generator matrices that
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`characterize the resulting output. Petitioner nonetheless argues that the irregular
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`repetition recited in the claims—i.e., repeating bits “a different number of times”
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`or “irregularly”—is in some way equivalent to operations that might be performed
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`by such an encoder, and that Kobayashi therefore discloses these claim limitations.
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`As discussed in the following sections, Petitioner misapplies claim construction
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`and anticipation principles and relies on flawed, self-contradictory reasoning to
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`conjure up irregular repetition from a reference that never discloses it.
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`-10-
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`1. Petitioner misinterprets the claims’ construction
`As discussed above in §II, Petitioner misinterprets the Federal Circuit’s
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`construction of “repeat,” stretching the actual construction to conclude that every
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`act of “multiplying a bit by a ‘1’ bit comprises ‘repeating’ the information bit,” on
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`the basis that passing a bit through an AND gate can perform an operation
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`“equivalent” to multiplying by “1.” Pet., 14-15. Petitioner then further extends this
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`interpretation, arguing that if an encoder, such as Kobayashi’s Hamming encoder,
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`performs a transform that can be characterized by a non-zero generator matrix with
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`different numbers of “1”s in different rows, then that encoder must necessarily
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`repeat bits different numbers of times or irregularly. See Pet., 15-16. Petitioner
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`does not justify its logical leap from a finding of infringement by a particular
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`device that duplicated bits and sent them through a specific configuration of AND
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`gates to a conclusion that every implementation of a transformation that could be
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`performed using binary multiplication must repeat bits.
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`The petition does not explain what it hopes to prove by referring to binary
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`multiplication as being “equivalent to” an AND gate. Pet., 14-15 (“Multiplying a
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`binary information bit by a ‘1’ bit is equivalent to passing the information bit
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`through an AND gate with a ‘1’ bit, and thus under this construction of ‘repeat,’
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`multiplying an information bit by a ‘1’ bit comprises ‘repeating’ the information
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`bit.”). Certainly, the petition never asserts that any of the ’710 patent’s claims
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`-11-
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`include a means- or step-plus-function limitation, nor does it perform the
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`corresponding analysis of whether the two types of operation are equivalents. Cf.,
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`e.g., MPEP §2183 (discussing factors supporting finding of equivalence in means-
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`and step-plus function claims). To the extent that Petitioner suggests that two
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`processes cannot be patentably distinct if they can produce equivalent outputs, this
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`reasoning would not satisfy the law of anticipation. “Anticipation requires identity
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`of the claimed process and a process of the prior art; the claimed process, including
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`each step thereof, must have been described or embodied, either expressly or
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`inherently, in a single reference.” Glaverbel Societe Anonyme v. Northlake Mktg.
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`& Supply, Inc., 45 F.3d 1550, 1554 (Fed. Cir. 1995). Even if two steps might
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`produce equivalent results, that would not make the steps themselves identical. As
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`to the ’710 patent claims, that a binary multiplication operation might produce an
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`output “equivalent” in some way to a repetition operation does not mean that a
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`process that could be accomplished with binary multiplication necessarily performs
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`a step of repetition, much less the particular irregular repetition recited in the
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`claims.
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`Regardless, as discussed below, even if Petitioner’s distortion of the Federal
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`Circuit’s opinion to equate multiplying input bits by “1” with repetition were
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`accepted, Kobayashi’s outer encoder does not expressly or inherently disclose
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`-12-
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`performance of such operations, and Petitioner’s attempt to stretch Kobayashi’s
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`disclosure to reach even their own interpretation of the claims is fatally flawed.
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`2. Kobayashi does not expressly disclose irregular repetition
`The petition asserts that in the outer (Hamming) encoder depicted in Fig. 8
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`of Kobayashi, “the information bits are repeated irregularly such that information
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`bits are repeated a different number of times.” Pet., 14-16. However, the petition
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`does not (as it could not) claim that Kobayashi expressly describes its outer
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`encoder as performing repetition, much less irregular repetition. See id. The
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`petition’s argument is instead premised on a theory that Kobayashi’s outer encoder
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`performs repetition by multiplying input bits by “1.” Id. However, even assuming
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`that multiplying bits by “1” constitutes repetition (which the petition fails to
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`substantiate, see supra §II), Kobayashi never discloses any such multiplication for
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`its outer encoder.
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`While Kobayashi describes the inputs to its encoder and how the encoder’s
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`output is mathematically related to its inputs, it provides almost no details as to
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`what process its outer encoder uses to generate its outputs. Kobayashi describes
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`Fig. 8 as having two codes: for “the outer code, a (7, 4) Hamming code is used and
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`the inner code is duobinary signaling with a precoder.” EX1005, 7:9-11.
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`Kobayashi never describes its outer (Hamming) encoder as performing repetition.
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`Kobayashi also never describes its outer encoder as multiplying input bits by
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`-13-
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`anything. Kobayashi says that a 28-bit packet is “segmented into blocks of k=4
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`bits, and each block is then encoded to a codeword of length n=7, by using a (7,4)
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`Hamming code.” EX1005, 7:49-65. Kobayashi specifies that the Hamming code’s
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`“parity-check and generator matrices are given in systematic form by” the
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`following matrices:
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`Id. The remainder of Kobayashi’s discussion of the outer encoder merely specifies
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`what the resulting 49 bit values are for its example input; thereafter, Kobayashi
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`discusses what is done subsequently with the output, never returning to elaborate
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`on how the outer encoder operates. See EX1005, 7:66-8:5. While Kobayashi
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`specifies the result of its encoding (namely, that the output of its encoder is related
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`to the input by the specified generator and parity-check matrices), it never provides
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`any details of how the output is actually computed. In particular, Kobayashi never
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`states that the bits input to the Hamming encoder are repeated in any way, much
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`less irregularly. Nor does Kobayashi say that the input bits are multiplied by “1”s
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`at all, and certainly not different numbers of times. Accordingly, even under
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`-14-
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`Petitioner’s interpretation of “repeat,” there is no express teaching in Kobayashi
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`that its outer encoder repeats bits at all, much less “irregularly” or “a different
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`number of times” as required by the independent claims.
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`3. Petitioner fails to show Kobayashi’s first encoder inherently
`performs irregular repetition
`In an attempt to avoid Kobayashi’s lack of express disclosure, Petitioner
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`turns to an inherency argument, but this argument is grounded in unsupported and
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`false assumptions. Petitioner’s case rests on a mistaken assumption that an encoder
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`characterized by a particular generator matrix necessarily performs a pattern of
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`repetitions corresponding to the “1”s in that generator matrix.
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`Inherency sets a high bar to show that a limitation is necessarily present in
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`the cited prior art. “[A]nticipation by inherent disclosure is appropriate only when
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`the reference discloses prior art that must necessarily include the unstated
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`limitation.” Therasense, Inc. v. Becton, Dickinson and Co., 593 F.3d 1325, 1332
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`(Fed. Cir. 2010) (quoting Transclean Corp. v. Bridgewood Servs., Inc., 290 F.3d
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`1364, 1373 (Fed. Cir. 2002)) (emphasis and alteration in original). “Inherent
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`anticipation requires that the missing descriptive material is ‘necessarily present,’
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`not merely probably or possibly present, in the prior art.” Trintec Indus., Inc. v.
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`Top-U.S.A. Corp., 295 F.3d 1292, 1295 (Fed. Cir. 2002) (quoting In re Robertson,
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`169 F.3d 743, 745 (Fed. Cir. 1999)).
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`-15-
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`In addition to the erroneous application of claim construction discussed in
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`§IV.A.1, Petitioner’s inherency argument relies on further mistaken reasoning.
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`Petitioner asserts that “any type of linear code using a non-zero generator matrix
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`will ‘repeat’ input bits because the process of multiplying a vector of information
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`bits by the generator matrix will necessarily involve multiplying input bits by ‘1’
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`bits.” Pet., 15. More specifically, Petitioner asserts that because Kobayashi’s
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`generator matrix G has different numbers of “1”s in different rows, the encoder
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`characterized by that generator matrix multiplies different input bits by “1”
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`different numbers of times, with this multiplication producing irregular repetition
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`of the input bits. See Pet., 15-16. However, Petitioner is wrong.
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`Even presuming Petitioner’s interpretation of the “irregular repetition”
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`limitations is correct (which, as discussed in §IV.A.1, it is not), Petitioner’s
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`reasoning still fails because Petitioner assumes the existence of operations by
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`Kobayashi’s encoder that are neither disclosed nor inherent. Petitioner’s assertion
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`(p. 15) that “any type of linear code using a non-zero generator matrix will ‘repeat’
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`input bits because the process of multiplying a vector of information bits by the
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`generator matrix will necessarily involve multiplying input bits by ‘1’ bits” is
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`unsubstantiated and simply not true. Petitioner points to nothing in Kobayashi
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`stating that any input bit of its Hamming encoder is multiplied by any bit at all.
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`This is unsurprising, since Kobayashi provides no details of how its Hamming
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`-16-
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`encoder transforms the input bits into output bits. Indeed, Kobayashi never states
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`that any of the elements depicted in the transmitter of Fig. 8 multiplies an input bit
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`by another bit. See EX1005, 7:5-8:33, Fig. 8. The petition also never explains why
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`it should be true that if an encoder is characterized by a nonzero generator matrix,
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`it necessarily performs its encoding using binary multiplication. See Pet., 15.
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`Petitioner’s further assertion that because Kobayashi’s generator matrix G
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`has different numbers of “1”s in different rows, the encoder multiplies different
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`input bits by “1” different numbers of times, thereby producing irregular repetition
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`of the input bits, fails for similar reasons. Since Kobayashi never describes any of
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`the input bits to the Hamming encoder being multiplied by anything, it certainly
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`never discloses them being multiplied by “1” different numbers of times. Nor is
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`there any explanation of why it would be necessary to multiply input bits by “1”
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`different numbers of times to produce the encoding described by Kobayashi. See
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`Pet., 15.
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`The testimony the petition cites to also fails to substantiate Petitioner’s
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`assertion that every encoder with a non-zero generator matrix must multiply input
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`bits by “1,” much less that Kobayashi’s encoder multiplies input bits by different
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`numbers of “1”s according to the rows of the generator matrix G. Dr. Valenti
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`repeats the petition’s statement “under this construction, any type of linear code
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`using a non-zero generator matrix will ‘repeat’ input bits because the process of
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`-17-
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`

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`multiplying a vector of information bits by the generator matrix will necessarily
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`involve multiplying input bits by ‘1’ bits,” but this circular argument puts the cart
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`before the horse. EX1002, ¶64. That is, Dr. Valenti assumes that Kobayashi
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`involves a “process of multiplying a vector of information bits by the generator
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`matrix” to reach the conclusion that such an operation necessarily multiplies input
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`bits by “1.” But the initial presumption that Kobayashi’s encoder multiplies
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`information bits by the generator matrix is unsupported. In the next sentence, he
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`states, “For example, as I described above, Kobayashi’s Hamming encoder
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`multiplies each 4-bit sub-block of I1 by the 4x7 generator matrix G, resulting in
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`seven 7-bit codewords.” EX1002, ¶65. However, this is the first time Dr. Valenti
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`actually asserted that Kobayashi performs such multiplications, and Kobayashi
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`itself says nothing about performing multiplications, so this assertion is
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`unsupported. See EX1002, ¶¶61-65. Dr. Valenti presents a figure (reproduced in
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`the petition at p. 16) purporting to show the multiplication, but this is Petitioner’s
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`creation, not Kobayashi’s disclosure. EX1002, ¶¶66-67.
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`Dr. Valenti also cites to his own discussion of “matrix multiplication and
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`modulo-2 arithmetic” (id. (citing EX1002, Section V.B (¶¶28-35)), but this
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`undermines his opinion rather than supporting it. There, he says that matrix
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`multiplication “is typically performed by taking the inner product of the vector
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`with each of the columns of the matrix” involving certain multiplication and
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`-18-
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`

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`addition operations, not that it can only be performed by such an inner product.
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`EX1002, ¶28. Far from confirming that Kobayashi necessarily performs matrix
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`multiplication in its first encoding or that such multiplication would necessarily
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`involve multiplication of bits, Dr. Valenti posits that this is merely possible, falling
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`short of establishing inherency.
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`4. Petitioner’s arguments are fatally inconsistent
`Petitioner’s own arguments undermine the assumptions of its inherency
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`case: those arguments imply that, contrary to the petition’s assertion, (1) a
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`component of an encoder can perform an operation that has a non-zero generator
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`matrix with different numbers of “1”s in different rows without performing any
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`irregular repetition of input bits whatsoever; and (2) an encoder could perform
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`Kobayashi’s Hamming encoding in particular without ever using an AND gate or
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`binary multiplication operation on the input bits. These conclusions are apparent
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`from Petitioner’s own statements in this and other petitions, and they are
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`substantiated by at least one further example of an encoder that encodes according
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`to Kobayashi’s Hamming code without any repetition of bits. In light of these fatal
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`deficiencies, Petitioner’s arguments cannot stand.
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`-19-
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`

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`The arguments elsewhere in the petition provide an example of why a
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`component of an encoder4 that can be characterized by a non-zero generator matrix
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`need not multiply input bits to perform its linear transform, and also need not
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`repeat input bits different numbers of times even if the generator matrix has
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`different numbers of “1”s in different rows. When discussing Kobayashi’s
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`precoder, Petitioner describes it as “an accumulator” that performs a “linear
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`transformation.” Pet., 19-20. Petitioner evokes the same misleading “equivalence”
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`reasoning as it uses for its irregular repetition arguments, asserting that “the
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`accumulation operation is equivalent to multiplying the 1x49 vector I3 by a 49x49
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`generator matrix GA,” which it says is constructed as follows:
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`
`
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`4 Petitioner misidentifies Kobayashi’s precoder as being an encoder that
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`performs the inner encoding operation. In fact, it is