ISSCC99 /SESSION 14 / PAPER TP 14.6
`
`TP 14.6
`
`A 70Mbls Variable-Rate DMT-Based
`Modem far VDSL
`
`Daniel Veithen, Paul Spruyt, Thierry Pollet, Miguel Peelers, Stijn Braet,
`Olivier Van de Wiel, Hugo Van De Weghe
`
`Alcatel Bell, Antwerp, Belgium
`
`Very high-speed digital subcriber line (VDSL) technology can
`deliver data a t multi-Mbits/s over the unshielded, twisted pair in
`overlay to the plain old telephone service (POTS) and ISDN
`services [l,21. Discrete multi-tone (DMT) is one candidate for the
`modulation of VDSL. The DMT transmit signal is the sum of
`independent quadrature amplitude modulated (QAM) carriers
`spread over a bandwidth of 11.04 MHz. Time division duplexing
`(TDD) is used to provide a half-duplex communication channel
`over a single pair [1,2]. This chip integrates the complete digital
`signal processing required by a TDD-DMT VDSL system and the
`Transport Convergence (TC) sublayer functions such a s
`(dehnterleaving, Reed-Solomon (de)coding, (de)scrambling,
`(de)framing and the ATM-specific TC functions (Figure 14.6.1). It
`can be used both a t the Network Termination (NT) and the Line
`Termination (LT) side.
`
`DMT modulation and demodulation is by an FFT/IFFT block. This
`block performs a 512 points real FFT in less than 2 0 ~ s . The FFT/
`IFFT is decomposed in complex radix-2, radix-4 and special resolve
`butterflies to combine results ofthe real FFT [31. The block is based
`on a dedicated pipelined dual ALU. ALUO can perform radix-4,
`radix-2 and special resolve butterflies. ALUl needs only perform
`radix-4 operations (Figure 14.6.2). ALUl is therefore 20% less
`complex than ALUO. To perform a complete 512 point real FFT,
`input data are read from the input buffer, pass ALU1, are
`temporarily reorganised in a small scratch buffer, pass ALUO and
`are stored in the output buffer. This process is repeated twice and
`the final result is available in the output buffer (Figure 14.6.2).
`Table 14.6.2 summarizes the configuration of both ALU for the
`IFFT and FFT during the 3 passes. Data and twiddle coefficients
`are coded as floating point with 13 bits mantissa and 4 bits
`exponent, avoiding the use of block floating point with interme-
`diate scaling between the radix [4]. Using a bit-true C++ model,
`optimum bit length for each intermediate stage of the ALU is
`derived. Simulations have shown that the noise generated by the
`FFTIIFFT block is well under the noise level of the VDSL system
`in the most favorable configuration.
`
`In the front-end receive part of the chip, a variable rate decimator
`is followed by a variable rate Time Equalization (TEQ) block
`implemented as a FIR filter with programmable coefticients. The
`length of the TEQ can be programmed from 1 to 32 taps depending
`on the application. In the transmit path, a variable rate interpo-
`lator shares the same hardware as the decimator, due to the TDD
`scheme.
`
`Symbol timing recovery uses a digital phase-locked loop (PLL).
`This DPLL can be programmed l o be of the second order or the
`third order with a bandwidth ranging from O.1Hz to 100Hz,
`depending on the location of the chip in the system. The phase
`difference between receiver and transmitter clock is measured a t
`the Demapper block and filtered out by a proportional-integral
`filter and then integrated to produce a value used to perform a
`digital rotation on each carriers in the frequency domain in both
`transmit and receive paths (Figure 14.6.1).
`
`A slave Utopia interface provides the chip with ATM cells. Scram-
`bling, header error control (HEC) generation and Idle cell inser-
`tion can be applied in the transmit direction. In the receive
`direction, basic ATM cell functions like cell synchronization,
`payload descrambling, idlehnassigned cell filtering and cell header
`detection and correction are provided.
`
`A fully programmable Reed-Solomon (RS) encoder protects against
`random and burst errors. The number of check bytes can be
`programmed from 0 to 16 Band the number of data bytes can be
`programmed from 2 to 255B. An interleaver protects against error
`bursts by spreading the errors over a number of RS code-words.
`It is a triangular interleaver, with parameter I ranging from 1 to
`255 and parameter M ranging from 1 to 34 (Figure 14.6.4). In the
`receive part, a programmable RS decoder and a deinterleaver
`perform the opposite transform. The parameters ranges are the
`same as for the transmit side. Two on-chip 32kB RAMS are
`provided to support the full parameter range for the interleaver
`and deinterleaver.
`
`For some services, a constant data delay is mandatory, even if the
`bit rate on the line is changing. Therefore, the parameters of the
`interleaveddeinterleaver and RS encodeddecoder can be modi-
`fied during normal operation of the chip, without any interruption
`or error generation. The synchronization between transmit and
`receive (of two different chips) is guaranteed by counting on both
`ends the number of transmitted and received RS code-words [61.
`
`All the blocks of the chip can be separately bypassed for debugging.
`A central block, the Timing Unit, is responsible for chip synchro-
`nization of the chip and proper sequencing of operations.
`
`A complete bit-true C model of the chip is available. The chip
`processes a 7OMbls data stream coming from or going to the Utopia
`interface.
`
`A buffer-tree used for clock distribution reduces power dissipated
`by the clock network. The characteristics of the chip are described
`in Table 14.6.1. A micrograph of the chip is available in Figure
`14.6.5.
`
`Acknowledgements:
`The authors thank F. De Meersman and H. Fabri for contribution
`to chip layout.
`
`The hardest noise encountered in VDSL system is radio-fre-
`quency interference (RFI). Its power spectral density is typically
`well above the received signal (Figure 14.6.3). A programmable
`digital RFI canceller works in the frequency domain 151. The RFI
`noise can be detected on 4 predefined frequency bands for each
`DMT symbol. The interference of two simultaneous RFI on the
`neighboring carriers can be reduced. The same floating-point
`format as for the FFTDFFT block is used here to cope with the data
`dynamics encountered in the presence of RFI. A windowing is
`performed on the samples in the time domain, just before the FFT.
`Combining this windowing with the digital RFI cancelling yields
`an interference reduction of 45dB on the neighboring carriers.
`
`References:
`I1 1 ETSI TM6, “VDSLAlliance SDMTVDSLDraft Standard Proposal”, Lulea,
`Sweden, June 22-26 1998.
`[21 ANSI TlE1.4/98-043R2, “VDSL System Requirements”, May 26, 1998.
`13 1A.V. Oppenheim, R.W. Schafer, Discrete-Time Signal Processing. Prentice-
`Hall, 1989.
`141 L. Kiss et al., “A Customizable DSP for DMT-based ADSL Modem”,
`Proceedings of the 24 th IEEE European Solid-state Circuits Conference,
`September 22-24,1998, The Hague, The Netherlands.
`L51 P. Spruyt,S. Braet,“Solvingthe IssueofRadioInterference whenDeploying
`Digital Subcriber Lines”, in Broadband Access Networks, D.W. Faulkner and
`A.L. Harmer(Eds.), 10s Press 1997, pp. 98-105.161 M. Peeters, P. Spruyt, “A
`Dynamic Interleaving Scheme for VDSL,” ANSI TlE1.4/97-052.
`161 R. Peters, PSpruyt, “A dynamic Interleaving Scheme for VDSL,”
`ANSI TlE1,4/97-052.
`
`248
`
`1999 IEEE International Solid-state Circuits Conference
`
`0-7803-5126-6/99 / $10.00 I O IEEE
`
`Authorized licensed use limited to: UCLA Library. Downloaded on January 24,2022 at 20:31:04 UTC from IEEE Xplore. Restrictions apply.
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1026
`Page 1 of 2
`
`
`
`TP 14.6
`
`A 70Mbls Variable-Rate DMT-Based
`Modem far VDSL
`
`Daniel Veithen, Paul Spruyt, Thierry Pollet, Miguel Peelers, Stijn Braet,
`Olivier Van de Wiel, Hugo Van De Weghe
`
`Alcatel Bell, Antwerp, Belgium
`
`Very high-speed digital subcriber line (VDSL) technology can
`deliver data a t multi-Mbits/s over the unshielded, twisted pair in
`overlay to the plain old telephone service (POTS) and ISDN
`services [l,21. Discrete multi-tone (DMT) is one candidate for the
`modulation of VDSL. The DMT transmit signal is the sum of
`independent quadrature amplitude modulated (QAM) carriers
`spread over a bandwidth of 11.04 MHz. Time division duplexing
`(TDD) is used to provide a half-duplex communication channel
`over a single pair [1,2]. This chip integrates the complete digital
`signal processing required by a TDD-DMT VDSL system and the
`Transport Convergence (TC) sublayer functions such a s
`(dehnterleaving, Reed-Solomon (de)coding, (de)scrambling,
`(de)framing and the ATM-specific TC functions (Figure 14.6.1). It
`can be used both a t the Network Termination (NT) and the Line
`Termination (LT) side.
`
`DMT modulation and demodulation is by an FFT/IFFT block. This
`block performs a 512 points real FFT in less than 2 0 ~ s . The FFT/
`IFFT is decomposed in complex radix-2, radix-4 and special resolve
`butterflies to combine results ofthe real FFT [31. The block is based
`on a dedicated pipelined dual ALU. ALUO can perform radix-4,
`radix-2 and special resolve butterflies. ALUl needs only perform
`radix-4 operations (Figure 14.6.2). ALUl is therefore 20% less
`complex than ALUO. To perform a complete 512 point real FFT,
`input data are read from the input buffer, pass ALU1, are
`temporarily reorganised in a small scratch buffer, pass ALUO and
`are stored in the output buffer. This process is repeated twice and
`the final result is available in the output buffer (Figure 14.6.2).
`Table 14.6.2 summarizes the configuration of both ALU for the
`IFFT and FFT during the 3 passes. Data and twiddle coefficients
`are coded as floating point with 13 bits mantissa and 4 bits
`exponent, avoiding the use of block floating point with interme-
`diate scaling between the radix [4]. Using a bit-true C++ model,
`optimum bit length for each intermediate stage of the ALU is
`derived. Simulations have shown that the noise generated by the
`FFTIIFFT block is well under the noise level of the VDSL system
`in the most favorable configuration.
`
`In the front-end receive part of the chip, a variable rate decimator
`is followed by a variable rate Time Equalization (TEQ) block
`implemented as a FIR filter with programmable coefticients. The
`length of the TEQ can be programmed from 1 to 32 taps depending
`on the application. In the transmit path, a variable rate interpo-
`lator shares the same hardware as the decimator, due to the TDD
`scheme.
`
`Symbol timing recovery uses a digital phase-locked loop (PLL).
`This DPLL can be programmed l o be of the second order or the
`third order with a bandwidth ranging from O.1Hz to 100Hz,
`depending on the location of the chip in the system. The phase
`difference between receiver and transmitter clock is measured a t
`the Demapper block and filtered out by a proportional-integral
`filter and then integrated to produce a value used to perform a
`digital rotation on each carriers in the frequency domain in both
`transmit and receive paths (Figure 14.6.1).
`
`A slave Utopia interface provides the chip with ATM cells. Scram-
`bling, header error control (HEC) generation and Idle cell inser-
`tion can be applied in the transmit direction. In the receive
`direction, basic ATM cell functions like cell synchronization,
`payload descrambling, idlehnassigned cell filtering and cell header
`detection and correction are provided.
`
`A fully programmable Reed-Solomon (RS) encoder protects against
`random and burst errors. The number of check bytes can be
`programmed from 0 to 16 Band the number of data bytes can be
`programmed from 2 to 255B. An interleaver protects against error
`bursts by spreading the errors over a number of RS code-words.
`It is a triangular interleaver, with parameter I ranging from 1 to
`255 and parameter M ranging from 1 to 34 (Figure 14.6.4). In the
`receive part, a programmable RS decoder and a deinterleaver
`perform the opposite transform. The parameters ranges are the
`same as for the transmit side. Two on-chip 32kB RAMS are
`provided to support the full parameter range for the interleaver
`and deinterleaver.
`
`For some services, a constant data delay is mandatory, even if the
`bit rate on the line is changing. Therefore, the parameters of the
`interleaveddeinterleaver and RS encodeddecoder can be modi-
`fied during normal operation of the chip, without any interruption
`or error generation. The synchronization between transmit and
`receive (of two different chips) is guaranteed by counting on both
`ends the number of transmitted and received RS code-words [61.
`
`All the blocks of the chip can be separately bypassed for debugging.
`A central block, the Timing Unit, is responsible for chip synchro-
`nization of the chip and proper sequencing of operations.
`
`A complete bit-true C model of the chip is available. The chip
`processes a 7OMbls data stream coming from or going to the Utopia
`interface.
`
`A buffer-tree used for clock distribution reduces power dissipated
`by the clock network. The characteristics of the chip are described
`in Table 14.6.1. A micrograph of the chip is available in Figure
`14.6.5.
`
`Acknowledgements:
`The authors thank F. De Meersman and H. Fabri for contribution
`to chip layout.
`
`The hardest noise encountered in VDSL system is radio-fre-
`quency interference (RFI). Its power spectral density is typically
`well above the received signal (Figure 14.6.3). A programmable
`digital RFI canceller works in the frequency domain 151. The RFI
`noise can be detected on 4 predefined frequency bands for each
`DMT symbol. The interference of two simultaneous RFI on the
`neighboring carriers can be reduced. The same floating-point
`format as for the FFTDFFT block is used here to cope with the data
`dynamics encountered in the presence of RFI. A windowing is
`performed on the samples in the time domain, just before the FFT.
`Combining this windowing with the digital RFI cancelling yields
`an interference reduction of 45dB on the neighboring carriers.
`
`References:
`I1 1 ETSI TM6, “VDSLAlliance SDMTVDSLDraft Standard Proposal”, Lulea,
`Sweden, June 22-26 1998.
`[21 ANSI TlE1.4/98-043R2, “VDSL System Requirements”, May 26, 1998.
`13 1A.V. Oppenheim, R.W. Schafer, Discrete-Time Signal Processing. Prentice-
`Hall, 1989.
`141 L. Kiss et al., “A Customizable DSP for DMT-based ADSL Modem”,
`Proceedings of the 24 th IEEE European Solid-state Circuits Conference,
`September 22-24,1998, The Hague, The Netherlands.
`L51 P. Spruyt,S. Braet,“Solvingthe IssueofRadioInterference whenDeploying
`Digital Subcriber Lines”, in Broadband Access Networks, D.W. Faulkner and
`A.L. Harmer(Eds.), 10s Press 1997, pp. 98-105.161 M. Peeters, P. Spruyt, “A
`Dynamic Interleaving Scheme for VDSL,” ANSI TlE1.4/97-052.
`161 R. Peters, PSpruyt, “A dynamic Interleaving Scheme for VDSL,”
`ANSI TlE1,4/97-052.
`
`248
`
`1999 IEEE International Solid-state Circuits Conference
`
`0-7803-5126-6/99 / $10.00 I O IEEE
`
`Authorized licensed use limited to: UCLA Library. Downloaded on January 24,2022 at 20:31:04 UTC from IEEE Xplore. Restrictions apply.
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1026
`Page 1 of 2
`
`
`
`ISSCC99/February 16,1999/Salon 8/4:15 PM
`
`TC sublayer
`
`DMT
`
`Fronl-End
`
`ALUO
`
`- l a
`- - - -
`radix-2,
`radix-4, 4 :
`special
`
`radix-4 cl. ALUl
`
`Input Buffer
`
`sidcos
`
`sidcos
`
`Output Buffer
`
`I
`Timing + Scheduling
`Figure 14.6.1: Chip block diagram.
`
`1
`
`Ingress RFI
`
`AWCN
`
`g
`2
`
`-110
`-140
`
`t Buffer
`
`Oitput Buffer
`
`Figure 14.6.2: FFT architecture.
`
`O.OE+OO
`
`Z.OE+O~
`
`~ . o E + o ~
`
`6 . 0 ~ t 0 6
`(Hz)
`( I ) Cable lype 26 AWG, 1 km
`AWCN =Average While Gaussian Noise
`Figure 14.6.3: RFI noise characteristics.
`
`~ . o E + o ~
`
`I . O E + O ~
`
`U
`M
`Figure 14.6.4: Interleaver.
`
`Technology
`Gate
`R A M
`Fsequenc y
`
`Package
`Transistors
`
`0.35 Fm 5-metal CMOS
`680k
`900kbit
`44.16 MHz
`150 mm2
`PQFP-208
`
`Figure 14.6.5: VDSL chip micrograph.
`
`Table 14.6.1: Chip characteristics.
`
`IFFT
`pass 1
`pass 2
`pass 3
`
`ALUO
`ALUl
`bypass
`special butterfly
`radix4 radix4
`radix-4 radix-4
`
`DIGEST OF TECHNICAL PAPERS
`
`249
`
`Authorized licensed use limited to: UCLA Library. Downloaded on January 24,2022 at 20:31:04 UTC from IEEE Xplore. Restrictions apply.
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1026
`Page 2 of 2
`
`
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