(12) United States Patent
`Fadavi-Ardekani et al.
`
`I 1111111111111111 11111 111111111111111 111111111111111 IIIII lll111111111111111
`
`US006707822B1
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,707,822 Bl
`Mar.16,2004
`
`(54) MULTI-SESSION ASYMMETRIC DIGITAL
`SUBSCRIBER LINE BUFFERING AND
`SCHEDULING APPARATUS AND METHOD
`
`(75)
`
`Inventors: Jalil Fadavi-Ardekani, Newport, CA
`(US); Walter G. Soto, Irvine, CA (US);
`Weizhuang Xin, Aliso Viejo, CA (US)
`
`(73) Assignee: Agere Systems Inc., Allentown, PA
`(US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 09/479,611
`
`(22) Filed:
`
`Jan. 7, 2000
`
`Int. Cl.7 .............................. H04B 1/38; H04L 5/16
`(51)
`(52) U.S. CI . .................... 370/395.5; 370/466; 370/480;
`375/222
`(58) Field of Search ................................. 370/230, 235,
`370/235.1, 395.1, 412, 428, 429, 395.5,
`480,503,505,511,512,513,514,516;
`375/222
`
`(56)
`
`References Cited
`
`U.S. PXI'ENT DOCUMENTS
`
`5,737,337 A * 4/1998 Voith et al .................. 714n02
`5,751,741 A
`• 5/1998 Voith et al .................. 714n58
`6,134,283 A
`• 10/2000 Sands et al. ................ 375/354
`6,233,250 Bl • 5/2001 Llu et al. .................... 370/469
`6,480,475 Bl • 11/2002 Modlin et al. .............. 370/294
`
`OTIIER PUBLICXTIONS
`
`U.S. Pub No.: 2002/0167949 Al (Bremer et al., Provisional
`Filing Date Apr. 4, 1999).*
`U.S. Pub. No.: 2002/0146014 Al (Karlsson et al., Filing
`Date Apr. 6, 2001).*
`
`U.S. Pub No.: 2203/0091053Al (Tzannes et al., Filing Date
`Oct. 4, 2002).*
`
`• cited by examiner
`
`Primary Examiner-Ricky Ngo
`Assistant Examiner-Kevin Mew
`(74) Attorney, Agent, or Firm--Synnestvedt & Lechner
`LLP
`
`(57)
`
`ABSTRACT
`
`A transceiver for an asymmetric communication system is
`provided that implements a buffering and scheduling scheme
`that utilizes a virtual clock signal to synchronize processing
`of asynchronous frame data for multiple ADSL sessions. In
`every virtual clock cycle, the transceiver first sequentially
`performs transmit-processes for each active ADSL line and
`then sequentially performs receive-processes for each active
`ADSLline. An Asynchronous Transfer Mode (ATM) Accel(cid:173)
`eratol provides the network interface to multiple XfM
`channels and communicates frame data to a Frame Buffer
`(FB). The FB may be used in a ping-pang fashion for the
`communication of data between the XfM accelerator and a
`Framer/Coder/Interleaver (FCI), which performs its
`namesake, among other, functions. The FCI also interfaces
`a Digital Signal Processing (DSP) core through an
`Interleave/De-Interleave Memory (IDIM). The DSP core
`generates the virtual clock signal, which schedules operation
`of the XI'M accelerator and the FCI. IDIM holds DMT
`frames of data and may also be utilized in a ping-pang
`fashion. Memory is shared by multiple ADSL sessions and
`by the transmit and receive processes within an individual
`session.
`
`26 Claims, 2 Drawing Sheets
`
`v22B
`
`16000
`DSP CORE
`
`232
`\
`
`/222
`
`ATM
`ACCELERATOR
`
`FRAME
`BUFFER
`12k X 16)
`
`224
`
`-
`
`f-'
`
`-
`
`FCI
`
`226
`
`-
`
`>
`
`INTERLEAVER/ v230
`DEINTERLEAVER
`RAM
`( 10k X 16)
`
`
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 1 of 9
`
`

`

`i,-
`~
`N
`N
`0'J
`-...,l
`Q
`':...l
`O'I
`rJ'J.
`e
`
`N
`
`'"""' 0 ....,
`~ ....
`'JJ. =(cid:173)~
`
`,i;;..
`0
`0
`N
`'"""' ~~
`~ :;
`~
`
`~ = ......
`
`~ ......
`~
`r'1
`~
`
`156
`
`150
`
`152
`
`154 ~----,
`
`TERMINAL
`EXTERNAL
`
`PHONE
`
`MOOEM
`
`DEVICE
`EXTERNAL
`
`I
`
`•
`
`1
`
`TRANSCEIVER I
`
`OSL
`
`151
`
`L
`i
`
`SPLITTER
`
`148
`
`138
`
`REMOTE TERMINAL
`
`DEVICE
`EXTERNAL
`
`124
`
`TRANSCEIVER I • • I SPLITTER Pl 126
`
`'
`---7
`
`""
`
`CENTRAL OFFICE----1._
`130
`
`---__
`~ ______ \_
`12
`
`120
`
`132
`
`NETWORK
`DIGITAL
`
`l_ ___ _
`
`DSC
`
`I
`'
`I .--'---
`!
`
`DSC
`
`144
`
`TERMINAL
`EXTERNAL
`
`142
`
`140
`
`MOOEM
`
`PHONE
`
`TRANSCEIVER
`i,....--136
`------, I
`,
`---------7
`
`I
`,
`,--------REMO-TE tERM-INAL
`
`.,__~
`
`SPLITTER
`
`I
`
`134
`
`-------L--__,
`
`_c!_
`122
`
`139
`
`FIG. 1
`
`100
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 2 of 9
`
`

`

`U.S. Patent
`
`Mar.16,2004
`
`Sheet 2 of 2
`
`US 6,707,822 Bl
`
`FIG. 2
`
`/228
`
`16000
`DSP CORE
`
`'
`
`'
`
`.
`
`232
`
`\
`
`✓
`
`' ~
`
`' ~
`
`v222
`
`ATM
`ACCELERATOR
`
`FRAME
`BUFFER
`(2k X 16)
`
`224
`
`.....
`
`-
`.
`
`FCI
`
`226
`
`,....
`
`-
`
`.
`-
`
`'
`
`INTERLEAVER/ v23o
`DEINTERLEAVER
`RAM
`( 10k X 16)
`
`FIG. 3
`
`320 VIRTUAL CLOCK
`
`322 Tx P~~~f~SING
`
`IDLEI TxO
`
`I Tx1 I Tx2
`
`I Tx3 I
`
`IDLE
`
`324 Tx COMPLETE _____ nL....-_ _ _
`
`I RxO
`Rx 1
`IDLE
`326 Rx PROCESSING
`STATE _________ ...J.... _ _ __,__ _
`-
`
`Rx2 I Rx3
`
`I IDLE
`
`_,_ _ _ --L... - -
`
`___,__ _
`
`328 Rx COMPLETE ________________ fL
`_ _ _ _ _ n_
`
`330
`
`PROCESSING
`COMPLETE
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 3 of 9
`
`

`

`US 6,707,822 B 1
`
`1
`MULTI-SESSION ASYMMETRIC DIGITAL
`SUBSCRIBER LINE BUFFERING AND
`SCHEDULING APPARATUS AND METHOD
`
`FIELD OF THE INVENTION
`
`The invention relates generally to broadband
`communications, and more particularly to the transmission
`of broadband signals using twisted-pair cable.
`
`2
`be sub-multiplexed to form multiple, lower rate channels
`utilizing one of several modulation technologies. One such
`modulation technology, Discrete MultiTone (DMT), is a
`multi-carrier technique that divides the available bandwidth
`of twisted-pair media connections into mini-subchannels or
`bins. In the ADSL standard, DMT may be used to generate
`up to 250 separate 4.3125 Khz subchannels from 26 Khz to
`1.1 Mhz for downstream transmission and up to 26 sub(cid:173)
`channels from 26 Khz to 138 Khz for upstream transmission.
`10 Other modulation technologies used with ADSL include
`Carrierless Amplitude Modulation (CAP) and Multiple Vir(cid:173)
`tual Line (MVL).
`At the central office in a typical ADSL system, a Digital
`Subscriber Line Access Multiplexer (DSLAM) multiplexes/
`de-multiplexes a unique set of data for each of multiple
`ADSL lines, concentrating the ADSL lines into a single
`terminating device for connection onto the backbone net(cid:173)
`work interconnecting central offices. An ADSL transceiver
`associated with each ADSL line is in communication with
`the DSLAM. For the unique data stream of each ADSL line,
`the ADSL transceiver provides data to ( and receives data
`from) several channels with the data grouped into frames
`that include both payload data bytes and overhead data
`bytes. Data from each channel is placed in different positions
`in a frame depending on whether the data is interleaved or
`non-interleaved. In general, for transmission, a frame is
`assembled from the payload data of the channels with
`overhead bytes appended as appropriate. In particular, a
`cyclic redundancy check (CRC), scramble, interleave (if
`selected), and forward error correction (FEC) are performed
`on the frame data prior to its transmission. The frames in
`turn are grouped together into a "superframe" which
`includes 68 data frames plus an additional synchronization
`frame, which delineates the superframe boundary. A CRC is
`35 performed on all the data in a superframe and transmitted in
`the overhead bytes of the first frame of the next superframe.
`The frame data is converted into a set of complex symbols,
`each of which represents a number of frame bits as defined
`by a bit allocation table. These complex symbols are sub-
`40 sequently converted into an analog signal that is transmitted
`on a twisted-pair. Conversely, when receiving an analog
`signal from a twisted-pair, an ADSL transceiver must con(cid:173)
`vert the analog signal into complex digital symbols, convert
`the complex symbols into a receive frame, and de-interleave,
`45 FEC, CRC, and de-scramble the received frame to recover
`payload data.
`In order to provide service to multiple remote end user
`premises, the central office of an ADSL communication
`system needs to support multiple ADSL lines, each line
`50 having a session or active period of data transfer. In addition,
`the central office must manage asynchronous downstream
`and upstream data streams for each ADSL session since, the
`recurrence of frames containing data for/from an individual
`remote end user is not necessarily periodic. In a conven-
`55 tional ADSL communication system, the central office has
`an ADSL transceiver for each remote end user served by the
`system. Such a system is excessively duplicative in terms of
`transceivers and memory in each transceiver, and thus more
`costly than necessary to provide the desired functionality.
`SUMMARY OF THE INVENTION
`The invention provides an Asymmetric Digital Subscriber
`Line (ADSL) transceiver that manages multiple asynchro(cid:173)
`nous ADSL sessions, synchronizing the digital signal pro(cid:173)
`cessing tasks for the sessions with a buffering and schedul(cid:173)
`ing scheme such that the various transceiver components
`operate seamlessly (i.e., in a semi-synchronous fashion).
`
`60
`
`15
`
`20
`
`25
`
`BACKGROUND
`High-speed data communications paths are desirable for
`Internet access and are essential for high data rate interactive
`services such as video on demand. Since fiber optic cable,
`the preferred transmission media for such services, is not
`readily available in the transmission link between a network
`node and a user premise and is prohibitively expensive to
`install, it is desirable to utilize the existing Plain Old
`Telephone Service (POTS) infrastructure. However, current
`POTS wiring connections consist of copper twisted-pair
`media which was designed for low frequency, voice-band
`(0---3400 Hz) analog telephony, and does not readily support
`the data rates or bandwidth required for high data rate
`interactive services. Conventional POTS analog transmis-
`sion is limited to a data rate of about 56 Kbps, which
`represents only a small portion of the amount of information
`that can be transmitted over twisted-pair media.
`DSL (Digital Subscriber Line) provides a method of
`communicating high-bandwidth data over twisted-pair 30
`media. In addition, some forms of DSL service ( e.g., ADSL)
`include a subdivision of the DSL bandwidth so that some
`bandwidth is used to provide POTS service simultaneously
`with data transmission. Thus, DSL enables high data rate
`interactive services without requiring the installation of fiber
`optic cable.
`Asymmetrical Digital Subscriber Line (ADSL (ANSI T
`1.413-1998)) is specifically designed to exploit the asym(cid:173)
`metric nature of most multimedia communication, in which
`large amounts of information flow toward an end user (i.e.,
`downstream) and only a small amount of information (e.g.,
`interactive control information) is returned by the end user
`to a central office (i.e., upstream). ADSL is "asymmetric" in
`that most of its two-way (duplex) bandwidth is utilized to
`transmit downstream and only a small portion is utilized for
`upstream transmission. Using ADSL, approximately 6-8
`Mbps of data can be sent downstream and approximately
`512 Kbps can be sent upstream. Other variations of DSL
`(i.e., xDSL) include High bit rate DSL (HDSL) and Very
`high bit rate DSL (VDSL).
`Many DSL technologies require that a signal splitter be
`installed at a remote end user location to split POTS service
`from the digital data transmission. However, the line split for
`an end user can be managed remotely from a central office
`using G.Lite (a/k/a DSL Lite, splitterless ADSL, and Uni(cid:173)
`versal ADSL), which is essentially a slower form of ADSL.
`Equipment installation costs are saved using G.Lite (ITU-T
`standard G-992.2), which provides a data rate of approxi(cid:173)
`mately 1.5 Mbps downstream and approximately 512 Kbps
`upstream.
`In a conventional ADSL communication system, an
`ADSL transceiver at each end of a twisted-pair ( a remote end
`user premise and a central office) connects to the twisted(cid:173)
`pair circuit, creating information channels-a high speed
`downstream channel, a medium speed upstream channel, 65
`and depending on implementation, a POTS or an Integrated
`Services Digital Network (ISDN) channel. Each channel can
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 4 of 9
`
`

`

`3
`Utilizing this buffering and scheduling methodology, reduc(cid:173)
`tions in the design sizes of various transceiver components
`and the data flow complexity of the transceiver may be
`achieved.
`A central office transceiver (i.e., headend processor)
`according to the invention includes various functional ele(cid:173)
`ments and memories coupled together with digital signal
`processing tasks synchronized by a virtual clock signal. An
`Asynchronous Transfer Mode (ATM) Accelerator provides
`the· network interface to multiple ATM channels for multiple 10
`asynchronous ADSL sessions. The ATM accelerator trans(cid:173)
`fers frame data to a Frame Buffer (FB) as controlled by a
`Digital Signal Processing (DSP) core. The FR provid~s a
`dual access memory that is used in a ping-pang fash10n,
`based on the logic level of the virtual clock, for the com(cid:173)
`munication of data between the ATM accelerator and a 15
`Framer/Coder/Interleaver (FCI). The FCI performs various
`processing tasks on the frame data and also interfaces the
`DSP core through an Interleave/De-interleave Memory
`(IDIM), which holds DMT frames of data and may also be
`utilized in a ping-pang fashion. The DSP core generates the 20
`virtual clock signal, which is approximately 4 Khz and
`coincides with the ADSL Discrete MultiTone (DMT) sym(cid:173)
`bol rate. The DSP core controls operation of the ATM
`accelerator and the FCI and performs various processing
`tasks such as moving data to/from the FB and the IDIM.
`According to the buffering and scheduling scheme of the
`invention, after every transition of the virtual clock signal
`(i.e., in every virtual clock cycle), the transceiver first steps
`through ADSL lines, performing FCI transmit-processes for
`each active ADSL line and generating a control signal after 30
`completing all transmit-processes. The FCI then again steps
`through ADSL lines, processing receive-processes for all
`active ADSL lines and generating control signals indicating
`completion of receive processes and completion of all
`processing.
`In every virtual clock cycle, the DSP core provides the
`FCI with data by reading Receive (RX) data frames to and
`loading Transmit (TX) data frames from the FB after pro(cid:173)
`cessing. The FB is divided into segments for each individual
`ADSL session with the same memory space used for both 40
`RX data and TX data. The FCI and ATM accelerator first
`perform reading processes and then loading processes, read(cid:173)
`ing RX data first before loading the TX data into the FB. In
`this way, the same buffer can be used for both RX data and
`TX data, thereby permitting the FB memory to be half the 45
`size of that in a conventional ADSL transceiver arrange(cid:173)
`ment. The DSP core also loads RX data frames and reads TX
`data frames to/from the IDIM, which may be used in a
`ping-pang fashion by the FCI and DSP core.
`Numerous other advantages and features of the present 50
`invention will become readily apparent from the following
`detailed description of the invention and the embodiments
`thereof, from the claims and from the accompanying draw(cid:173)
`ings in which details of the invention are fully and com(cid:173)
`pletely disclosed as a part of this specification.
`BRIEF DESCRIPTION OF THE DRAWINGS
`For a better understanding of the present invention, ref(cid:173)
`erence may be had to the following Detailed Description of
`exemplary embodiments thereof, considered in conjunction
`with the accompanying drawings, in which:
`FIG. 1 illustrates, in block diagram form, an Asymmetric
`Digital Subscriber Line (ADSL) system/in accordance with
`the invention;
`FIG. 2 illustrates, in block diagram form, an ADSL 65
`transceiver for a central office in accordance with the inven-
`tion;
`
`25
`
`35
`
`60
`
`Central Office ADSL Transceiver
`
`FIG. 2 illustrates a central office ADSL transceiver 120
`according to the invention. The transceiver implements a
`
`US 6,707,822 B 1
`
`4
`FIG. 3 illustrates, an exemplary processing sequencing for
`a case when four Transmit and Receive lines are enabled;
`In the detailed description below, like reference numerals
`are used to describe the same, similar or corresponding
`elements in FIGS. 1-3.
`
`DETAILED DESCRIPTION
`
`A headend transceiver (i.e., central office side processor)
`is provided for processing Asymmetric Digital Subscriber
`Line (ADSL) data. The provided ADSL transceiver imple(cid:173)
`ments a buffering and scheduling scheme for synchronizing
`the digital signal processing tasks for multiple asynchronous
`ADSL lines. As a result, the various components of the
`ADSL transceiver are able to operate seamlessly (i.e., in a
`semi-synchronous fashion) and the design sizes of various
`transceiver components and the data flow complexity of the
`transceiver are reduced. It should be noted, however, that the
`ADSL transceiver of the invention may alternatively incor(cid:173)
`porate other variations of DSL (i.e., xDSL), such as High
`bit-rate DSL (HDSL) and Very high bit-rate DSL (VDSL).
`
`Asymmetric Digital Subscriber Line
`Communication System
`
`FIG. 1 illustrates, in block diagram form, an Asymmetric
`Digital Subscriber Line (ADSL) system in accordance with
`the invention. The ADSL system 100 includes a central
`office 120 and remote end user terminals 122-124, which are
`connected together copper twisted-pair media forming a
`telephone line 126. The central office 120 includes anADSL
`transceiver according to the invention 128 and a splitter 130.
`Central office ADSL transceiver 128 is bi-directionally
`coupled to the splitter 130 and is additionally
`bi-directionally coupled externally to a digital network 132.
`A first remote end user terminal 122 includes splitter 134
`and conventional ADSL transceiver 136. ADSL transceiver
`136 is bi-directionally coupled to splitter 134 and is addi(cid:173)
`tionally coupled to external device 138. The splitter 134 is
`bi-directionally coupled via a Plain Old Telephone Service
`(POTS) channel 139 to a telephone 140 and is additionally
`coupled to a modem 142. The modem 142 is further coupled
`to an external terminal 144. The second remote end user
`terminal 124 is similarly arranged. The second remote end
`user terminal 124 includes a splitter 146 and a conventional
`ADSL transceiver 148. The ADSL transceiver 148 is
`bi-directionally coupled to the splitter 146 and is addition(cid:173)
`ally coupled to an external device 150. The splitter 146 is
`bi-directionally coupled via a POTS channel 151 to a
`telephone 152 and additionally coupled to a modem 154,
`which is further coupled to an external terminal 156.
`The exemplary digital communication system 100 allows
`high-speed data communication between a variety of remote
`end users having computers, telephones, fax machines,
`modems, television sets, and any number of other commu-
`55 nication devices. Digital network 132 is used to transmit
`information for a variety of high data rate interactive
`services, each of which may have a different transmission
`format and frequency. An exemplary digital communication
`system employing G.lite is similar to FIG. 1, with splitters
`130, 134 and 146 merely replaced by a hardware device
`providing a direct correction to ADSL transceivers 128, 136,
`and 148 respectively.
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 5 of 9
`
`

`

`US 6,707,822 B 1
`
`5
`buffering and scheduling scheme for synchronizing the
`processing of data on multiple ADSL lines (i.e., sessions),
`thereby enabling the various components of the transceiver
`to operate seamlessly (i.e., in a semi-synchronous fashion).
`In conventional ADSL, data arrives at and is transmitted by
`the ADSL transceiver asynchronously. The data is asynchro(cid:173)
`nous in the sense that the recurrence of frames containing
`information to/from an individual end-user are not neces(cid:173)
`sarily periodic. In addition, frame data does not necessarily
`arrive at the transceiver synchronous with a transition in a 10
`transceiver clock; the transceiver clock may not coincide
`with the start of any frame of data. Therefore, frame data
`must be buffered in order to make frame data for each ADSL
`line available for processing on a transition of a transceiver
`clock. The transceiver of the invention buffers and schedules 15
`these asynchronous communications for multi-session
`ADSL, synchronizing digital signal processing tasks utiliz(cid:173)
`ing an approximately 4 Khz virtual clock of the same
`frequency as the ADSL Discrete MultiTone (DMT) symbol
`rate. This buffering and scheduling scheme permits reduc(cid:173)
`tions in the design size of transceiver components and the
`data flow complexity of the transceiver.
`The ADSL transceiver of the invention 120 is a single
`integrated circuit which has various component including:
`an Asynchronous Transfer Mode (ATM) accelerator 222, a
`Frame Buffer (FB) 224, a Framer/Coder/Interleaver (FCI)
`226, a Digital Signal Processing (DSP) core 228, and a
`Interleave/De-Interleave Memory (IDIM) 230. The FCI 226
`interfaces the ATM accelerator 222 through the FB 224 and
`interfaces the DSP core 228 through the IDIM 230. Trans(cid:173)
`ceiver components that interface each other may be
`bi-directionally coupled via a bus 232, which refers to a
`plurality of signals or conductors which may he used to
`transfer one or more various types of information, such as
`data, address, control, or status information. In a preferred
`embodiment, the bus 232 is a sixteen bit bus. A virtual clock
`signal of approximately 4 Khz, which coincides with the
`ADSL DMT symbol rate, is generated by the DSP core 228
`and controls the operation of the ATM accelerator 222 and
`FCI 226.
`The Asynchronous Transfer Mode (ATM) accelerator 222
`is the network interface to multiple ATM channels (not
`shown). The ATM accelerator provides those functions that
`are responsible for data transport for a plurality of data
`streams communicated via twisted pair media. The data may
`be transported on any one of a plurality of programmable
`bearer channels. The data is synchronized into an appropri-
`ate one of the plurality of programmable bearer channels and
`the channels multiplexed in the ATM accelerator as deter(cid:173)
`mined by the ADSL standard. The ATM accelerator subjects
`this framed data to various operations that calculate a
`plurality of complex numbers representing DMT tones. The
`ATM accelerator subsequently transfers this DMT tone data
`on the twisted-pair media. In exemplary embodiments, the
`ATM accelerator may include UTOPIA-2 and serial port ss
`external network interface elements.
`The Frame Buffer (FB) 224 provides a dual access
`memory that is used in a ping-pang fashion to transfer
`unframed bearer channel data between the ATM accelerator
`222 and the FCI 226. "Ping-pang" means that areas of the
`memory buffer are alternately utilized exclusively by one
`agent ( a transceiver component for performing some
`function) and then by a second agent. As one area of memory
`is being used by a first agent, another area of memory can
`be used by a different agent. As long as different agents (in
`this case, the ATM accelerator and the FCI) access different
`areas of a dual access memory, there are no memory address
`
`6
`conflicts that could cause communication errors. At any
`time, an agent is allowed to access either a ping area of
`memory or a pang area of memory based on the logic level
`of the virtual clock signal. Thus, the FB should be allocated
`a memory of a size sufficient to provide ping-pang func(cid:173)
`tionality. In the preferred embodiment as illustrated in FIG.
`2, the frame buffer is allocated as two 1 Kx16 memory
`blocks, since the smallest Random Access Memory (RAM)
`block currently available is 1 Kx16.
`The Framer/Coder/Interleaver (FCI) 226 interfaces the
`ATM accelerator 222 through the FB 224. The FCI Supports
`multiple ADSL sessions and performs various tasks on
`payload data including: framing/de-framing, cyclic redun(cid:173)
`dancy check generation/checking (CRCing), scrambling/de(cid:173)
`scrambling, Reed-Solomon encoding/decoding, and
`interleaving/de-interleaving. The FCI may also provide Net-
`work Timing Reference generation and insertion, Interleave
`and Fast Path support, and access to its internal state and
`data in support of a test methodology using the DSP core as
`smart test controller. All functionalities of the FCI are
`20 provided as per ADSL standards. In a preferred embodiment
`of the invention, approximately four G.lite (ITU G.992.2) or
`approximately four ADSL (ANSI Tl .413-1998) sessions are
`supported by the FCI. It should be noted that the FCI is able
`to support additional sessions limited only by the size of the
`2s buffers with which it is interconnected and not limited to any
`specific implementation.
`The Digital Signal Processing (DSP) core 228 generates
`a virtual clock signal that controls the operation of the ATM
`accelerator 222 and the FCI 226. The virtual clock signal is
`30 an approximately 4 Khz signal that coincides with the ADSL
`DMT symbol rate. The DSP core 228 also responds to
`control signals generated by the ATM accelerator 222 and
`FCI 226 and performs various tasks such as moving data
`to/from the FB 224 and the IDIM 230. The DSP core may
`35 access the other components of the transceiver through a
`standard memory read/write operation. Alternatively, the
`components of the transceiver of the invention need not
`necessarily be co-located on a single computer chip. In that
`case the DSP core may access other transceiver components
`40 via a programmable (Direct Memory Access) DMA chan(cid:173)
`nels. DMA allows data to be sent directly from an attached
`device to the a processor's memory
`In the exemplary embodiment, the transceiver uses a
`Digital Signal Processor (DSP) core and is preferably imple-
`45 mented as a core of an DSP16K single chip DSP, which is
`available from Lucent Technologies, Inc., of Murrary Hill,
`N.J. it should be noted, however, that other types of pro(cid:173)
`cessor cores may also be utilized for the DSP core. Accord(cid:173)
`ing to the invention, processing components of the trans-
`so ceiver communicate with the DSP core. Other processing
`elements having additional functionality may be added to
`the transceiver as needed and implemented as peripheral
`modules to the DSP core. Thus, the invention is not limited
`to the particular components disclosed herein.
`The Interleave/De-Interleave Memory (IDIM) 230 pro-
`vides a memory through which the FCI 226 interfaces the
`DSP core 228. The IDIM holds DMT frames of data and
`may be utilized in a ping-pang fashion. The IDIM is used to
`transfer framed, coded and possibly interleaved data frames
`60 between the FCI core and the DSP Core. In addition to
`interleave data storage, the IDIM may contain a dedicated
`area for the transfer of fast path data to the DSP Core. The
`IDIM may be organized as 16 bit words with byte write
`capability to allow beneficial performance of various
`65 interleave/de-interleave processes.
`In a preferred embodiment of the invention, the IDIM is
`allocated as 10 Kx16 (i.e., 20 K) Random Access Memory
`
`CommScope, Inc.
`IPR2023-00066, Ex. 1006
`Page 6 of 9
`
`

`

`US 6,707,822 B 1
`
`7
`(RAM), which supports approximately four G .lite or
`approximately four standard ADSL session/sat less than full
`interleave depth. The size of the IDIM and the interleave
`depth may be varied so that a different number of sessions
`may be supported by the transceiver of the invention. The
`size of the IDIM is derived as follows. A simple implemen(cid:173)
`tation of a transmit interleaver for G.lite communication
`requires 4 Kbytes per session for downstream processing,
`derived by multiplying the maximum codeword length by
`the maximum interleaver depth. The simple G.lite transmit 10
`interleaver also requires 2 Kbytes per session for upstream
`processing. Therefore, 24 Kbytes of RAM is required to
`support four G.lite sessions. Similarly, a simple implemen(cid:173)
`tation of a transmit interleaver for standard ADSL requires
`16 Kbytes per session for downstream processing and 2 15
`Kbytes per session for upstream processing, for a total of 72
`Kbytes for four sessions. A fast path buffer is also required
`for fast path data in both the interleave and de-interleave
`processes and requires 256 bytes of RAM per session, or a
`total of 1 K bytes for four sessions. Since the smallest RAM 20
`block currently available is 1 Kx16, 1 Kx16or 2 Kbytesmust
`be allocated for the fast path buffer per direction. Therefore,
`a simple implementation of an interleaver would require 76
`Kbytes for four standard ADSL sessions ( 64 K interleave +8
`K de-interleave +4 K fast path). An optimal implementation 25
`of the interleaver according to the method of the invention
`utilizes the same memory for receive data and transmit data
`and thus requires 20 Kbytes to support a standard ADSL
`session at full interleave depth (16 K interleave &
`de-interleave +4 K fast path). With a lesser interleave depth, 30
`additional sessions may be supported with the same size
`buffer. With a larger buffer, additional session may be
`supported.
`It should be noted that in a preferred embodiment, the
`firmware required for performing processing tasks associ- 35
`ated with the central office is resident on the single inte(cid:173)
`grated circuit transceiver of the invention. As functions
`implemented in hardware are typically executed more
`quickly than those implemented in software, for optimal
`speed, central office transceiver of the invention implements 40
`its functions in hardware so that data is transmitted at a high
`rate. It should be noted, however, that similar functionality
`can be provided in a software implementation.
`
`Buffering and Scheduling Scheme
`To provide ADSL service, normal operation of the ADSL
`transceiver of the invention requires that, in every virtual
`clock cycle, the DSP core provide the FCI with data by
`reading one or more frames of Receive (RX) data from the
`FB (Frame Buffer) and loading one or more frames of
`Transmit (TX) data to the FB. In addition, the DSP core
`needs to load one or more frames of RX data to the IDIM
`and read one or more frames of TX data from the IDIM.
`FIG. 3 depicts an exemplary processing sequence accord(cid:173)
`ing to the invention for a case when four ADSL lines are
`enabled (i.e., four sessions are active). FCI processing is
`initiated by a transition of the virtual clock signal 320. Logic
`within the FCI captures the state of the virtual clock signal
`on successive CLK rising edges to detect the transition.
`Virtual clock signal transitions are generated by the DSP
`Core at an approximately 4 KHz rate (i.e., approximately
`69/68*4 KHz), locked to the modem frame rate and local
`timing reference. According to the buffering and scheduling
`scheme of the invention, after every transition of the virtual
`clock signal (i.e., in every virtual clock cycle), the FCI core
`first processes TX data for each active ADSL line 322
`(reading from the FB, framing, CRCing, scrambling, encod-
`
`8
`ing and interleaving). After processing TX data, the FCI core
`then processes RX data for each active ADSL line 326
`(deinterleavilg, decoding, CRCing, descrambling, and
`deframing, writing to the FB). This sequence of operations
`minimizes memory requirements by allowing the RX data to
`overwrite the same memory area in the FB that is used by the
`TX data, thereby permitting the size of the FB to be half that
`of a conventional ADSL transceiver. Since buffers/memory
`space consume integrated circuit area and add to the cost of
`a device, the memory savings and corresponding reduction
`in buffer size permitted by the invention reduces integrated
`circuit area and ADSL transceiver cost. In addition, since the
`single transceiver sequentially performs processing for mul(cid:173)
`tiple ADSL sessions, a central office that utilizes the ADSL
`transceiver of the invention consistently requires a lesser
`number of ADSL transceivers than prior art ADSL commu(cid:173)
`nications systems. While described in terms of an ADSL
`transceiver, the buffering and scheduling scheme of the
`invention may also be utilized in transceivers for various
`xDSL communication systems including High bit-rate DSL
`(HDSL) and Very high bit rate DSL (VDSL).
`In a given virtual clock processing cycle, the stream
`processing state machine (i.e., FCI) will first begin process(cid:173)
`ing TX data. The FCI will step through each TX line in
`increasing order, testing for enabled lines and i