a2) United States Patent
`US 6,314,137 B1
`(10) Patent No.:
`Onoet al.
`(45) Date of Patent:
`Nov.6, 2001
`
`
`US006314137B1
`
`(54) VIDEO DATA COMPRESSION SYSTEM,
`VIDEO RECORDING/PLAYBACK SYSTEM,
`AND VIDEO DATA COMPRESSION
`ENCODING METHOD
`Inventors: Koichi Ono, Yokosuka; Hideo
`Nishijima; Takayuki Kanesaki, both of
`Hitachinaka; Tadasu Horiuchi;
`Nobuyoshi Tsukiji, both of Yokohama,
`all of (JP)
`
`(75)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`(*) Notice:
`
`Subject to any disclaimer,the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/050,568
`
`(22) Filed:
`
`Mar. 30, 1998
`
`(30)
`
`Foreign Application Priority Data
`
`Mar. 31, 1997
`
`(IP) ecseseccessseesccsseseseresseesesseeeeeseneees 9-080082
`
`Tmt, C0 ne sssesssesenseceeesecereceecnecneneee HOAN 7/12
`(SL)
`(52) US. Ch ou.
`375/240; 375/240.01
`
`(58) Field of Search 0...ees 348/402, 409,
`348/14.1, 14.08, 159, 385.1, 705, 176
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,580,998 *
`3,582,542 *
`
`/1971 Hammond et al. oo. 348/159
`6/1971 Smierciak 0... eee 348/385.1
`
`6/1979 Dischert vsecseccccssceeeeee 348/176
`4,158,208 *
`
`. 348/14.08
`4,961,211 * 10/1990 Tsugane etal.
`.
`
`6/1993 HOmjo ..ccceccesssreeeseneeees 358/426
`5,223,949 *
`5,371,535 * 12/1994 Takizawa .....
`w 348/141
`5,488,482 *
`eee 348/402
`1/1996 Ueda et al.
`oe
`
`5,579,060 * 11/1996 Elberbaum ......eeeee 348/705
`FOREIGN PATENT DOCUMENTS
`
`KOKAI
`62-179280
`KOKAI
`64-65989
`
`8/1987 (IP).
`3/1989 (JP).
`
`* cited by examiner
`
`Primary Examiner—Chris Kelley
`Assistant Examiner—Allen Wong
`(74) Attorney, Agent, or Firm—Mattingly, Stanger &
`Malur, P.C.
`
`(57)
`
`ABSTRACT
`
`A video data compression/playback system efficiently com-
`presses a plurality of video data pieces through inter-frame
`predictive-encoding. Mixed video data VSMIr composedof
`time-divided video data received by video input terminals
`are divided video data pieces each of which corresponding
`to video input terminals and the video data pieces are written
`into memories respectively by a memorycontrol circuit for
`recording modc. The mixed video data written into the
`memoriesis read, a specified numberof framesat a time. An
`MPEGencoding circuit performs inter-frame predictive-
`encoding for each specified number of frames.
`
`13 Claims, 20 Drawing Sheets
`
`26
`
`
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`U.S. Patent
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`Nov.6, 2001
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`US 6,314,137 B1
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`U.S. Patent
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`Nov.6, 2001
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`Sheet 3 of 20
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`U.S. Patent
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`Nov.6, 2001
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`U.S. Patent
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`Nov.6, 2001
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`Sheet 5 of 20
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`US 6,314,137 B1
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`Nov.6, 2001
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`U.S. Patent
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`Sheet 13 of 20
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`US 6,314,137 Bl
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`1
`VIDEO DATA COMPRESSION SYSTEM,
`VIDEO RECORDING/PLAYBACK SYSTEM,
`AND VIDEO DATA COMPRESSION
`ENCODING METHOD
`
`BACKGROUND OFTHE INVENTION
`
`1. Field of the Invention
`
`This invention relates to a video data compression system,
`and moreparticularly to a compression encoding system for
`use in a video recording unit which sequentially switches
`video data obtained from a plurality of video cameras such
`as those used in a video surveillance system.
`2. Description of the Related Art
`Conventionally,
`a video surveillance system which
`records video from multiple video cameras (hereafter simply
`called cameras) onto a long-time recording time-lapse VTR
`has been used. This system uses a switcher to switch video
`from multiple cameras in a time-dividing manner.
`Earlier patent disclosures dealing with this type of video
`surveillance systems are found in Japanese Patent Laid-
`Open Application No. Sho 64-65989 and Japanese Patent
`Laid-Open Application No. Hei 5-73312.
`The system disclosed in Japanese Patent Laid-Open
`Application No. Sho 64-65989 synchronizes multiple cam-
`eras with the reference signal to eliminate the discontinuity
`of video signals at switching time.
`It also synchronizes the VTR recording timing with the
`video signal switching signal to minimize unstable operation
`time. This results in a shorter video switching period,
`making high-density recording possible.
`In addition, detecting at the time of playback, the camera
`identification signal superimposed on the video signal
`allows only the desired video to be selectively monitored.
`The system disclosed in Japanese Patent Laid-Open
`Application No. Hei 5-73312 switches timely between a
`2-system video selection means and a 2-system video signal
`synchronization means to enable a video surveillance
`system, which has cameras not under control of external
`synchronization signals or each controlled by ils own syn-
`chronization method,
`to synchronize video signals for
`proper switching.
`A system which switches multiple cameras in a time-
`division manner to combine their video signals into one
`mixed video signal is called a frame switcher. Many such
`systems are commercially available.
`Today, digital video recording and playback systems
`which record and play back digital image data have become
`popular.
`In general, image data to be recorded digitally is com-
`pressed to prevent the amount of data from increasing and
`theretore to allow the recording medium to be used for
`recording for a longer period oftime.
`Well-known image data compression techniques include
`JPEG (Joint Photographic Experts Group) and MPEG
`(Moving Pictures Experts Group).
`Because these techniques are described in detail in many
`books,
`the following briefly gives the summary of their
`algorithms.
`First, JPEG will be described
`JPEG divides an image into multiple small blocks and
`converts each block into two-dimensional frequency com-
`ponents through DCT (Discrete Cosine Transform). It then
`reduces the amount of data through non-linear quantization
`and entropy encoding.
`
`2
`A high intra-frame correlation in the image means closer
`two-dimensional frequency components, thus increasing the
`encoding efficiency and reducing the amount of data while
`ensuring the picture image quality.
`However, an image composedoffine patterns results in a
`lower intra-frame correlation and therefore decreases the
`
`compression efficiency. Thus, a compression ratio of up to
`10:1 is required to ensure a reasonable JPEG image.
`Next, MPEG will be described.
`In addition to the technique used by JPEG described
`above, MPEGusesan inter-frame correlation to reduces the
`amount of data. More specifically, it finds changes between
`every two frames and performs DCT onthe changes. Thisis
`called inter-frame predictive encoding.
`For slow-moving video with little or no change between
`frames, MPEG produces a very small amountof data.
`Even for
`fast-moving video, MPEG provides an
`extremely high predictive encoding efficiency because it
`detects motion vector between frames and motion compen-
`sation for them.
`
`As a result, the image quality is not degradedat all even
`when the compression ratio is several scores to one and,
`therefore, a recording/playback system using the MPEG
`compression algorithm can record video data longer in time
`than JPEG.
`
`SUMMARYOF THE INVENTION
`
`Time lapse VTRs, which record analog video signals on
`magnetic tapes, have been used in most conventional video
`surveillance systems. It is also possible to configure a video
`surveillance system using digital recording system
`explained above.
`That is, a system with only one camera digitizes the
`output video signals, reduces the amount of data by com-
`pressing data with MPEG,and records compressed data on
`a disk or tape.
`A system with multiple cameras has an MPEG compres-
`sion unit and a recording/playback unit installed for each
`camera to record digitized video signals sent from each
`camera.
`
`The problem is that a video surveillance system with
`multiple MPEG compression encoding units is very expen-
`sive because the MPEG compression encoding unit is very
`expensive. It is therefore preferable that, as with the con-
`ventional video surveillance system, the system has only one
`compression encoding unit which compresses video signals
`sent from multiple cameras for recording.
`However, compressing digitized mixed videosignals gen-
`erated by a frame switcher with MPEGposesthe following
`problem.
`In mostcases, video generated by separate cameras has no
`correlation. This means that the amount of changes among
`video obtained by separate cameras is much larger than the
`amount of changes among video obtained by the same
`camera.
`
`Therefore, a frequent switch among multiple cameras in
`the time divided manner affects inter-frame predictive
`encoding. Video data cannot be compressed efficiently for
`recording.
`This invention seeks to solve the problems associated
`with the prior art described above. It is an object of this
`invention is to provide a video data compression system,
`video recording/playback system, and video data compres-
`sion encoding method which efficiently compress multiple
`video data items through predictive encoding.
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`US 6,314,137 Bl
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`3
`To solve the above problems, a first embodiment of this
`invention is a video data compression system which com-
`presses mixed video data generated by mixing a plurality of
`video data items in a time-divided manner, wherein the
`mixed video data is compressed by performing inter-frame
`or inter-field predictive encoding for each of the plurality of
`video data items.
`
`For example, such a system comprises first storage means
`for storing the mixed video data; first control means for
`controlling writing and reading the mixed video data to and
`from the first storage means; and predictive encoding means
`for performing predictive encoding among a plurality of
`images of the mixed video data.
`The first control means writes the mixed video data into
`the first storage means, the mixed video data being divided
`into the plurality of video data pieces, and sequentially reads
`the mixed video data, a plurality of imagesat a time, for each
`of the plurality of video data items from the first storage
`means and wherein
`
`the predictive encoding meansperformspredictive encod-
`ing among a plurality of images of video data sequentially
`read, a plurality of images at a time, from the first storage
`means.
`
`In addition, when the mixed video data is composedof the
`plurality of video data items, each of the plurality of video
`data ilems sequentially appearing for a predetermined num-
`ber of images,
`the predictive encoding means performs
`predictive encoding on a plurality of images appearing at an
`interval of a number of images, the number being a product
`of the predetermined number of images, the number of the
`plurality of video data items, and a natural number.
`The first embodimentof this invention compresses mixed
`video data, composed of a plurality of video data items,
`through predictive encoding for each of the plurality of
`video data items, thus efficiently compressing the mixed
`video data.
`A second embodiment of this invention is a video data
`
`compression system which compresses a plurality of video
`data items, comprising video data acquisition means for
`sequentially acquiring a predetermined numberof video data
`images from the plurality of video data items on a frame
`basis or on a field basis; and predictive encoding means for
`compressing the mixed video data by performing predictive-
`encoding among the images of video data images sequen-
`tially acquired by the video data acquisition means.
`For example, the video data acquisition means comprises
`first storage means for storing the plurality of video data
`items; and first control means for controlling writing and
`readingthe plurality of video data items to and from thefirst
`storage means.
`The first control means divides each of the plurality of
`video data itemsat an interval of a predetermined numberof
`images, writes the divided video data into the first storage
`means, and sequentially reads the video data, a plurality of
`images at a time, for each of the plurality of video data
`pieces from the first storage means and
`the predictive encoding meansperformspredictive encod-
`ing amongthe plurality of images of video data sequentially
`read, a plurality of images at a time, from the first storage
`means.
`
`The second embodiment of this invention sequentially
`acquires a predetermined numberof video data images from
`a plurality of video data items and compressesthe video data
`by performing predictive encoding among a plurality of
`images of the acquired video data, thus compressing the
`plurality of video data items efficiently.
`
`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`5
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`FIG. 1 is a block diagram showing the outline of a video
`data recording/playback system used in a first embodiment
`of this invention.
`
`FIG. 2 is a diagram showing the outline of the synchro-
`nization switching circuit 5 shown in FIG. 1.
`FIG. 3 is a timing diagram showing the operation of the
`synchronization switching circuit 5 shown in FIG. 2.
`FIG. 4 is a diagram explaining the waveform ofthe signal
`used for a camera code included in a video signal output
`from the synchronization switching circuit 5 shown in FIG.
`2.
`
`15
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`FIG. 5 is a diagram showing the outline of the camera
`code determination circuit 12 shown in FIG. 1.
`
`FIG. 6 is a diagram showing the outline of the memory
`control circuit for recording mode 13 shown in FIG. 1.
`FIG. 7 is a timing diagram showing the operation of the
`memory controlcircuit for recording mode 13 shownin FIG.
`6.
`
`FIG. 8 is a timing diagram showing the operation of the
`memory controlcircuit for recording mode 13 shownin FIG.
`6.
`
`FIG. 9 is a diagram showing the outline of the MPEG
`encoding circuit 11 shown in FIG. 1.
`FIG. 10 is a timing diagram showing the operation of the
`MPEGencoding circuit 11 shown in FIG. 9.
`FIG. 11 is a diagram showing the outline of the MPEG
`decoding circuit 15 shown in FIG. 1.
`FIG. 12 is a diagram showing the outline of the memory
`control circuit for playback mode 21 shown in FIG. 1.
`FIG. 13 is a timing diagram showing the operation of the
`memory control circuit for playback mode 21 shownin FIG.
`12.
`
`FIG. 14 is a diagram showing the outline of the display
`control circuit 24 shown in FIG. 1.
`
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`
`FIG. 15 is a block diagram showing the outline of a video
`data recording/playback system of a second embodimentof
`this invention.
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`FIG. 16 is a diagram showing the outline of the MPEG
`encoding circuit 131 shown in FIG. 15.
`FIG. 17 is a diagram showing the outline of the picture
`reordering circuit 141 shown in FIG. 16.
`TIG. 18 is a timing diagram showing the operation of the
`picture reordering circuit 141 shown in FIG. 17.
`FIG. 19 is a diagram showing the outline of the image
`memory circuit 142 shown in FIG.15.
`FIG. 20 is a timing diagram showing the operation of the
`image memory circuit 142 shown in FIG. 19.
`FIG. 21 is a diagram showing the outline of the MPEG
`decoding circuit 132 shown in FIG. 15.
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`A first embodiment according to this invention will now
`be described with reference to the attached drawings.
`FIG. 1 is a block diagram showing the outline of a video
`data recording/playback system usedin the first embodiment
`according to this invention.
`In the figure, numbers1 to 4 refer to video input terminals,
`number 5 refers to a synchronization switching circuit,
`numbers 6-9 and numbers 16-19 refer to memory, number
`11 refers to an MPEG encoding circuil, number 12 refers to
`
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`5
`a camera code determination circuit, number 13 refers to a
`memory control circuit for recording mode, number 14
`refers to a recording/playback module, number 15 refers to
`an MPEGdecoding circuit, number 21 refers to a memory
`control circuit for playback mode, number 23 refers to a
`camera code addition circuit, number 24 refers to a display
`control circuit, number 25 refers to a video output terminal,
`number26 refers to a video decoder circuit, and number 27
`refers to a video encodercircuit. Number10 refers to a frame
`
`switcher composed of the synchronization switching circuit
`5 and the display control circuit 24.
`The video input
`terminals 1-4 receive analog video
`signals from the cameras not shown in the figure.
`The synchronization switching circuit 5 converts the four
`analog video signals received by the video input terminals
`1-4 to digital signals, synchronizes and sequentially
`switches the four video signals, and outputs them as one
`mixed video signal. In addition, the circuit adds camera
`codes each identifying the four video signals to the corre-
`sponding part of the mixed video signal.
`The video decoder circuit 26 converts the mixed video
`
`signal from the synchronization switching circuit 5 to video
`data VSMIr which is composedof three signals: a luminance
`signal and two color difference signals composed of the
`oumber of picture elements corresponding, to the MPEG
`encoding format.
`The camera code determination circuit 12 detects the
`
`camera codes in the mixed video signal output from the
`synchronization switching circuit 5.
`Memory (1R) 6 to memory (4R)9 store the corresponding
`part of the video data VSMIr.
`The memorycontrol circuit for recording mode 13 con-
`trols memory containing the video data VSMIr from the
`video decoder circuit 26 according to the camera codes
`determined by the camera code determination circuit 12.
`In this embodiment, the video data VSMIris controlled
`according to the camera codes as follows. That
`is,
`the
`memory (1R) 6 to the memory (4R) 9 are controlled such
`that the video data correspondingto the video signal entered
`from the video input terminals 1 is stored in the memory
`(1R) 6,
`the video data corresponding to the video signal
`entered from the video input terminals 2 is stored in the
`memory (2R) 7, the video data corresponding to the video
`signal entered from the video input terminals 3 is stored in
`the memory (3R) 8, and the video data corresponding to the
`video signal entered from the video input terminals 4 is
`stored in the memory(4R) 9.
`The memorycontrol circuit for recording mode 13 also
`sequentially accesses the memory (1R) 6 to the memory
`(AR) 9 to read anyframes of video data VSMIrstored in each
`memory.
`In this way, the video data VSMIr from the video decoder
`circuit 26 is converted to video data VSMOr where sequence
`of frames has been changed. ‘The video data VSMOrwill
`consist a sequence of frames each of which corresponding to
`the signals reccived by video input terminals 1 to 4.
`The MPEG encoding circuit 11 encodes the video data
`VSMOrusing MPEG format and outputs it as an MPEGbit
`stream BSr.
`
`Atthis time, the MPEG encodingcircuit 11 adds camera
`code data to the bit stream BSr according to the instruction
`generated by the memory controlcircuit for recording mode
`13. The camera code data is that of the video signals from
`which VSMOrwas generated, which was in turn converted
`to the bil stream BSr.
`
`6
`The recording/playback module 14 records the bit stream
`BSr output from the MPEGcodingcircuit 11 on a recording
`medium such as a disk or tape. It also plays back the bit
`stream from the recording medium and outputs the played-
`back bit stream BSp.
`The MPEG decoding circuit 15 decodes the bit stream
`BSp played back by the recording/playback module 14 and
`converts it to video data VSMIp composed of the luminance
`signal and the color difference signals. It also detects the
`camera codes added to the bit stream BSp.
`The memory (1P) 16 to the memory (4P) 19 eachstore the
`corresponding part of the video data VSMIp output from the
`MPEGdecoding circuit 15.
`The memory control circuit for playback mode 21 con-
`trols memory to contain the video data VSMIp output from
`the MPEG decoding circuit 15 according to the camera
`codes detected by the MPEG decodingcircuit 15.
`In this embodiment, the video data VSMIp decoded by the
`MPEG decoding circuit 15 is controlled according to the
`camera codesas follows. That is, the memory (1P) 16 to the
`memory (4P) 19 are controlled such that the video data
`corresponding to the video signal entered from the video
`input terminals 1 is stored in the memory (1P) 16, the video
`data corresponding to the video signal entered from the
`video input terminals 2 is stored in the memory (2P) 17, the
`video data corresponding to the video signal entered from
`the video input terminals 3 is stored in the memory (3P) 18,
`and the video data corresponding to the video signal entered
`from the video input terminals 4 is stored in the memory
`(4P) 19.
`The memory control circuit for playback mode 21 also
`accesses the memory (1P) 16 to the memory (4P) 19
`sequentially to read video data VSMIp sequentially, one
`frame at a time. This way, it generates video data VSMOp
`composed of frames generated from the video data corre-
`sponding to the video input terminals 1-4, with a frame from
`a terminal sequentially followed by a frame from the next.
`The video encoder circuit 27 converts the video data
`VSMOpto the composite video signal.
`The camera code addition circuit 23 adds the correspond-
`ing camera code to the composite video signal, converted by
`the video encoder circuit 27, during the vertical blanking
`interval according to the instruction from the memory con-
`trol circuit for playback mode 21.
`In a similar manner as the reproduction process of the
`conventional frame switcher, the display control circuit 24
`determines the camera cade and outputs the video signal
`from the video output terminal 25 so that only the vidco of
`the desired camera may be selectively displayed.
`The video output terminal 25 is connected to a monitor,
`not shownin the figure, on which video is displayed.
`Next,
`the components of the video data recording/
`playback system shown FIG. 1 are described in more detail.
`First,
`the synchronization switching circuit 5 will be
`described.
`
`FIG. 2 is a diagram showing the outline of the synchro-
`nization switching circuit 5.
`In this figure, number 31 refers to a video selection circuit
`A, number32 refers to a video selection circuit B, number
`33 refers to an input timing signal generation circuit, num-
`bers 34 and 35 refer to A/D converters, numbers 36 and 37
`refer to switching circuits, number38 refers to a FIFO (First
`IN First Out) memory A, number 39 refers to a FIFO
`memory B, number 40 refers to a write control circuit A,
`number 41 refers to a wrile control circuil B, number 42
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`US 6,314,137 Bl
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`7
`refers to a read control circuit A, number 43 refers to a read
`control circuit B, number 44 refers to an output selection
`circuit, number 45 refers to a reference timing signal gen-
`eration circuit, and number 47 refers to a camera code
`addition circuit.
`
`‘The video selection circuit A 31 selects one of analog
`video signals VS1-VS4entered from the video input termi-
`nals 1-4 according to a control signal SA from the reference
`timing signal generation circuit 45.
`The video selection circuit B32 selects one of analog
`video signals VS1-VS4entered from the video input termi-
`nals 1-4 according to a control signal SB from the reference
`timing signal generation circuit 45.
`The A/D converter 34 converts the analog video signa
`selected by the video selection circuit A 31 to the digita
`signal.
`The A/D converter 35 converts the analog video signa
`selected by the video selection circuit B 32 to the digita
`signal.
`The video signal output from the A/D converter 34 is
`written into the FIFO memory A 38 according to the contro
`signal MWAsent from the write control circuit A 40, and the
`video signal VQA written into the FIFO memory A 38 is
`read according to the control signal MRAsent from the read
`control circuit A 42.
`
`
`
`The video signal output from the A/D converter 35 is
`written into the FIFO memory B 39 accordingto the contro
`signal MWBsentfrom the write control circuit B 41, and the
`video signal VQB written into the FIFO memory B 39 is
`read according to the control signal MRB sent from the read
`control circuit B 43.
`
`The output selection circuit 44 selects one of the video
`signal VQAread from the FIFO memory A 38 andthe video
`signal VQBread from the FIFO memory B 39 according to
`the control signal SQ sent from the reference timing signal
`generation circuit 45.
`The reference timing signal generation circuit 45 uses an
`internal crystal oscillator and so on to generate the 4fsc clock
`signal with the frequencythatis four times as high as that of
`the color sub-carrier. It supplies control signals generated
`based on the 4fsc clock signal.
`‘The camera code addition circuit 47 generates camera
`codes, based on the video selection information from the
`video selection circuit A31, video selection circuit B 32, and
`output selection circuit 44, and adds the camera codesto the
`output video signal VO from the output selection circuit 44
`during the vertical blanking interval.
`‘The input timing signal generation circuit 33 separates the
`horizontal sync signal and the vertical sync signal from the
`vidco signals VS1—VS4received bythe video input termi-
`nals 1-4. Based on the separated horizontal sync signal and
`the vertical sync signal, the input timing signal generation
`circuit generates the start timing and the end timing of a
`frame of the video signal. For each of the video signals
`VS1-VS4,the input timing signal generation circuit also
`generates the 4fsc clock signal which is in phase lock with
`the sub-carrier of the signal.
`The start timing and the end timing of a frame of the
`signal and the 4fsc clock signal, which are generated for
`each of the analog video signals VS1-VS4,are called the
`input timing of the signal.
`The switching circuit 36 selects and outputs one of input
`timings from those of each of video signals VSI-VS4,
`generated by the input timing signal generation circuit 33,
`according to the control signal SA sent from the reference
`uming signal generation circuit 45.
`
`8
`The switching circuit 37 sclects and outputs one input
`timing from those of each of video signals VS1-VS4,
`generated by the input timing signal generation circuit 33,
`according to the control signal SB sent from the reference
`timing signal generation circuit 45.
`The write control circuit A 40 generates the control signal
`MWAwhich causes one frame of the video signal to be
`written into the FIFO memory A 38 according to the control
`signal from the reference timing signal generation circuit 45
`and the input timing from the switching circuit 36. The
`circuit also supplies the 4fsc clock signal, included in the
`input timing, to the A/D converter 34.
`The write control circuit B 41 gene