CA 02247588 2003-04-24
`
`77575-7
`
`means for evaluating the headers to determine the
`
`formats of the corresponding packets, and
`
`means for causing the packets to arrive at the
`
`module corresponding to their formats.
`
`IPR2022-01227
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`

`

`CA 02247588 1998-12-15
`
`31.
`
`The system according to claim 29 further including
`
`a time-division-multiplexed bus connecting the voice data processing modules and the
`
`router.
`
`32.
`
`The system of claim 29 wherein the first means includes
`
`meansfor receivingthefirst data stream,
`
`means for processing the first data stream to extract information according to the
`
`format corresponding to that module, and
`
`means for formatting the extracted information in the intermediate format.
`
`33.
`
`The system of claim 32 wherein the first means also includes
`
`buffering meansfor rate adaption.
`
`34.|The system of claim 32 wherein the first means also includes
`
`means for performing cell delay variation compensation.
`
`35.|The system according to claim 32 further including
`
`a time-division-multiplexed bus connecting the voice data processing modules and the
`
`router.
`
`36.
`
`The system of claim 35 wherein the means for formatting the extracted information
`
`into the intermediate format includes
`
`meansfor placing the extracted information into appropriate slots in the time-division-
`
`multiplexed bus.
`
`37.
`
`The system of claim 32 wherein the second meansincludes
`
`meansfor assembling needed information from the intermediate format,
`
`means for organizing the assembled information according to the format
`
`correspondingto this module, and
`
`meansfor placing the organized information into the second data stream.
`
`17
`
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`

`

`CA 02247588 1998-12-15
`
`38.
`
`The system according to claim 37 further including
`
`a time-division-multiplexed bus connecting the voice data processing modules and the
`
`router.
`
`39.
`
`The system of claim 38 wherein the means for assembling includes
`
`meansfor selecting the information from appropriate slots of the time-division-
`
`multiplexed bus.
`
`40.
`
`The system of claim 29 further comprising
`
`a time slot interchanger coupled to the voice data processing modules.
`
`41.
`
`The system of claim 29 wherein the switch includes
`
`an egress control circuit for arbitrating among the voice data processing modules.
`
`42.
`
`The system of claim 29 wherein the router includes
`
`ATMingresscircuitry coupled to the voice data processing modules.
`
`43.|The system of claim 42 wherein the ATM ingresscircuitry includes
`
`header extraction circuitry for extracting a VPI/VCI headerfrom thefirst data stream.
`
`44.
`
`The system of claim 43 wherein the ATM ingresscircuitry includes
`
`means for forming module identification signals from the extracted header.
`
`45.
`
`The system of claim 43 wherein the ATM ingresscircuitry includes
`
`means for forming data type signals from the extracted header.
`
`18
`
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`
`

`

`CA 02247588 2003-04-24
`
`77575-7
`
`46.
`
`An interworking device receiving a first data
`
`stream in a plurality of formats,
`
`the device comprising:
`
`a plurality of data processing modules capable of
`
`operating in parallel, each of the modules including
`
`first means for converting the first data steam
`
`from one of the plurality of formats to a data stream in an
`
`intermediate format, and
`
`second means for converting data streams in the
`
`intermediate format to a second data stream;
`
`10
`
`a router for sending to the appropriate one of the
`
`modules portions of the first data stream with the
`
`corresponding formats; and
`
`a switch for switching the data stream in the
`
`intermediate format between different ones of the modules.
`
`SMART & BIGGAR
`
`OTTAWA, CANAGA
`
`PATENT AGENTS
`
`IPR2022-01227
`IPR2022-01227
`EXHIBIT 1003 - PAGE 00404
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`
`

`

`CA 02247588 1998-12-15
`
`FORTY EIGHT OCTETS FROM ONE DSO
`
`HORTsor[osoe||
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`SIX DSOs WITH 8 OCTETS FROM EACH
`
`[Horoso1psoaosodosoq
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`TWELVE DSO’s WITH 4 OCTETS FROM EACH
`
`HORTVETET
`
`FORTY EIGHT DSO’s WITH 1 OCTET FROM EACH
`
`DELAY AND BANDWIDTH REQUIRED FOR DIFFERENT SIZE “TRUNKS”
`IN THE VOICE OVER ATM MULTIPLEX FORMATS
`
`MPSS| BERSEHE|PORE|carne
`PERCELL oeEACH DSO
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`FIG. 1
`
`IPR2022-01227
`IPR2022-01227
`EXHIBIT 1003 - PAGE 00405
`EXHIBIT 1003 - PAGE 00405
`
`

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`IPR2022-01227
`EXHIBIT 1003 - PAGE 00406
`EXHIBIT 1003 - PAGE 00406
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`IPR2022-01227
`EXHIBIT 1003 - PAGE 00407
`EXHIBIT 1003 - PAGE 00407
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`IPR2022-01227
`IPR2022-01227
`EXHIBIT 1003 - PAGE 00408
`EXHIBIT 1003 - PAGE 00408
`
`

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`CA
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`IPR2022-01227
`IPR2022-01227
`EXHIBIT 1003 - PAGE 00409
`EXHIBIT 1003 - PAGE 00409
`
`
`
`
`

`

`CA 02247588 1998-12-15
`
`ATM
`19.44 MHz
`
`
`630
`
`TDM
`
`
`
`ATM
`
`
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`READ SIGNAL
`FROM CONTENTION
`
`CIRCUITRY
`
`MXT3010
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`FRAME
`PULSE
`
`FIG. 6
`
`READ SIGNAL
`FOR VoA MODULE #1
`
`READ SIGNAL
`FOR VoA MODULE #N
`
`
`
`ATM BUS CLk
`TDM FRAME PULSE
`
`EGRESS CONTENTION
`CIRCUITRY
`
`
`255
`
`FIG. 7
`
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`EXHIBIT 1003 - PAGE 00410
`EXHIBIT 1003 - PAGE 00410
`
`

`

`240
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`EXHIBIT 1003 - PAGE 00411
`EXHIBIT 1003 - PAGE 00411
`
`

`

`
`
`oO)
`
`Europdisches Patentamt
`European Patent Office
`Office européen des brevets
`
`AMM
`
`
`(1) Publication number: 0 614 317 A2
`
`2)
`
`EUROPEAN PATENT APPLICATION
`
`@1) Application number : 94301252.6
`@2) Date offiling : 22.02.94
`
`Priority : 05.03.93 JP 45112/93
`
`Date of publication of application -
`07.09.94 Bulletin 94/36
`
`Designated Contracting States :
`DE FR GB IT NL
`
`@4) Applicant : SONY CORPORATION
`7-35 Kitashinagawa 6-chome
`Shinagawa-ku
`Tokyo 141 (JP)
`
`6) Int. cl: HO4N 7/13
`
`@) Inventor : Koyanagi, Hideki, c/o Intellectual
`Property Div.
`Sony Corporation,
`6-7-35 Kitashinagawa
`Shinagawa-ku, Tokyo 141 (JP)
`Inventor : Sumihiro, Hiroshi, c/o Intellectual
`Property Div.
`Sony Corporation,
`6-7-35 Kitashinagawa
`Shinagawa-ku, Tokyo 141 (JP)
`Inventor : Emoto, Seiichi, c/o Intellectual
`Property Div.
`Sony Corporation,
`6-7-35 Kitashinagawa
`Shinagawa-ku, Tokyo 141 (JP)
`Inventor : Wada, Tohru, c/o Intellectual
`Property Div.
`Sony Corporation,
`6-7-35 Kitashinagawa
`Shinagawa-ku, Tokyo 141 (JP)
`
`Representative : Robinson, Nigel Alexander
`Julian et al
`D. Young & Co.,
`21 New Fetter Lane
`London EC4A 1DA (GB)
`
`
`
`63
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`Video signal decoding.
`
`that has been encoded
`i) A digital video signal
`using motion- compensated prediction,
`trans-
`form encoding, and variable-length coding,
`is
`decoded using parallel processing. Frames of
`the video signal are dividedinto slices (1, 2, 3, 4)
`made up of a sequence of macroblocks (MB).
`The signal
`to be decoded is slice-wise divided
`for parallel variable-length decoding. Each vari-
`able-length-decoded macroblock is divided into
`its constituent blocks for parallel
`inverse trans-
`form processing. Resulting blocks of difference
`data are added in parallel
`to corresponding
`blocks of reference data. The blocks of refer-
`
`ence data corresponding to each macroblock
`are read out
`in parallel
`from reference data
`memories (44, 45, 46, 47) on the basis of a
`motion vector (83) associated with the macrob-
`lock. Reference data corresponding to each
`macroblock is distributed for storage among a
`number of reference data memories.
`
`EP0614317A2
`
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`
`35,
`
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`IPR2022-01227
`IPR2022-01227
`EXHIBIT 1003 - PAGE 00412
`EXHIBIT 1003 - PAGE 00412
`
`

`

`1
`
`EP 0 614 317 A2
`
`2
`
`This invention relates to decoding of prediction-
`codedvideosignals, and more particularly is directed
`to the application of parallel processing to such de-
`coding.
`Itis known to perform compression coding on vid-
`eo data which represents a movingpicture in order to
`reduce the quantity of data to be recorded and/or
`transmitted. Such data compression may be useful,
`for example, in recording/reproducing systems using
`recording media such as magnetic tape or optical
`disks, andis also useful in transmission systems such
`as those used for video teleconferencing, video tele-
`phones, television broadcasting (including direct sat-
`ellite broadcast), and the like. For example,
`it has
`been proposed by the Moving Picture Experts Group
`(MPEG) to compression-code moving picture video
`data utilizing motion-compensated prediction, trans-
`form processing using an orthogonal transformation
`suchasthe discrete cosine transform (DCT), and va-
`riable-length coding. A system for decoding and re-
`producing such compression-codedvideo dataisillu-
`strated in block diagram form in Figure 14 of the ac-
`companying drawings.
`As shownin Figure 14, a sequence of compres-
`sion-codedvideo data is provided at an input terminal
`101 for processing, in turn, by an inverse VLC (vari-
`able-length coding) circuit 102, an inverse quantiza-
`tion circuit 103, and an inverse DCTcircuit 104. An
`addingcircuit 105 forms a reconstructed frame of vid-
`eo data on the basis of a difference signal provided
`from the inverse DCTcircuit 104 and predictive pic-
`ture data (reference data) provided from a motion
`compensation circuit 106. The resulting reconstruct-
`ed video data is stored in a frame memory 107.
`The motion compensation circuit 106 forms the
`predictive picture data from reconstructed data pre-
`viously stored in frame 107 on the basis of motion
`compensation information (including, for example,
`motion vectors) extracted from the input signal and
`supplied to the motion compensation circuit 106 by
`the inverse VLC circuit 102. Alternatively, with re-
`spect to frames for which predictive coding was not
`performed, such as “intra-frame" coded data, the mo-
`tion compensation circuit 106 simply provides the val-
`ue "0" to the adder 105. Reconstructed framesofvid-
`
`eo data are output from the frame memory 107 viaa
`digital-to-analog converter 108 for display by a dis-
`play device 109.
`As the number of pixels in each frameof the video
`signal has increased from, for example, the 352 x 240
`frame used for video telephones to the 720 x 480
`frame used in the NTSC format or the 1920 x 1024
`
`frame in a HDTV (high definition television) system,
`it was found to be difficult to perform the necessary
`processing using only one processor and one pro-
`gram execution sequence. For this reason,
`it has
`been proposed to divide each frame of the video data
`into a plurality of subframes, asillustrated in Figure
`
`16 of the accompanying drawings, and then to provide
`arespective processorfor eachofthe plurality of sub-
`frames, so that coding and decoding are performed
`with parallel processing by the plurality of processors.
`For example, Figure 15 of the accompanying draw-
`ings is a block diagram of a decoding system provided
`in accordancewith this proposal.
`In the system of Figure 15, input sequencesof en-
`coded video data, each representing a respective
`subframe, are respectively provided via input termi-
`nals 110-113 to processors (decoderblocks) 114-117.
`The processors 114-117 decode the respective data
`sequences based upon data supplied from frame
`memories 119-122, which store respective sub-
`frames and are assigned to respective ones of the
`processors 114-117. For example, processor 114
`stores a subframe of decoded data in the memory
`119.
`In order to provide motion compensation, a
`switching logic circuit 118 provided between the proc-
`essors 114-177 and the frame memories 119-122,
`permits the processor 114 to read out data from an
`adjacentportion of the frame memory 120 as well as
`from all of frame memory 119. The switching logiccir-
`cuit 118 also provides frames of output video data
`from the memories 119-120, via a digital-to-analog
`converter 123 for display on a display device 124.
`The four data sequencesrespectively provided to
`the processors 114-117 can, for practical purposes,
`be combinedinto a single data sequence byproviding
`headers for controlling multiplexing of the data se-
`quence. For this purpose, a separation block (not
`shown) is provided upstream from the decoder for
`separating the combined data sequenceinto the four
`sequencesto be provided to the respective proces-
`sors. Examples of parallel processing techniques
`which use division of a video frame into subframes
`
`are disclosed in U.S. Patent No. 5,138,447 and Jap-
`anese
`Patent Application
`Laid Open
`No.
`139986/1992 (Tokkaihei 4-139986).
`Asjust described, according to the conventional
`approach, the video frame was generally divided into
`subframes which were processedin parallel by re-
`spective processors. However, when a frameis div-
`ided in this manner, there are restrictions on the ex-
`tent to which the processors can accessdata thatis
`outside of the processor’s respective subframe. Al-
`though, as indicated above, a processor can access
`a region that adjoins its respective subframe, the ex-
`tent of such accessis limited in order to keep the scale
`of the switching logic circuit 118 from becoming undu-
`ly large. As a result, the degree of compression effi-
`ciencyis reduced, and there are variations in the qual-
`ity of the reproducedpicture at the boundary between
`the subframes, which mayresult in visible artifacts at
`the subframe boundary.
`In addition, the processing for compression-cod-
`ing is carried out completely separately for each of the
`subframes, which makes it
`impossible to provide
`
`10
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`25
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`30
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`40
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`50
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`

`

`3
`
`EP 0 614 317 A2
`
`4
`
`compression-coding on the basis of data blocks in
`other subframes, a limitation that is not present when
`the frame is not divided into subframes. Accordingly,
`the compression coding method must be changed to
`accommodate the division into subframes, resulting
`in alack of compatibility and a loss in compression ef-
`ficiency.
`Furthermore, if header data is added to the data
`sequence to be recorded or transmitted in order to
`provide for multiplexing the data sequenceinto the re-
`spective sequencesprovided to the parallel proces-
`sors, the additional header data increases the over-
`head in the recorded data with a corresponding loss
`of efficiency, and it may also be necessary to change
`the coding procedure, and so forth.
`In accordancewith a first aspect of the presentin-
`vention, there is provided an apparatus for decoding
`a coded video signalthat represents an image frame,
`said coded video signal having been divided into a
`plurality of slices each of said slices being a sequence
`of macroblocks, each of said macroblocks being a
`two-dimensional array of picture elements of said im-
`age frame, said coded video signal being a bit stream
`that represents a sequenceof said slices whichto-
`gether representsaid image frame, said bit stream in-
`cluding a plurality of synchronizing code signals, each
`of which is associated with a respective one of said
`slices for indicating a beginning of the respective
`slice, the apparatus comprising:
`a plurality of decoding means each for decod-
`ing a respective portion of said coded video signal
`that represents said image frame; and
`distributing means responsive to said syn-
`chronizing code signals for distributing said slices
`among said plurality of decoding means.
`According to a second aspect of the invention,
`there is provided an apparatus for decoding inputsig-
`nal blocks that were formed by transform encoding
`and then variable-length encoding blocks of video
`data, the apparatus comprising:
`decoding means for variable-length decoding
`a series of said input signal blocks;
`parallel data means for forming plural parallel
`data streams, each of whichincludes respective ones
`of said series of input signal blocks which were vari-
`able-length decoded by said decoding means; and
`a plurality of inverse transform means eachfor
`receiving a respective one of said parallel data
`streams and for performing inverse transform proc-
`essing on the variable-length decoded signal blocks
`in the respective data stream.
`In preferred embodiments of the apparatus just
`described, the decodingcircuit is one of a plurality of
`decoding circuits for variable-length decoding re-
`spective series of input signal blocks, and the appa-
`ratus further includes a distributing circuit for forming
`the respective series of input signal blocks to be de-
`coded by the plural decoding circuits from a bit
`
`10
`
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`
`20
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`25
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`40
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`45
`
`50
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`55
`
`stream representing an image frame, and the respec-
`tive series of input signal blocks are formed in re-
`sponseto synchronizing signals provided at predeter-
`mined intervals in the bit stream representing the im-
`age frame.
`According to a third aspectof the invention, there
`is provided an an apparatus for decoding an inputdig-
`ital video signal which includes groups of blocks of
`prediction-coded differencedata, each of said groups
`consisting of a predeterminedplurality of said blocks
`and having a respective motion vector associated
`therewith, each of said blocks of prediction-codeddif-
`ference data having been formed on the basis of the
`respective motion vector associated with the respec-
`tive group which includes said block, the apparatus
`comprising:
`output meansfor supplying in parallel blocks of
`prediction-coded difference data contained in one of
`said groups of blocks;
`reference data meansfor supplying in parallel
`plural blocks of reference data, each of said blocks of
`reference data being formed on the basis of the mo-
`tion vector associated with said one of said groups of
`blocks and corresponding to oneof said blocksofpre-
`diction-coded difference data supplied by said output
`means; and
`a plurality of adding means each connectedto
`said output meansand said reference data meansfor
`adding a respective one of said blocks of prediction-
`coded difference data and the corresponding block of
`reference data.
`
`In preferred embodiments of the invention, the
`reference data circuit includes a plurality of reference
`data memories from whichreference data is read out
`
`in parallel on the basis of the motion vector associat-
`ed with that group of blocks, a plurality of buffer mem-
`ories for temporarily storing reference data read out
`from the plurality of reference data memories and a
`distribution circuit. According to one alternative em-
`bodiment of this aspect of the invention, each of the
`buffer memories is associated with a respective one
`of the reference data memories and is controlled on
`
`the basis of the motion vector for reading out the ref-
`erence data temporarily stored therein, and the dis-
`tributing circuit
`is connected between the buffer
`memories and the adding circuits and distributes the
`reference data stored in the buffer memories among
`the adding circuits on the basis of the motion vector.
`According to anotheralternative embodimentof this
`aspectof the invention, each of the buffer memories
`is associated with one of the adding circuits and the
`distributing circuit is connected between the refer-
`ence data memories and the buffer memories for dis-
`
`tributing among the buffer memories, on the basis of
`the motion vector associated with that group of
`blocks, the reference data read out from the reference
`data memories.
`
`According to a fourth aspect of the invention,
`
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`there is provided a method of decoding a coded video
`signal that represents an image frame, said coded
`video signal having been divided into a plurality of
`slices each of said slices being a sequence of macro-
`blocks, each of said macroblocks being a two-dimen-
`sional array of picture elements of said image frame,
`said coded video signal being a bit stream that repre-
`sents a sequenceofsaid slices which together repre-
`sent said image frame, said bit stream including a
`plurality of synchronizing code signals, each of which
`is associated with a respective one of said slices for
`indicating a beginning of the respective slice, the
`method comprising the stepsof:
`providing a plurality of decoding means each
`for decoding a respective portion of said coded signal
`that represents said video frame; and
`distributing said slices among said plurality of
`decoding means in response to said synchronizing
`code signals.
`The data representing each macroblock may be
`distributed block-by-block among the plurality of
`memories or line-by-line in a cyclical fashion among
`the plurality of memories.
`A video signal decoding apparatus may be pro-
`vided in which the input coded signalis distributed for
`parallel processing among several decodingcircuits
`on the basis of synchronizing code signals that are
`provided in the signal in accordance with a conven-
`tional coding standard. In this way, parallel decoding
`can be precisely carried out on the basis of synchron-
`izing signals provided in accordance with a conven-
`tional coding method and during time periods avail-
`able between the synchronizing signals. In this way,
`restrictions on the conventional coding method can
`be reduced.
`
`In addition, the data may be sequenced on the
`basis of "slices" which are a standard subdivision of
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`a video frame constituting a plurality of macroblocks
`and theslices of data are distributed among decoding
`circuits so that high speed parallel decoding may be
`carried out.
`
`Further, each of the blocks making up a macro-
`block may be distributed to a respective inverse
`transformation circuit so that inverse transform proc-
`essing can be carried out simultaneously in parallel
`for all of the blocks of a macroblock, and the inverse
`transform blocks are then combined, in parallel, with
`reference data to recover the video signal which had
`been predictive-coded. The reference data, in turn,
`may be provided from parallel memories at the same
`time on the basis of the motion compensation vector
`for the particular macroblock, and in such a waythat
`there is no needto place restrictions on the motion-
`compensation carried out during the predictive cod-
`ing. For example, there is no needto limit the range
`of the motion vector.
`Embodiments of the invention will now be descri-
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`bed, by way of example only, with reference to the ac-
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`companying drawings, in which:
`Figure 1 is a block diagram of an embodiment of
`an apparatus for decoding a moving picture video
`data signal;
`Figure 2 is a schematicillustration of a manner in
`which video data corresponding to an image
`frameis distributed for decoding;
`Figure 3 is a timing diagram whichillustrates op-
`eration of a buffer memory provided in the appa-
`ratus of Figure 1;
`Figure 4 is a block diagram whichillustrates a
`code buffering arrangement provided upstream
`from variable-length decodercircuits provided in
`the apparatus of Figure 1;
`Figure 5 is a timing diagram whichillustrates op-
`eration of the code buffering arrangement shown
`in Figure 4;
`Figure 6 is a block diagram which showsan alter-
`native code buffering arrangement provided up-
`stream from variable-length decodercircuits pro-
`vided in the apparatus of Figure 1;
`Figure 7 is a timing diagram whichillustrates op-
`eration of the code buffering arrangement shown
`in Figure 6;
`Figures 8(A), 8(B) and 8(C) together schematical-
`ly illustrate a mannerin which reference data is
`provided on the basis of a motion vector to adders
`that are part of the apparatus of Figure 1;
`Figure 9 is a timing diagram which illustrates an
`operation for providing reference data to the ad-
`ders which are part of the apparatus of Figure 1;
`Figure 10 is a block diagram of another embodi-
`mentof an apparatus for decoding a moving pic-
`ture video data signal;
`Figure 11(A), 11(B) and 11(C) together schemat-
`ically illustrate a mannerin which reference data
`is provided on the basis of a motion vectorto ad-
`ders that are part of the apparatus of Figure 10;
`Figures 12(A) and 12(B) together schematically
`illustrate an alternative manner in which refer-
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`ence data is provided on the basis of a motion
`vector to the adders which are part of the appa-
`ratus of Figure 10;
`Figure 13 is timing diagram whichillustrates an
`operation for providing reference data according
`to the example shownin Figure 12;
`Figure 14 is a block diagram of a conventional ap-
`paratus for decoding and reproducing a moving
`picture video data signal;
`Figure 15 is a block diagram of a portion of a con-
`ventional apparatus for decoding and reproduc-
`ing a movingpicture video data signal by means
`of parallel processing; and
`Figure 16 schematically illustrates operation of
`the conventional decoding apparatus of Figure
`15.
`
`Apreferred embodimentof the invention will now
`be described, initially with reference to Figure 1.
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`Figure 1 illustrates in block diagram form an ap-
`paratus for decoding a moving picture video data sig-
`nal that has been coded according to a proposed
`MPEG standard system.
`Aninput bit stream representing the coded video
`data signal
`is provided to a demultiplexer 25, by
`means of which the input signal is distributed, slice-
`by-slice, to code buffers 26-29.
`Figure 2 illustrates the slice-by-slice distribution
`of the input data. As is well known to those who are
`skilled in the art, each slice is a sequence of macro-
`blocks transmitted in raster scanning order. The start-
`ing point of each slice is indicated by a synchronizing
`codesignal, and the slices are provided sothat trans-
`mission errors and the like can be confined to a single
`slice, because after an error occurs, proper coding
`can resumeat the synchronizing code signal provided
`at the beginning of the subsequentslice. Accordingly,
`the demultiplexer 25 is provided with a circuit which
`detects the synchronizing code signals, and distribu-
`tion of the input signal among the code buffers 26-29
`is carried out in responseto the detected synchroniz-
`ing codesignals.
`Asis also well known, the motion vectors provid-
`ed with respect to each macroblock, and the DC coef-
`ficients for each block, are differentially encoded. In
`other words, only the difference between respective
`motion vectors for the current macroblock and the
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`shown as being one macroblock high and extending
`horizontally entirely across the image frame, so that
`eachslice consists of one row of macroblocks. How-
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`ever, it is also within the contemplation of this inven-
`tion to provide for slices having a fixed length in terms
`of macroblocksthatis longer or shorter than one row
`of macroblocks.
`It is further contemplated that the
`number of macroblocks per slice may be variable
`within each frame and/or from frame to frame and
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`that the positions of slices within a frame mayvary.
`In case variable-length slices are provided within a
`frame,it will be appreciated that the number of mac-
`roblocksdistributed to each of the variable-length de-
`coders maybe unbalanced, in which case someof the
`variable-length decoders may be required to output
`filler macroblocks (all zeros for example) until other
`decoders have "caught up". Furthermore, it is provid-
`ed that variable-length decoding of slices from the
`next image framewill not proceeduntil all of the slic-
`es of the current frame have been variable-length de-
`coded.
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`It will be recognized that any loss of decodingef-
`ficiency that results from the occasional needto in-
`terrupt the processing by someof the variable length
`decoders is compensated for by the fact that the cod-
`ing can be performed with slices that have a variable
`length in terms of macroblocks.
`Details of the variable-length decoding process-
`ing will now be described.
`preceding macroblock is encoded and transmitted,
`Data which has been decodedbythe respective
`and also, only the difference between the respective
`DC coefficient for the present block and that of the
`variable length decoders are transferred to buffer
`
`preceding block are coded and transmitted. memories 35-38 by way of switcher 34. Figure3illus-
`trates the mannerin which datais distributed to, and
`Asindicated in Figure 2, the first, fifth, ninth, etc.
`output from, the buffer memories 35-38. It will be not-
`slices of each image frame are storedin the first code
`buffer 26, and theseslices are provided for variable-
`ed that, upstream from the buffers 35-38, processing
`had been performedin a slice-wise parallel manner,
`length decoding by a variable-length decodercircuit
`30. Similarly, the second, sixth, tenth, etc. slices of
`but downstream from the buffers 35-38 processing is
`performed in a block-wise parallel manner. In partic-
`the image frameare stored in the second code buffer
`27 for variable-length decoding by variable-length de-
`ular, the four blocks of luminance data making up a
`codercircuit 31; the third, seventh, eleventh, etc.slic-
`macroblock are output in parallel from respective
`es are stored in the third code buffer 28 for variable-
`ones of the buffer memories 35-38. (It will be under-
`stood that a macroblock also includes chrominance
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`length decoding by the variable-length decoder circuit
`32; and the fourth, eighth, twelfth, etc. slices are stor-
`ed in the fourth code buffer 29 for variable-length de-
`coding by the variable-length decodercircuit 33.
`According to the example shownin Figure 2, the
`numberof macroblocksin eachslice is fixed, so that
`it will not be necessary for any of the variable-length
`decodersto wait. As result, decoding carried on by the
`variable-length decodersis synchronized and is car-
`ried out efficiently.
`It will be understood that, although the numberof
`macroblocks per slice is fixed, the numberof bits per
`slice in the input signal will vary because of variable-
`length encoding. Nevertheless, the number of macro-
`blocksperslice output by each variable-length decod-
`ing circuit is the same according to this example.
`In the example shown in Figure 2, eachslice is
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`blocks. For example, in the 4:2:2 format, each mac-
`roblock includes four blocks of chrominance data in
`addition to the four blocks of luminance data. The dis-
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`cussion from this point forward will deal only with the
`luminance data blocks, it being understood that the
`corresponding four chrominance data blocks can be
`processed in a similar manner.)
`Referring again to Figure3, it will be seen that the
`variable length decoders 30-33 respectively output
`simultaneously the respective first block of the first
`through fourth slices. The respective first blocks are
`distributed among the buffer memories 35-38 so that
`the first block of the first slice (i.e., the first block of
`the first macroblock of the first slice) is stored in the
`first buffer memory 35, the second blockof the first
`slice is stored in the second buffer memory 36. the
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`third block of the first slice is distributed to the third
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`buffer memory 37, and the fourth block of the first
`slice is distributed to the fourth buffer memory 38. As
`a result, all four blocks of a single macroblock can be
`read outin parallel by the respective buffer memories
`35-38, so that block-wise parallel processing can be
`accomplished downstream. Such processing _in-
`cludes conventional inverse transform processing in
`accordancewith zig-zag scanning.
`In the example just discussed, each buffer mem-
`ory preferably has two banks which each havethe ca-
`pacity of storing four data blo