(12) United States Patent
`Helms
`
`USOO67.48545B1
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,748,545 B1
`Jun. 8, 2004
`
`(54) SYSTEM AND METHOD FOR SELECTING
`BETWEEN A VOLTAGE SPECIFIED BY A
`PROCESSOR AND AN ALTERNATE
`VOLTAGE TO BE SUPPLIED TO THE
`PROCESSOR
`
`(75) Inventor: Frank P. Helms, Round Rock, TX
`(US)
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 582 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/621,931
`(22) Filed:
`Jul. 24, 2000
`
`(51) Int. Cl. .................................................. G06F 1/26
`
`(52) U.S. Cl. ....................................................... 713/300
`(58) Field of Search ................................. 713/300, 320,
`713/340
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,086,501 A 2/1992 DeLuca et al.
`... 713/320
`5,142,684. A * 8/1992 Perry et al. ...
`5,534,771. A
`7/1996 Massie ....................... 323/285
`5,659,789 A 8/1997 Hausauer et al.
`5,715,467 A * 2/1998 Jirgal ......................... 713/340
`5,737,616 A * 4/1998 Watanabe .....
`... 713/340
`5,761,479 A * 6/1998 Huang et al. ............... 710/301
`5,821,924. A 10/1998 Kikinis et al.
`5.835,780 A * 11/1998 Osaki et al. ................ 713/300
`6,031,742 A
`2/2000 Journeau ..................... 363/60
`6,282,662 B1 * 8/2001 Zeller et al. ......
`... 713/300
`6,448,672 B1 * 9/2002 Voegeli et al. ................ 307/52
`6,526,507 B1 * 2/2003 Cromer et al. .............. 713/162
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`O5108.193 A * 4/1993 ............. GO6F/1/04
`
`OTHER PUBLICATIONS
`IBM, DC/DC Converter Output Voltage Control by Suspend
`Signal, Oct. 1, 1995, vol. 38, pp. 181-182.*
`
`International Search Report Application No. PCT/US
`01/14907, mailed Aug. 29, 2002.
`
`* cited by examiner
`
`Primary Examiner Thomas Lee
`Assistant Examiner Mark Connolly
`(74) Attorney, Agent, or Firm Meyertons Hood Kivlin
`Kowert & Goetzel, P.C.; B. Noél Kivlin
`(57)
`ABSTRACT
`
`Disclosed herein are a method and apparatus to provide a
`deterministic power-on voltage in a System having a
`processor-controlled Voltage level. In one embodiment, the
`System includes a DC/DC converter, a processor, and a
`selection circuit. The DC/DC converter receives a voltage
`Setting Signal or Signals from the Selection circuit and
`provides an adjustable power output signal having a Voltage
`indicated by the Voltage Setting Signal. The processor is
`powered by the adjustable power output signal. When
`powered, the processor provides a programmable Voltage
`Setting Signal or Signals. The Selection circuit receives the
`programmable Voltage Setting Signal or Signals, a hardwired
`Voltage Setting Signal, and a Selection Signal or signals, and
`when the Selection Signal is in a predetermined condition,
`the selection circuit provides the programmable voltage
`Setting Signal or signals from the processor to the DC/DC
`converter. Preferably, when the Selection signal is in a
`Second predetermined condition complementary to the first
`predetermined condition, the circuit provides the hardwired
`voltage setting signal to the DC/DC converter. The first and
`Second predetermined conditions of the Selection signal are
`preferably de-assertion and assertion, respectively. The
`Selection signal may be determined by a logic gate that
`combines a mode control signal and a power good Signal,
`and causes the Selection signal to Select the Voltage Setting
`Signal from the processor only when the power good Signal
`is asserted and the mode control Signal is de-asserted. This
`advantageously allows for the processor to dictate its oper
`ating Voltage level, an ability that is extremely useful for
`power and thermal management in notebook PCs.
`
`17 Claims, 2 Drawing Sheets
`
`
`
`VID4:0
`SVIDI4:0
`
`SELECT SVID#
`
`CPUSTOPE IPWRGD
`
`AC ADAPTER OR
`BATTERYyOLTAGE
`
`
`
`DCIDC
`
`
`
`CPUVCC PROCESSOR
`
`PWRDNE
`
`Anker, EX1007, p. 1
`
`

`

`U.S. Patent
`
`Jun. 8, 2004
`
`Sheet 1 of 2
`
`US 6,748,545 B1
`
`
`
`OVID4:O
`SVID4:0
`
`
`
`
`
`MVID(4:0)
`
`CPUVCC PROCESSOR
`
`CPUSTOPE
`
`FIG. 1
`
`
`
`
`
`
`
`AC ADAPTER OR
`BATTERY VOLTAGE
`
`
`
`VID(4:0)
`SVID4:0
`
`
`
`MVID4:O
`
`SELECT SVID#
`
`
`
`PWRDNH
`
`PROCESSOR
`
`CPUSTOPE IPWRGD
`
`FIG. 2
`
`Anker, EX1007, p. 2
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`

`

`U.S. Patent
`
`Jun. 8, 2004
`
`Sheet 2 of 2
`
`US 6,748,545 B1
`
`+ 2 O Dr. > Ci
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`VDD3
`CPUSTOPH
`CPURST#
`PWRGD
`SVID(4:0)
`SVIDI40 AREVALID
`VID4:OAREVALID
`VID(4:0) -
`SELECTSVID#
`4:0
`MVS
`MVID4:O MV
`CPUVCC
`
`
`
`SVID40
`
`MVD40)-
`VID40)
`
`CLOCKS
`
`G.
`CLOCKSARERUNNIN
`
`FIG. 3
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`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
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`Anker, EX1007, p. 3
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`

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`US 6,748,545 B1
`
`1
`SYSTEMAND METHOD FOR SELECTING
`BETWEEN A VOLTAGE SPECIFIED BY A
`PROCESSOR AND AN ALTERNATE
`VOLTAGE TO BE SUPPLIED TO THE
`PROCESSOR
`
`2
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`FIG. 1 is a functional block diagram of a System having
`hardwired Voltage Settings,
`FIG. 2 is a functional block diagram of a System having
`processor-controlled Voltage Settings, and
`FIG. 3 is a timing diagram showing the operation of the
`deterministic power-on method.
`While the invention is susceptible to various modifica
`tions and alternative forms, specific embodiments thereof
`are shown by way of example in the drawings and will
`herein be described in detail. It should be understood,
`however, that the drawings and detailed description thereto
`are not intended to limit the invention to the particular form
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents and alternatives falling within the
`Spirit and Scope of the present invention as defined by the
`appended claims.
`Certain terms used throughout this disclosure are hereby
`defined. The term “signal' is intended to refer to a value
`conveyed via electrical impulses or electromagnetic waves
`on one or more conductive wires or other Suitable transport
`media. Hence the word Signal may be used to refer to a
`binary value conveyed by transmitting the representative bit
`values in parallel acroSS multiple conductors. It may also be
`used to refer to an analog value conveyed by a proportional
`Voltage on a Single wire. It is to be understood that there are
`many ways to convey a value between components, and the
`use of the Singular term “signal” in a claim does not limit the
`scope of the claim. The terms “asserted” and “de-asserted”
`are intended to refer to complementary conditions of a
`two-state signal. They are not necessarily respectively lim
`ited to digital logic “high” and “low” voltages. It is to be
`understood that the System designer can individually decide
`for each Signal which digital logic States will represent the
`assertion and de-assertion of that Signal. Such design con
`siderations do not limit the Scope of the invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`Turning now to the figures, FIG. 1 shows a processor
`receiving a power supply voltage signal (CPUVCC) from a
`programmable voltage converter (DC/DC). The converter
`receives power (in this case +5V) and a voltage setting
`Signal (MVID), and provides a regulated output voltage at
`the level indicated by the Voltage Setting Signal. Because it
`is desirable to provide the System with a power-Saving mode
`in addition to the normal operating mode, the Voltage Setting
`signal has two possible values: SVID for “sleep” mode and
`OVID for “operating” mode. A multiplexer (VID MUX)
`Selects between these two Voltage Settings in response to a
`mode control signal (CPUSTOPH) which may be provided
`from the South bridge. In this embodiment, the OVID and
`SVID are hardwired, i.e. Set by resistors, fuses, jumpers, or
`Some other non-volatile mechanical means.
`It is noted that computer Systems typically have multiple
`buses with devices called “bridges' that allow communica
`tions between components on different buses. It is also noted
`that computer Systems typically have Support circuitry that
`perform administrative functions Such as interrupt manage
`ment (the interrupt controller), clock/calendar/timer func
`tions (the clock), configuration management, power Supply
`control, and power-on signal Sequencing. This Support cir
`cuitry has commonly been placed in the bridge from the PCI
`bus to the peripherals and lower bandwidth busses, i.e. the
`“south bridge'.
`
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`BACKGROUND OF THE INVENTION
`The present invention generally relates to a method for
`Setting an initial power Supply Voltage in a System having a
`programmable power Supply Voltage.
`It has recently been regarded as desirable to dynamically
`adjust the power Supply Voltage and clock frequency of
`computer System processors to minimize power consump
`15
`tion and regulate heating of the processor core. The com
`puter System processors themselves would seem to be an
`ideal mechanism for controlling these adjustments but for
`the fact that they must first receive the power and clock
`before they can determine the appropriate Settings.
`Until the processor is Supplied with a minimum power-up
`Voltage, it is not capable of driving the Voltage identification
`outputs to control its operating Voltage. Therefore it is
`necessary for the System hardware to ensure the processor is
`Supplied with the required power-up Voltage and to prevent
`the DC/DC converter from responding to the processor's
`Voltage identification outputs until the processor is driving
`them to Select the Startup Voltage. To avoid damaging the
`processor, it is necessary to ensure that as the System is
`powered on, indeterminate Signals from the processor do not
`cause the power Supply Voltage level to exceed the proces
`Sors maximum operating limits.
`SUMMARY OF THE INVENTION
`The above issues are Solved by a method and apparatus to
`provide a deterministic power-on voltage in a System having
`a processor-controlled Voltage level. In one embodiment, the
`System includes a DC/DC power converter, a processor, and
`a selection circuit. The DC/DC converter receives a voltage
`Setting Signal from the Selection circuit and provides an
`adjustable power output signal having a Voltage indicated by
`the Voltage Setting Signal. The processor is powered by the
`adjustable power output Signal. When powered, the proces
`Sor provides a programmable Voltage Setting Signal. The
`Selection circuit receives the programmable Voltage Setting
`Signal, a hardwired Voltage Setting Signal, and a Selection
`Signal, and when the Selection signal is in a predetermined
`condition, the Selection circuit provides the programmable
`Voltage Setting Signal from the processor to the DC/DC
`converter. Preferably, when the Selection signal is in a
`Second predetermined condition complementary to the first
`predetermined condition, the circuit provides the hardwired
`voltage setting signal to the DC/DC converter. The first and
`Second predetermined conditions of the Selection signal are
`preferably de-assertion and assertion, respectively. The
`Selection signal may be determined by a logic gate that
`combines a mode control signal and a power good Signal,
`and causes the Selection signal to Select the Voltage Setting
`Signal from the processor only when the power good Signal
`is asserted and the mode control Signal is de-asserted. This
`advantageously allows for the processor to dictate its oper
`ating Voltage level, an ability that is extremely useful for
`power and thermal management in notebook PCs.
`BRIEF DESCRIPTION OF THE DRAWINGS
`A better understanding of the present invention can be
`obtained when the following detailed description of the
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`Anker, EX1007, p. 4
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`

`

`3
`Consequently, one of skill in the art will recognize that the
`South bridge may be configured to monitor the activity level
`of the computer System, and to place the computer System
`into a “sleep” mode if it is determined that the computer
`System has been inactive for a predetermined length of time.
`In the embodiment of FIG. 1, the assertion of the mode
`control Signal causes the power Supply Voltage to be lowered
`to the hardwired sleep setting. In systems having APM
`(Advanced Power Mangaement), if the south bridge later
`detects activity, (e.g. a key press or motion of a pointing
`device), the South bridge can deassert the mode control
`Signal to raise the power Supply Voltage to the hardwired
`“operating Setting. In Systems having ACPI, the operating
`System decides when to place the System into a sleep State,
`and calls device drivers to place the devices into a low power
`State and then manipulates a register in the South bridge to
`initiate the hardware Sequence into the sleep State.
`One example of a programmable Voltage converter is a
`MAXIM MAX1711 High-Speed, Digitally Adjusted Step
`Down Controller or its equivalent. The MAX1711 can
`transition between selected voltages in less than 100 us. The
`MAX1711 uses its D4 through D0 inputs to determine the
`output voltage level as follows:
`
`15
`
`D4:DO
`
`Output Voltage
`
`OOOOO
`OOOO
`OOO10
`OOO
`OO1OO
`OO1O
`OO110
`OO1
`O1OOO
`O1OO
`O1010
`O1O
`O1100
`O110
`O1110
`O11
`OOOO
`OOO
`OO10
`OO
`O1OO
`O1O
`O110
`O1
`1OOO
`1OO
`1010
`1O
`11OO
`110
`1110
`11
`
`2.OO
`95
`.90
`85
`8O
`.75
`70
`65
`60
`55
`50
`45
`.40
`35
`3O
`Shutdown
`275
`250
`225
`2OO
`175
`150
`125
`1OO
`O75
`OSO
`O25
`OOO
`0.975
`O.950
`0.925
`Shutdown
`
`See the MAXIM Data sheet for more information on Shut
`down.
`It is desirable to provide processors Such as upcoming
`versions of AMD's K6-III and Athlon processors with
`voltage identification (VID) output signals that they will
`drive to the DC/DC converter that supplies their operating
`Voltage. These, in addition to adjustable core frequencies,
`will allow for maximum Notebook PC performance in any
`thermal environment, and will also allow the user to deter
`mine the tradeoff between performance and battery life.
`The processors will preferably be provided with a register
`that contains the current Voltage Setting. When the processor
`is reset, the Voltage Setting is initialized to Some “Safe”
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`US 6,748,545 B1
`
`4
`Voltage Such as, e.g. 1.5 V, and during the assertion of the
`reset Signal, the Setting Signals are driven to the processor
`output pins. When desired, the Voltage Setting Signals are
`changed by writing to this register.
`When the system would be first powered on, the processor
`would not be powered, and would therefore not be capable
`of driving its VID outputs until its voltage becomes stable at
`an operational level and its clock is running. Also, as power
`is applied to the processor, the State to which it would drive
`its VID outputs could not be guaranteed until the Voltage is
`within its specified limits, reset is asserted, and the clock to
`the processor is running and Stable. Additionally, Some
`processors require a power good Signal to be asserted to the
`processor before the processor drives its startup VID. How
`ever Since outputs of the processor are used to dictate to the
`DC/DC converter what voltage level should be driven to the
`processor, it cannot be known what Voltage will be driven to
`the processor when the System is first powered on. The
`possibility exists that the DC/DC converter could drive a
`Voltage So low that the processor would not be able to
`operate enough to drive its VID outputs to select the
`intended power up Voltage. If this Scenario occurred the
`system would he “hung” in a state that it could not exit from.
`Another possibility is that the DC/DC could drive a voltage
`level that is higher than the maximum allowed Voltage for
`the processor. Either of these Scenarios could damage the
`CPU after some period of time.
`FIG. 2 shows a configuration that solves this problem by
`ensuring that the processor is always Supplied with a voltage
`at which it will be operational when the system is powered
`on. In this embodiment, the Sleep Voltage Setting Signals
`SVID are still hardwired, but the operating voltage setting
`Signals are provided by the processor. A Selection signal
`(SELECT SVID#) is provided to the multiplexer to select
`the appropriate multiplexer input. A logic circuit is used to
`produce this Selection Signal. When the Selection signal is
`asserted, the multiplexer Selects the hardwired Voltage Set
`ting Signals, whereas when the Selection Signal is
`de-asserted, the multiplexer Selects the Voltage Setting Sig
`nals from the processor.
`The logic circuit is preferably designed to assert the
`Selection signal during the initial power-up Sequence and
`whenever the computer System goes into the sleep mode.
`Accordingly, the logic circuit operates on the mode control
`signal (CPUSTOP#) and the power-good signal (PWRGD).
`Only if the mode control Signal is asserted to indicate Sleep
`mode or if the power-good Signal is de-asserted does the
`logic circuit assert the Selection signal. Otherwise the Selec
`tion Signal is de-asserted.
`Persons of skill in the art are familiar with the power-good
`Signal. When power is initially applied to a computer
`System, this signal is held in a de-asserted State until all of
`the Voltage rails in the System are stable within Specified
`limits. At that time, the power-good Signal is asserted and
`maintained until the system is powered down. The PWRGD
`signal of FIG. 2 is deasserted so that SVID4:0 drives the
`DC/DC until CPUVCC is at a level where the processor can
`deterministically drive the VID signals. It will be the respon
`sibility of the BIOS or system software to set the VID
`signals early in the POST routine to transition the processor
`core Voltage to the desired performance level.
`As a quick aside, it is noted that the DC/DC converter of
`FIG. 2 may receive a power down (PWRDN#) signal.
`PWRDN# is a control input that when asserted causes the
`DC/DC to shut off its outputs, and enter a low power state.
`FIG.3 illustrates the operation of the deterministic power
`on circuit by showing a Sequence of Signal transitions after
`
`Anker, EX1007, p. 5
`
`

`

`US 6,748,545 B1
`
`15
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`S
`an exemplary computer System is turned on. When the user
`presses the power Switch, the power on (PWRON#) signal
`is asserted, and the power down (PWRDN#) signal is
`de-asserted. After the power rails for the System are within
`specified limits, the power good (PWRGD) signal is
`asserted.
`As the Sleep Voltage Setting (SVID) signals are hardwired,
`they are always fixed at their predetermined values.
`Conversely, the operating voltage setting (VID) signals are
`not driven to their programmed values until the processor
`has been powered. Preferably, these signals reach their
`programmed values before assertion of the System power
`good Signal. However, the VID Signals can be driven to
`Select the operating Voltage as the power good Signal is
`asserted. The selection signal (SELECT SVID#) is prefer
`ably de-asserted only after the power good Signal is asserted,
`causing the multiplexed voltage setting (MVID) signal to
`equal the sleep Voltage Setting Signals until the power good
`Signal is asserted. The de-assertion of the Selection signal
`then causes the multiplexed Voltage Setting Signal to equal
`the operating Voltage Setting Signals provided by the pro
`cessor. Preferably, the allowed transition time from the
`power up Voltage Selected by SVID to the operating Voltage
`selected by the CPU VID outputs is 100 microseconds.
`Consequently, the processor voltage (CPUVCC) signal is
`deterministically controlled. Before the power good Signal is
`asserted, the processor is powered at the Sleep Voltage
`Setting. This is Sufficient to let the processor drive the
`programmed operating Voltage Setting Signals. After the
`power good Signal is asserted, the processor is powered at its
`programmed operating Voltage Setting. The clock signals are
`operating before the power good signal is asserted, So that
`the processor can propagate the reset Signal and drive the
`startup VID when the CPU PWROK signal (may be the
`System power good Signal) is asserted. At approximately 1.8
`milliseconds after the power good Signal is asserted, the
`processor reset Signal is de-asserted, allowing the processor
`to be fetching code from the address for its reset vector.
`Changes to the Startup voltage and frequency Setting can
`later be made by System Software. In an exemplary System,
`the following StepS will be taken to carry out a change to the
`Voltage Settings.
`1) A software driver is called to transition the CPU voltage
`and frequency.
`2) For K6 systems, the SMM handler sets the advanced
`configuration and power interface (ACPI-) defined
`arbitration disable (ARB DIS) bit in the north bridge
`to prevent System bus masters from being granted the
`buS and access to System memory while the transition
`is taking place. This is required for K6 because the
`processor is not capable of responding to cache Snoops
`while its core Voltage and/or frequency are being
`transitioned.
`3) The SMM handler verifies that all system bus activity
`has ceased before initiating the transition. This is
`required because there could be a bus master cycle in
`progress when the ARB DIS bit is asserted, and this
`transaction will have to complete before the System bus
`master relinquishes control of the System bus. The
`SMM handler can determine that no system bus master
`has control of the System bus by reading a register in
`the South bridge. This read cannot complete until any
`System bus master that has control relinquishes own
`ership of the System buS.
`4) The SMM handler writes to registers in the processor
`to Specify the new Voltage and frequency that the
`processor should operate at and then writes a register to
`initiate the transition to the new Voltage and frequency.
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`6
`5) The SMM handler clears the ARB DIS bit in the north
`bridge to allow System bus masters access to System
`memory.
`6) The SMM handler executes a resume (RSM) instruc
`tion to return the processor to normal operation.
`It is noted that SMM is only required for K6. For K7, the
`ARB DIS bit is not used for voltage and frequency tran
`sitions and neither is SMM mode.
`Numerous variations and modifications will become
`apparent to those skilled in the art once the above disclosure
`is fully appreciated. AS an example, it is noted that it is not
`necessary to drive all of the VID4:0 outputs of processor
`to the voltage select inputs of the DC/DC converter. The
`voltage select inputs of the DC/DC that are not driven by the
`processor VID outputs can be Strapped high or low on the
`motherboard with a resistor.
`Further, it is not necessary to use a multiplexer, as other
`logic can achieve the same functionality. It is even possible
`that at Some point, the DC/DC converter will incorporate the
`multiplexer functionality So that a separate logic circuit will
`be unnecessary.
`Additionally, when using DC/DC converters that rely on
`a “feedback Voltage” rather than a digital look-up table, the
`Voltage Setting inputs may be applied to change an imped
`ance value of a Voltage divider network to vary the feedback
`Voltage and thereby Set the desired output Voltage. It is
`intended that the following claims be interpreted to embrace
`all Such variations and modifications.
`What is claimed is:
`1. A computer System that comprises:
`a DC/DC converter configured to provide an adjustable
`output voltage;
`a processor powered by the adjustable output Voltage of
`the DC/DC converter, wherein the processor provides
`one or more Voltage identification Signals, and
`a Selection circuit configured to receive the Voltage iden
`tification signals, an alternate Voltage Setting Signal,
`and a Selection signal, wherein the Selection circuit is
`configured to provide the Voltage identification signals
`or the alternate Voltage Setting Signal to control the
`output voltage of the DC/DC converter dependent upon
`a State of the Selection Signal.
`2. The computer System of claim 1, wherein the alternate
`Voltage Setting Signal is provided by the Selection circuit
`when the Selection signal is asserted and wherein the Voltage
`identification Signals are provided by the Selection circuit
`when the Selection signal is de-asserted.
`3. The computer System of claim 2, further comprising:
`a power Supply configured to provide power to the
`DC/DC converter when the system is powered-on,
`wherein the power Supply is further configured to
`provide a power good Signal which is de-asserted for a
`predetermined time after the System is powered-on.
`4. The computer system of claim 3, wherein the selection
`Signal is de-asserted only if the power good Signal is
`asserted.
`5. The computer system of claim 4, wherein the selection
`Signal is provided by a logic gate, and wherein the logic gate
`is configured to determine the Selection signal by combining
`the power good Signal with a mode control signal.
`6. A method for assuring an adjustable, deterministic
`Voltage is provided to a processor, wherein the method
`comprises:
`a circuit receiving at least one hardwired Voltage Setting
`Signal;
`the circuit receiving at least one adjustable Voltage Setting
`Signal from the processor,
`
`Anker, EX1007, p. 6
`
`

`

`US 6,748,545 B1
`
`7
`the circuit receiving a Selection signal that determines
`which of the hardwired Voltage Setting Signal and the
`adjustable Voltage Setting Signal is provided to a
`DC/DC converter;
`the DC/DC converter providing a Voltage to the processor,
`wherein the Voltage level is Set by the Voltage Setting
`Signals received from the circuit, and
`wherein the Voltage Setting Signal is Set to the hardwired
`Voltage Setting Signal when power is initially Supplied
`to the DC/DC converter.
`7. The method of claim 6, further comprising:
`using a power good Signal as the Selection Signal to
`prevent the circuit from providing the adjustable Volt
`age Setting Signal while the power good Signal is
`de-asserted.
`8. The method of claim 7, further comprising:
`using a mode control Signal as the Selection signal to
`prevent the circuit from Selecting the adjustable Voltage
`Setting Signal while the mode control Signal is asserted.
`9. The method of claim 8, wherein a logic gate sets the
`Selection Signal to Select the adjustable Voltage Setting Signal
`when the power good Signal is asserted and the mode control
`Signal is de-asserted.
`10. A system that comprises:
`a DC/DC converter that receives voltage selection inputs
`and provides an adjustable Voltage output level having
`a Voltage specified by the Voltage Selection inputs;
`a electrical component configured to receive the adjust
`able voltage output from the DC/DC converter, wherein
`the component provides Voltage Selection output; and
`a Selection circuit configured to receive the Voltage Selec
`tion outputs from the electrical component and a selec
`tion signal, wherein the Selection circuit drives the
`voltage selection inputs to the DC/DC converter to
`Select a first voltage level independent of the Voltage
`Selection output of the electrical component when the
`Selection Signal is in a first State and drives the Voltage
`selection inputs to the DC/DC converter to select a
`
`8
`Voltage level dictated by the Voltage Selection output of
`the electrical component when the Selection signal is in
`a Second State.
`11. The system of claim 10, wherein said selection circuit
`is further configured to receive a fixed voltage Setting Signal,
`and wherein the Selection circuit drives the Voltage Selection
`inputs in accordance with the fixed voltage Setting Signals
`when the Selection signal is in the first State.
`12. The system of claim 10, wherein the first state is
`assertion of the Selection signal.
`13. The system of claim 12, further comprising:
`a power Supply that provides various Voltages to the
`System, wherein the System provides a power good
`Signal which is de-asserted when the System is
`powered-on until all of the Voltage rails in the System
`are within Specified operating levels.
`14. The system of claim 13, wherein the selection signal
`is de-asserted only if the power good Signal is asserted.
`15. The system of claim 14, wherein the selection signal
`is provided by a logic gate, and wherein the logic gate is
`configured to determine the Selection signal by combining
`the power good Signal with a mode control signal.
`16. A System which comprises:
`a DC/DC converter having a feedback input that deter
`mines an output voltage of the DC/DC converter;
`a voltage divider coupled to the feedback input of the
`DC/DC converter and coupled to the output voltage of
`the DC/DC converter;
`a Selection circuit which controls the impedance of the
`voltage divider so that the DC/DC converter provides a
`deterministic first voltage dictated by a motherboard
`while a Select Signal is in a first State, and So that the
`DC/DC converter provides the output voltage selected
`by a processor when the Select signal is in a Second
`State.
`17. The system of claim 16, wherein the select signal is
`based on a power good Signal and a mode control Signal.
`
`1O
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`15
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`25
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`35
`
`k
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`k
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`k
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`k
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`k
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`Anker, EX1007, p. 7
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