`
`ISSCC99 / SESSION 4 / PAPER MP 4.2
`
`
`MP 4.2 A DECT Transceiver Chip Set Using
`SiGe Technology
`
`Matthias Bopp, Martin Alles, Meinolf Arens, Dirk Eichel, Stephan Gerlach,
`Rainer Gétztried, Frank Gruson, Michael Kocks, Gerald Krimmer.
`Reinhard Reimann, Bernd Roos, Martin Siegle, Jlirgen Zieschang
`
`TEMIC Semiconduclor GmbH,Heilbrorn, Germany
`
`A fully-integrated RF-transceiver for DECT comprises two bipolar
`ICs including power amplifier, low-noise amplifier and VCO. Non-
`blind-slot and multi-slot capability is achieved by closed-loop modu-
`lation. The complete transceiver, which operates from 2.7 to 5V,
`avoids mechanical tuning, and requires <50 external components.
`
`The complete RF transceiver, including VCO and synthesizer, is
`integrated on one chip. A second IC, implemented in SiGe-technol-
`ogy, includes a low-noise amplifier in the receive path as well asa
`power amplifier for the transmit path and a driver for an external
`PIN diode switch (Figure 4.2.1). High integration level ofboth ICsin
`TQFP48 and PSSOP16 packagesallows use ofa compact 2-layer PC
`board using cost-effective FR4 material and only one component
`side. Furthermore, the transceiver does not require any mechanical
`tuning in production by providing bus-controlled electronic tuning.
`It operates from 2.7 to 5V, avoiding negative supply voltage and
`supports simple power management by meansofintegrated regula-
`tors and multiple power-dewn modes. Also, the generation of the
`analog control signal for applied power ramping ofthe TDMA signal
`isintegrated.
`
`The transmit path starts with the fully-integrated FIR baseband
`filter. This Gaussianfilter shapes the digital data stream precisely
`to keep adjacent channel emissions low (Figure 4.2.5). The inte-
`grated VCO with on-chip inductors operates at double the frequency
`ofthe DECT bandaround 3.8GHz. Its approximately -132dBc phase
`noise 5MHzoffset meets the DECTspecification at this critical
`point. The narrow-bandspectrum is shownin Figure 4.2.2. This VCO
`is directly modulated by the Gaussian basebandsignalandis subse-
`quently divided by a factorof 2 to thefinal frequency band ofDECT.
`Thus feedback from PA-driver and PA to the VCO is minimized.
`
`Thereceiver is based on a single-conversion superheterodyne con-
`cept. Coming from the antenna input with a characteristic imped-
`ancc of5082 the received signal passes througha dielectrica]l bandpass
`filter. This preselector provides far-off selectivity and improves
`imagerejection, The following PIN diode switch implemented with
`a /4-transmission line combines low insertion loss and minimum
`current consumption in receive mode. Next, the signal is amplified
`in the LNA with 19dB gain and 1.7dB noise figure (Figure 4.2.7). No
`external matching circuitry is necessary and the high reverseisola-
`tion of~50dB reducesthelocaloscillator leakage to the antenna and
`simplifies PC board design. The LNA outputsignalis passed to the
`image-rejection mixer in the transceiver IC. The mixercells are
`double-balanced and the 90° phaseshift on the LO side is accom-
`plished inherently by dividing the VCO signal downby a factor oftwo
`using both master and slave outputs. The RC-CR phaseshifters at
`the IF side are fully integrated and the symmetrical! outputsignalis
`coupledto a fully-symmetrical SAWfilter (Figure 4.2.8). The mixer
`features 25dB imagerejection and converts the signal down to
`110MHzsingle IF, is chosen for availability of various low-cost
`filters. No second front-endfilter is needed to achieve 70dB overall
`imagerejection. The large-signal compatibility is given in Figure
`4,2.9, Next, the signal is passed to the IF amplifier and FM demodu-
`lator. The quadrature demodulatortankcircuit is tuned internally
`by an integrated varactorvia bus control. Finally the demodulated
`signal is baseband filtered, huffered and passed to the baseband
`processing IC. A received signal strength indicator (RSSI) signalis
`derived in the IF chain. The overall dynamic range of the RSSI
`measured at the IF input is approx. 90dB to guarantee 60dB mini-
`mum RSSI dynamic range of the complete receiver and allow the
`application of SAW-filters with insertion losses from 6 to 17dB as
`well as provide margin for production tolerances.
`
`Thetransceiverchip is fabricated in a bipolar process. The front-end
`IC is produced in SiGe! technology, including npn HBTs with and
`without selectively implanted collector on the same wafer. In addi-
`tion, spiral inductors, nitride capacitors, three typesofpoly resis-
`tors, a LPNP, RF- and DC-ESDprotection and varactor diodes are
`incorporated in the technology (‘Table 4.2.1). Phe SiGe HBTs have
`30GHz f, with 6V BVCEO and 50GHz f,with 3V BVCEO. The
`maximum f, and f,,, are at current densities of 0.8mA/zm? and
`0.65mA/pzm?for the non-SIC and the SIC devices, respectively. Due
`to the high base dopingthe early voltage is above 50V.
`
`Packaging technologies with the chipscale technology will reduce
`cost (Figure 4.2.10), Anotherpossible direction is a true one-chip RF
`transceiver including PA and LNAin a SiGe BiCMOStechnology.
`
`Acknowledgemenis:
`The authors thank the team in layout, technology (H. Dietrich, U.
`Seiler, A. Schiippen and D. Zerrweck) and application support.
`
`Closed-loop modulation avoids distortion of the transmitted data
`stream by PLL operation without opening the loop. The principle of
`this circuit is illustrated in Figure 4.2.3. The binary data stream of
`the transmit data from the baseband chip is distributed to an
`integrated Gaussian basebandfilter and to a modulation compensa-
`tion circuit, a digital integrator. It derives the digital sum variation
`(i.e., the law frequency content) of the digital data stream. The
`reference signal of the PLL phase detector is shifted by a phase
`shifter, which is controlled by the modulation compcnsation block.
`Thus the phasedetector ofthe PLL will not see any changeof phase
`ofits input signals and the PLLis not removing the modulation ofthe
`directly modulated VCO, hence workingstill in closed loop. Loop
`bandwidthis high enoughto allow PLLsettling times <25ysresult-
`References:
`(1) TEMIC Semiconductor, Datasheets:
`ing in a cost-effective non-blind-slot solution. The quality of the
`“DECYRF/IF IC U2761B,” Rev.A4, 10. March 1998.
`closed loop modulated signal can be seen in the demodulated trans-
`“DECT PLL/TX IC U2785B,” Rev.A4,13. Oct. 1998.
`mit signal eye diagram ofFigure 4.2.4. Even for long sequencesof1s
`“DECT SiGe Front End IC U7004B,” Rev.A5, 10. June 1998.
`[2] R. Gitzfried, F. Beisswanger, and S. Gerlach, “Design of RF Integrated
`and0s, the eye is open. Thus multislot operation is possible. Up to23
`Circuits Using SiGe Bipolar Technology,” IEEE J. Solid-State Circuits, vol.
`slots can be collocated for a highly asymmetrical datalink as desir-
`33, pp. 1417-1422, Sept. 1998.
`able in many data applications.
`18] A. Schiippen, H. Dietrich, S. Gerlach, H. Héhnemann, J. Arndt, U.Seiler,
`R. Gotzfried, U. Erben, and H. Schumacher, “SiGe-technology and Compo-
`nents for Mobile Communication Systems,” in Bipolar/BiCMOS Circuits
`Technol. Mecting, Minneapolis, MN,Sept. 1996, pp. 130-133.
`(4| J. Sevenhans,B. Verstraeten, G. Fletcher, H. Dietrich, W. Rabe, J. L. Bacq,
`J. Varin, and J. Dulongpont, “Silicon Germanium and Silicon Bipolar RF
`Circuits for 2.7V Single Chip Radio Transceiver Integration,” proceedings of
`IEKE 1998 CICC,p. 409 to 412.
`[5] J. Sevenhanset al., “An Analog Radio Front-end Chip Set for a 1.9GHz
`Mobile Radio Telephone Application,” proceedings of ISSCC1994,p. 44-45.
`
`Thetransceiver IC-modulated output signal speetrum at 1.9GHz
`without external filtering isshown in Figure 4.2.5. The 0dBn output
`level) is amplified to 26dBm by the SiGe power amplifier,The power
`amplifier has 33dB small-signal gain, 38% max PAE and 26.6dBm
`saturated output power at 3V supply (Figure 4.2.6). The signal
`passes the PIN-diode switch and the only dielectric RF bandpass
`filter of the system. At the antenna, the output level is 24dBm.
`
`
`
`68
`
`e 1999 IEEE International Solid-State Circuits Conference
`
`0-7803-5126-6/99 / $10.00 / © IEEE
`
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`SAMSUNG 1051
`SAMSUNG1051
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`IPR2022-01004
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`1
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`1
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`

`

`
`
`ISSCC99 / February 15, 1999 / Salon 8 / 2:00 PM
`
`
`
`
`iF
`
`DEMOD
`TANK
`TANK
`
`
`THIRX
`
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`crane an]
`CONTROL
`
`RF-transceiverschematic
`
`including SiGe front-end.
`
`REL
`vBD
`Sut
`
`1D kbe
`300 Hz
`84D ms
`
`PE Gh
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` Certer 1.9367B9581 G4z
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`100 Liz
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`Span t MHz
`
`Ret.
`Clock
`
`TX Data
`
`Pre Reference Phase Phase
`Charge
`
`Amp Counter Shifter Detector
`Pump
`
`
`
`[pbeebte
`Modulation
`Compensation
`
` Modulo
`Pre
`Swallow
`Prescaler
`Counter
`Amp
`
`
`
`TX Data Filter
`
`
`
`Figure 4.2.3:
`
`Closed loop modulation concept.
`
`
`
`
`
`
`Figure4.2.2;
`
`Integrated VCO phasenoise spectrum.
`
`
`
`
`
` Device Parameter SiGe] UHF5S
`
`npn
`min.emitter
`0.8x1.6 zm? 0.75x2.0um?
`np (non-SIC)
`£, (GHz)
`30
`15
`npn (SIC)f, (GHz)
`Lpnp
`Vpnp
`12L
`MIM capacitor
`Poly resistor
`Spiral inductor
`Diode
`ESD
`
`Hep
`f, (GHz)
`
`f,./ em?
`Qisq
`L/nH
`
`n.a. = not available
`
`50
`
`30
`
`10
`na.
`n.a.
`11
`4.5/110/400
`0.5...20
`varactor
`RF/DC
`
`40
`2
`available
`na.
`100/825
`0.5...20
`varactor
`DC
`
`Table 4.2.1:
`
`Technology overvicw.
`
`
`
`Figure 4.2.4:
`
`Closed-loop modulation eye pattern with
`modulation compensation circuit enabled
`and disabled.
`
`Figure 4.2.5, Figure 4.2.6, Figure 4.2.7, Figure 4.2.8,
`Figure 4.2.9, and Figure 4.2.10:
`See page 447.
`
`
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`ISSCC99 PAPER CONTINUATIONS
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`Figure 4.2.6:
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`Figure 4.2.7;
`
`LNASiGe frontend : Gain, NF vs.
`Frequency.
`
`Figure 4.2.8:
`
`IR-mixer schematic.
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`Input Power RF [dBm]
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`
`Figure 4.2.9: UR-mixer large-signal compatibility.
`
`Figure 4.2.10: SiGe frontend IC in chip scale package
`
`SSSeySerDasusarvySP S SSSISS
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