Super Sequencer™ with Margining Control
`and Auxiliary ADC Inputs
`ADM1066
`
`
`
`
`
`FUNCTIONAL BLOCK DIAGRAM
`
`AUX1
`
`AUX2
`
`REFIN
`
`REFOUT
`
`REFGND
`
`SDA SCL A1
`
`A0
`
`ADM1066
`
`VREF
`
`SMBus
`INTERFACE
`
`PDO1
`PDO2
`PDO3
`PDO4
`PDO5
`PDO6
`
`PDO7
`
`PDO8
`
`PDO9
`
`PDO10
`
`PDOGND
`
`VDDCAP
`
`
`
`04609-001
`
`EEPROM
`
`CONFIGURABLE
`OUTPUT
`DRIVERS
`
`(HV CAPABLE
`OF DRIVING
`GATES OF
`N-CHANNEL FET)
`
`CONFIGURABLE
`OUTPUT
`DRIVERS
`
`(LV CAPABLE
`OF DRIVING
`LOGIC SIGNALS)
`
`12-BIT
`SAR ADC
`
`MUX
`
`CLOSED-LOOP
`MARGINING SYSTEM
`
`DUAL-
`FUNCTION
`INPUTS
`(LOGIC INPUTS
`OR
`SFDs)
`
`PROGRAMMABLE
`RESET
`GENERATORS
`
`(SFDs)
`
`SEQUENCING
`ENGINE
`
`VOUT
`DAC
`
`VOUT
`DAC
`
`VOUT
`DAC
`
`VOUT
`DAC
`
`VOUT
`DAC
`
`VOUT
`DAC
`
`VDD
`ARBITRATOR
`
`DAC1
`
`DAC2
`
`DAC3
`
`DAC4
`
`DAC5
`DAC6
`Figure 1.
`
`VCCP
`
`GND
`
`VX1
`VX2
`VX3
`VX4
`VX5
`
`VP1
`VP2
`VP3
`VP4
`VH
`
`AGND
`
`APPLICATIONS
`Central office systems
`Servers/routers
`Multivoltage system line cards
`DSP/FPGA supply sequencing
`In-circuit testing of margined supplies
`
`GENERAL DESCRIPTION
`
`The ADM1066 is a configurable supervisory/sequencing device
`that offers a single-chip solution for supply monitoring and
`sequencing in multiple-supply systems. In addition to these
`functions, the ADM1066 integrates a 12-bit ADC and six 8-bit
`voltage output DACs. These circuits can be used to implement a
`closed-loop margining system that enables supply adjustment
`by altering either the feedback node or reference of a dc-to-dc
`converter using the DAC outputs.
`
`(continued on Page 4)
`
`
`
`
`FEATURES
`Complete supervisory and sequencing solution for up to
`10 supplies
`10 supply fault detectors enable supervision of supplies to
`<0.5% accuracy at all voltages at 25°C
`<1.0 % accuracy across all voltages and temperatures
`5 selectable input attenuators allow supervision
`Supplies up to 14.4 V on VH
`Supplies up to 6 V on VP1 to VP4
`5 dual-function inputs, VX1 to VX5
`High impedance input to supply fault detector with
`thresholds between 0.573 V and 1.375 V
`General-purpose logic input
`10 programmable output drivers, PDO1 to PDO10
`Open collector with external pull-up
`Push/pull output, driven to VDDCAP or VPn
`Open collector with weak pull-up to VDDCAP or VPn
`Internally charge-pumped high drive for use with external
`N-FET (PDO1 to PDO6 only)
`Sequencing engine (SE) implements state machine control of
`PDO outputs
`State changes conditional on input events
`Enables complex control of boards
`Power-up and power-down sequence control
`Fault event handling
`Interrupt generation on warnings
`Watchdog function can be integrated in SE
`Program software control of sequencing through SMBus
`Complete voltage-margining solution for 6 voltage rails
`6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
`adjustment via dc-to-dc converter trim/feedback node
`12-bit ADC for readback of all supervised voltages
`2 auxiliary (single-ended) ADC inputs
`Reference input (REFIN) has 2 input options
`Driven directly from 2.048 V (±0.25%) REFOUT pin
`More accurate external reference for improved ADC
`performance
`Device powered by the highest of VPn or VH for improved
`redundancy
`User EEPROM: 256 bytes
`Industry-standard 2-wire bus interface (SMBus)
`Guaranteed PDO low with VH, VPn = 1.2 V
`40-lead 6 mm × 6 mm LFCSP
`48-lead 7 mm × 7 mm TQFP
`
`For more information about the ADM1066 register map,
`refer to the AN-698 Application Note.
`
`Rev. B
`Information furnished by Analog Devices is believed to be accurate and reliable. However, no
`responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
`rights of third parties that may result from its use. Specifications subject to change without notice. No
`license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
`Trademarks and registered trademarks are the property of their respective owners.
`
`
`
`
`
`One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
`www.analog.com
`Tel: 781.329.4700
`Fax: 781.461.3113
`©2006 Analog Devices, Inc. All rights reserved.
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 1
`
`

`

`ADM1066
`
`
`
`TABLE OF CONTENTS
`Features .............................................................................................. 1
`Functional Block Diagram .............................................................. 1
`Applications....................................................................................... 1
`General Description ......................................................................... 1
`Revision History ............................................................................... 3
`General Description ......................................................................... 4
`Specifications..................................................................................... 5
`Pin Configurations and Function Descriptions ........................... 8
`Absolute Maximum Ratings.......................................................... 10
`Thermal Characteristics ............................................................ 10
`ESD Caution................................................................................ 10
`Typical Performance Characteristics ........................................... 11
`Powering the ADM1066 ................................................................ 14
`Inputs................................................................................................ 15
`Supply Supervision..................................................................... 15
`Programming the Supply Fault Detectors............................... 15
`Input Comparator Hysteresis.................................................... 16
`Input Glitch Filtering ................................................................. 16
`Supply Supervision with VXn Inputs ...................................... 16
`VXn Pins as Digital Inputs........................................................ 16
`Outputs ............................................................................................ 18
`Supply Sequencing through Configurable Output Drivers .. 18
`Default Output Configuration.................................................. 19
`Sequencing Engine ......................................................................... 20
`Overview...................................................................................... 20
`Warnings...................................................................................... 20
`
`
`
`SMBus Jump/Unconditional Jump .......................................... 20
`Sequencing Engine Application Example............................... 21
`Fault and Status Reporting........................................................ 23
`Voltage Readback............................................................................ 24
`Supply Supervision with the ADC........................................... 24
`Supply Margining ........................................................................... 25
`Overview ..................................................................................... 25
`Open-Loop Margining .............................................................. 25
`Closed-Loop Supply Margining ............................................... 25
`Writing to the DACs .................................................................. 26
`Choosing the Size of the Attenuation Resistor....................... 26
`DAC Limiting/Other Safety Features ...................................... 26
`Applications Diagram .................................................................... 27
`Communicating with the ADM1066........................................... 28
`Configuration Download at Power-Up................................... 28
`Updating the Configuration ..................................................... 28
`Updating the Sequencing Engine............................................. 29
`Internal Registers........................................................................ 29
`EEPROM ..................................................................................... 29
`Serial Bus Interface..................................................................... 29
`SMBus Protocols for RAM and EEPROM.............................. 32
`Write Operations........................................................................ 32
`Read Operations......................................................................... 34
`Outline Dimensions....................................................................... 35
`Ordering Guide .......................................................................... 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 2
`
`

`

`
`
`
`REVISION HISTORY
`
`5/06—Rev. A to Rev. B
`Changes to Features Section ............................................................1
`Changes to Table 1 ............................................................................5
`Changes to Table 2 ............................................................................8
`Changes to Table 3 ..........................................................................10
`Added Table 4 ..................................................................................10
`Added Default Output Configuration Section............................19
`Changes to Fault Reporting Section .............................................19
`Added Table 11 ................................................................................30
`Changes to Ordering Guide...........................................................36
`
`ADM1066
`
`1/05—Rev. 0 to Rev. A
`Changes to Figure 1 ..........................................................................1
`Changes to Absolute Maximum Ratings Section .........................8
`Change to Supply Sequencing through Configurable
`Output Drivers Section ..................................................................16
`Changes to Figure 33 ......................................................................23
`Change to Table 10..........................................................................32
`
`10/04—Revision 0: Initial Version
`
`Rev. B | Page 3 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 3
`
`

`

`ADM1066
`
`
`
`GENERAL DESCRIPTION
`(continued from Page 1)
`
`Supply margining can be performed with a minimum of
`external components. The margining loop can be used for
`in-circuit testing of a board during production (for example, to
`verify the board’s functionality at −5% of nominal supplies),
`or can be used dynamically to accurately control the output
`voltage of a dc-to-dc converter.
`
`The device also provides up to 10 programmable inputs for
`monitoring under, over, or out-of-window faults on up to 10
`supplies. In addition, 10 programmable outputs can be used as
`logic enables. Six of them can also provide up to a 12 V output
`for driving the gate of an N-channel FET, which can be placed
`in the path of a supply.
`
`
`
`The logical core of the device is a sequencing engine. This state-
`machine-based construction provides up to 63 different states.
`This design enables very flexible sequencing of the outputs,
`based on the condition of the inputs.
`
`The device is controlled via configuration data that can be
`programmed into an EEPROM. The whole configuration can
`be programmed using an intuitive GUI-based software package
`provided by Analog Devices, Inc.
`
`AUX2
`
`AUX1
`
`REFIN
`
`REFOUT
`
`REFGND
`
`SDA SCL A1
`
`A0
`
`ADM1066
`
`VREF
`
`SMBus
`INTERFACE
`
`PDO1
`
`PDO2
`PDO3
`PDO4
`PDO5
`
`PDO6
`
`PDO7
`
`PDO8
`PDO9
`
`PDO10
`
`PDOGND
`
`
`
`04609-002
`
`12-BIT
`SAR ADC
`
`GPI SIGNAL
`CONDITIONING
`
`SFD
`
`GPI SIGNAL
`CONDITIONING
`
`SFD
`
`SFD
`
`SFD
`
`REG 5.25V
`CHARGE PUMP
`
`VOUT
`DAC
`
`DEVICE
`CONTROLLER
`
`OSC
`
`EEPROM
`
`CONFIGURABLE
`O/P DRIVER
`(HV)
`
`SEQUENCING
`ENGINE
`
`CONFIGURABLE
`O/P DRIVER
`(HV)
`
`CONFIGURABLE
`O/P DRIVER
`(LV)
`
`CONFIGURABLE
`O/P DRIVER
`(LV)
`
`VOUT
`DAC
`
`GND
`
`DAC2 DAC3 DAC4 DAC5
`DAC1
`VCCP
`Figure 2. Detailed Block Diagram
`
`DAC6
`
`VX1
`
`VX2
`VX3
`VX4
`
`VX5
`
`VP1
`
`VP2
`VP3
`VP4
`
`VH
`
`AGND
`
`VDDCAP
`
`SELECTABLE
`ATTENUATOR
`
`SELECTABLE
`ATTENUATOR
`
`VDD
`ARBITRATOR
`
`Rev. B | Page 4 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 4
`
`

`

`
`
`ADM1066
`
`
`
`SPECIFICATIONS
`VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
`Table 1.
`Parameter
`POWER SUPPLY ARBITRATION
`VH, VPn
`VP
`VH
`VDDCAP
`CVDDCAP
`POWER SUPPLY
`Supply Current, IVH, IVPn
`Additional Currents
`All PDO FET Drivers On
`
`Min
`
`3.0
`
`
`2.7
`10
`
`
`
`
`
`Typ
`
`
`
`
`4.75
`
`
`4.2
`
`1
`
`Max
`
`
`6.0
`14.4
`5.4
`
`
`6
`
`
`
`Unit
`
`V
`V
`V
`V
`μF
`
`mA
`
`mA
`
`Current Available from VDDCAP
`
`
`
`
`
`2
`
`mA
`
`Test Conditions/Comments
`
`Minimum supply required on one of VPn, VH
`Maximum VDDCAP = 5.1 V, typical
`VDDCAP = 4.75 V
`Regulated LDO output
`Minimum recommended decoupling capacitance
`
`VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
`
`VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
`PDO7 to PDO10 off
`Maximum additional load that can be drawn from all PDO
`pull-ups to VDDCAP
`6 DACs on with 100 μA maximum load on each
`Running round-robin loop
`1 ms duration only, VDDCAP = 3 V
`
`
`
`Midrange and high range
`
`
`
`
`
`Low range and midrange
`
`
`
`No input attenuation error
`
`
`
`No input attenuation error
`VREF error + DAC nonlinearity + comparator offset error +
`input attenuation error
`
`Minimum programmable filter length
`Maximum programmable filter length
`
`The ADC can convert signals presented to the VH, VPn,
`and VXn pins. VPn and VH input signals are attenuated
`depending on the selected range. A signal at the pin
`corresponding to the selected range is from 0.573 V to
`1.375 V at the ADC input.
`
`
`
`Endpoint corrected, VREFIN = 2.048 V
`
`DACs Supply Current
`ADC Supply Current
`EEPROM Erase Current
`SUPPLY FAULT DETECTORS
`VH Pin
`Input Impedance
`Input Attenuator Error
`Detection Ranges
`High Range
`Midrange
`VPn Pins
`Input Impedance
`Input Attenuator Error
`Detection Ranges
`Midrange
`Low Range
`Ultralow Range
`VX Pins
`Input Impedance
`Detection Ranges
`Ultralow Range
`Absolute Accuracy
`
`Threshold Resolution
`Digital Glitch Filter
`
`ANALOG-TO-DIGITAL CONVERTER
`Signal Range
`
`
`
`
`
`
`
`
`
`6
`2.5
`
`
`
`
`2.5
`1.25
`0.573
`
`1
`
`0.573
`
`
`
`
`
`
`0
`
`2.2
`1
`10
`
`
`52
`±0.05
`
`
`
`
`52
`±0.05
`
`
`
`
`
`
`
`
`
`
`8
`0
`100
`
`
`
`mA
`
`mA
`
`mA
`
`
`
`
`
`kΩ
`
`%
`
`
`
`V
`14.4
`V
`6
`
`
`kΩ
`
`%
`
`
`
`V
`6
`V
`3
`1.375 V
`
`
`
`MΩ
`
`
`1.375 V
`±1
`%
`
`
`
`
`
`VREFIN
`
`Bits
`μs
`μs
`
`V
`
`V
`
`Bits
`LSB
`
`Rev. B | Page 5 of 36
`
`Input Reference Voltage on REFIN Pin,
`VREFIN
`Resolution
`INL
`
`
`
`
`
`
`2.048
`
`
`
`12
`
`
`
`±2.5
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 5
`
`

`

`ADM1066
`
`
`Parameter
`Gain Error
`Conversion Time
`
`Offset Error
`Input Noise
`AUX1, AUX2 Input Impedance
`BUFFERED VOLTAGE OUTPUT DACs
`Resolution
`Code 0x7F Output Voltage
`
`Range 1
`Range 2
`Range 3
`Range 4
`Output Voltage Range
`LSB Step Size
`INL
`DNL
`Gain Error
`Maximum Load Capacitance
`Settling Time into 50 pF Load
`Load Regulation
`PSRR
`
`
`REFERENCE OUTPUT
`Reference Output Voltage
`Load Regulation
`
`Minimum Load Capacitance
`PSRR
`PROGRAMMABLE DRIVER OUTPUTS
`High Voltage (Charge Pump) Mode
`(PDO1 to PDO6)
`Output Impedance
`VOH
`VOH
`VOH
`2
`IOUTAVG
`Standard (Digital Output) Mode
`(PDO1 to PDO10)
`VOH
`VOH
`VOH
`VOL
`IOL
`2
`ISINK
`2
`RPULL-UP
`ISOURCE (VPn)2
`
`Min
`
`
`
`
`
`1
`
`
`
`
`0.592
`0.796
`0.996
`1.246
`
`
`
`
`
`
`
`
`
`
`
`2.043
`
`
`1
`
`
`
`
`
`11
`10.5
`8
`
`
`
`2.4
`
`VPU − 0.3
`0
`
`
`16
`
`
`Three-State Output Leakage Current
`Oscillator Frequency
`
`
`
`90
`
`
`Typ
`
`0.44
`84
`
`0.25
`
`
`8
`
`
`0.6
`0.8
`1
`1.25
`601.25
`2.36
`
`
`
`
`
`2.5
`60
`40
`
`2.048
`−0.25
`0.25
`
`60
`
`
`
`500
`12.5
`12
`10
`20
`
`
`
`
`
`
`
`
`20
`
`
`
`100
`
`
`Test Conditions/Comments
`Max
`Unit
`VREFIN = 2.048 V
`±0.05 %
`One conversion on one channel
`
`ms
`All 12 channels selected, 16x averaging enabled
`
`ms
`VREFIN = 2.048 V
`±2
`LSB
`
`LSBrms Direct input (no attenuator)
`
`MΩ
`
`
`
`
`
`Bits
`
`
`
`6 DACs are individually selectable for centering on one of
`four output voltage ranges
`
`
`
`
`Same range, independent of center point
`
`Endpoint corrected
`
`
`
`
`Per mA
`DC
`100 mV step in 20 ns with 50 pF load
`
`No load
`Sourcing current, IDACnMAX = −100 μA
`Sinking current, IDACnMAX = 100 μA
`Capacitor required for decoupling, stability
`DC
`
`
`
`0.603 V
`0.803 V
`1.003 V
`1.253 V
`
`mV
`
`mV
`±0.75
`LSB
`±0.4
`LSB
`1
`%
`50
`pF
`2
`μs
`
`mV
`
`dB
`
`dB
`
`
`2.053 V
`
`mV
`
`mV
`
`μF
`
`dB
`
`
`
`
`
`
`IOH = 0
`IOH = 1 μA
`IOH = 7 μA
`2 V < VOH < 7 V
`
`
`VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA
`VPU to VPn = 6.0 V, IOH = 0 mA
`VPU ≤ 2.7 V, IOH = 0.5 mA
`IOL = 20 mA
`Maximum sink current per PDO pin
`Maximum total sink for all PDOs
`Internal pull-up
`Current load on any VPn pull-ups, that is, total source
`current available through any number of PDO pull-up
`switches configured onto any one
`VPDO = 14.4 V
`All on-chip time delays derived from this clock
`
`
`
`14
`13.5
`13.5
`
`
`
`
`4.5
`
`0.50
`20
`60
`29
`2
`
`10
`110
`
`
`kΩ
`V
`V
`V
`μA
`
`
`V
`V
`V
`V
`mA
`mA
`kΩ
`mA
`
`μA
`kHz
`
`
`Rev. B | Page 6 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 6
`
`

`

`
`
`
`Parameter
`DIGITAL INPUTS (VXn, A0, A1)
`Input High Voltage, VIH
`Input Low Voltage, VIL
`Input High Current, IIH
`Input Low Current, IIL
`Input Capacitance
`Programmable Pull-Down Current,
`IPULL-DOWN
`SERIAL BUS DIGITAL INPUTS (SDA, SCL)
`Input High Voltage, VIH
`Input Low Voltage, VIL
`Output Low Voltage, VOL
`2
`SERIAL BUS TIMING
`Clock Frequency, fSCLK
`Bus Free Time, tBUF
`Start Setup Time, tSU;STA
`Start Hold Time, tHD;STA
`SCL Low Time, tLOW
`SCL High Time, tHIGH
`SCL, SDA Rise Time, tr
`SCL, SDA Fall Time, tf
`Data Setup Time, tSU;DAT
`Data Hold Time, tHD;DAT
`Input Low Current, IIL
`SEQUENCING ENGINE TIMING
`State Change Time
`
`Min
`
`2.0
`
`−1
`
`
`
`
`
`2.0
`
`
`
`
`4.7
`4.7
`4
`4.7
`4
`
`
`250
`5
`
`
`
`
`Typ
`
`
`
`
`
`5
`20
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`Max
`
`
`0.8
`
`1
`
`
`
`
`
`0.8
`0.4
`
`400
`
`
`
`
`
`1000
`300
`
`
`1
`
`
`
`Unit
`
`V
`V
`μA
`μA
`pF
`μA
`
`
`V
`V
`V
`
`kHz
`μs
`μs
`μs
`μs
`μs
`μs
`μs
`ns
`ns
`μA
`
`μs
`
`ADM1066
`
`Test Conditions/Comments
`
`Maximum VIN = 5.5 V
`Maximum VIN = 5.5 V
`VIN = 5.5 V
`VIN = 0
`
`VDDCAP = 4.75, TA = 25°C, if known logic state is required
`
`
`
`
`IOUT = −3.0 mA
`
`
`
`
`
`
`
`
`
`
`
`VIN = 0
`
`
`
` 1
`
` At least one of the VH, VPn pins must be ≥3.0 V to maintain the device supply on VDDCAP.
`2 Specification is not production tested, but is supported by characterization data at initial product release.
`
`
`Rev. B | Page 7 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 7
`
`

`

`ADM1066
`
`
`
`PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
`
`
`
`
`PDOGND
`VCCP
`
`32
`
`31
`
`A0 3
`A1 3
`SCL 3
`SDA 3
`AUX2
`AUX1
`VDDCAP
`
`5
`
`4
`
`3
`
`39
`
`38
`
`37
`
`6
`
`PIN 1
`INDICATOR
`
`ADM1066
`TOP VIEW
`(Not to Scale)
`
`GND 4
`
`0
`
`VX1 1
`VX2 2
`VX3 3
`VX4 4
`VX5 5
`VP1 6
`VP2 7
`VP3 8
`VP4 9
`VH 10
`
`6
`
`7
`
`8
`
`9
`
`0
`
`DAC62
`DAC51
`DAC41
`DAC31
`DAC21
`DAC11
`REFOUT1
`REFIN1
`REFGND1
`AGND1
`
`1
`
`2
`
`3
`
`4
`
`5
`
`Figure 3. LFCSP Pin Configuration
`
`NC 3
`
`7
`
`PDOGND
`VCCP
`
`39
`
`38
`
`A0 4
`A1 4
`SCL 4
`SDA 4
`AUX2
`AUX1
`VDDCAP
`
`46
`
`45
`
`44
`
`3
`
`2
`
`1
`
`0
`
`GND 4
`NC 4
`
`8
`
`7
`
`36
`35
`34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`
`NC
`PDO1
`PDO2
`PDO3
`PDO4
`PDO5
`PDO6
`PDO7
`PDO8
`PDO9
`PDO10
`NC
`
`04609-004
`
`
`
`PIN 1
`INDICATOR
`
`ADM1066
`TOP VIEW
`(Not to Scale)
`
`NC 1
`VX1 2
`VX2 3
`VX3 4
`VX4 5
`VX5 6
`VP1 7
`VP2 8
`VP3 9
`VP4 10
`VH 11
`NC 12
`
`1
`
`2
`
`3
`
`4
`
`NC2
`DAC62
`DAC52
`DAC42
`DAC32
`DAC21
`DAC11
`REFOUT1
`REFIN1
`REFGND1
`AGND1
`NC1
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`0
`
`NC = NO CONNECT
`Figure 4. TQFP Pin Configuration
`
`30
`29
`28
`27
`26
`25
`24
`23
`22
`21
`
`PDO1
`PDO2
`PDO3
`PDO4
`PDO5
`PDO6
`PDO7
`PDO8
`PDO9
`PDO10
`
`
`
`04609-003
`
`
`Table 2. Pin Function Descriptions
`Pin No.
`LFCSP
`TQFP
`
`1, 12, 13,
`24, 25, 36,
`37, 48
`2 to 6
`
`Mnemonic
`NC
`
`VX1 to VX5
`(VXn)
`VP1 to VP4
`(VPn)
`
`VH
`
`AGND1
`REFGND1
`REFIN
`
`REFOUT
`
`1 to 5
`
`6 to 9
`
`7 to 10
`
`10
`
`11
`12
`13
`
`14
`
`11
`
`14
`15
`16
`
`17
`
`15 to 20
`21 to 30
`
`18 to 23
`26 to 35
`
`31
`32
`
`33
`34
`35
`36
`37, 38
`
`
`
`38
`39
`
`40
`41
`42
`43
`44, 45
`
`
`
`DAC1 to DAC6
`PDO10 to
`PDO1
`PDOGND1
`VCCP
`
`A0
`A1
`SCL
`SDA
`AUX2, AUX 1
`
`
`
`Description
`No Connection.
`
`High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
`1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
`Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
`attenuation on a potential divider connected to these pins, the output of which connects to a supply
`fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
`High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
`attenuation on a potential divider connected to this pin, the output of which connects to a
`supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
`Ground Return for Input Attenuators.
`Ground Return for On-Chip Reference Circuits.
`Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
`The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
`2.048 V Reference Output. Typically connected to REFIN. Note that the capacitor must be
`connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
`Voltage Output DACs. These pins default to high impedance at power-up.
`Programmable Output Drivers.
`
`Ground Return for Output Drivers.
`Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
`and GND. A 10 μF capacitor is recommended for this purpose.
`Logic Input. This pin sets the seventh bit of the SMBus interface address.
`Logic Input. This pin sets the sixth bit of the SMBus interface address.
`SMBus Clock. Input pin. Open-drain. Requires external resistive pull-up.
`SMBus Data. Bidirectional pin. Open-drain. Requires external resistive pull-up.
`Auxiliary, Single-Ended ADC Inputs.
`
`
`
`Rev. B | Page 8 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 8
`
`

`

`
`
`
`
`Pin No.
`LFCSP
`TQFP
`39
`46
`
`Mnemonic
`VDDCAP
`
`40
`
`47
`
`GND1
`
`ADM1066
`
`Description
`Device Supply Voltage. Linearly regulated from the highest of the VPn, VH pins to a typical of 4.75 V.
`Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is
`recommended for this purpose.
`Supply Ground.
`
` 1
`
` In a typical application, all ground pins are connected together.
`
`
`
`Rev. B | Page 9 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 9
`
`

`

`ADM1066
`
`
`
`ABSOLUTE MAXIMUM RATINGS
`Table 3.
`Parameter
`Voltage on VH Pin
`Voltage on VPn Pins
`Voltage on VXn Pins
`Voltage on AUX1, AUX2, REFIN Pins
`Voltage on A0, A1 Pins
`Voltage on REFIN, REFOUT Pins
`Voltage on VDDCAP, VCCP Pins
`Voltage on DACn Pins
`Voltage on PDOn Pins
`Voltage on SDA, SCL Pins
`Voltage on GND, AGND, PDOGND,
`REFGND Pins
`Input Current at Any Pin
`Package Input Current
`Maximum Junction Temperature (TJ max)
`Storage Temperature Range
`Lead Temperature,
`Soldering Vapor Phase, 60 sec
`ESD Rating, All Pins
`
`
`Rating
`16 V
`7 V
`−0.3 V to +6.5 V
`−0.3 V to +5 V
`−0.3 V to +7 V
`5 V
`6.5 V
`6.5 V
`16 V
`7 V
`−0.3 V to +0.3 V
`
`±5 mA
`±20 mA
`150°C
`−65°C to +150°C
`
`215°C
`2000 V
`
`Stresses above those listed under Absolute Maximum Ratings
`may cause permanent damage to the device. This is a stress
`rating only; functional operation of the device at these or any
`other conditions above those indicated in the operational
`section of this specification is not implied. Exposure to absolute
`maximum rating conditions for extended periods may affect
`device reliability.
`
`THERMAL CHARACTERISTICS
` θJA is specified for the worst-case conditions, that is, a device
`soldered in a circuit board for surface-mount packages.
`Table 4. Thermal Resistance
`Package Type
`40-Lead LFCSP
`48-Lead TQFP
`
`
`Unit
`°C/W
`°C/W
`
`θJA
`25
`50
`
`
`
`ESD CAUTION
`ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
`the human body and test equipment and can discharge without detection. Although this product features
`proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
`electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
`degradation or loss of functionality.
`
`
`
`
`Rev. B | Page 10 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 10
`
`

`

`ADM1066
`
`
`
`04609-053
`
`6
`
`5
`
`4
`
`1
`
`2
`
`3
`VVP1 (V)
`Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
`
`
`04609-054
`
`2
`
`4
`
`6
`
`10
`
`
`
`
`
`TYPICAL PERFORMANCE CHARACTERISTICS
`
`180
`
`160
`
`140
`
`120
`
`100
`
`80
`
`60
`
`40
`
`20
`
`0
`
`0
`
`5.0
`
`4.5
`
`4.0
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0
`
`IVP1 (μA)
`
`IVH (mA)
`
`
`
`04609-050
`
`6
`
`5
`
`04609-051
`
`4
`
`2
`
`3
`VVP1 (V)
`Figure 5. VVDDCAP vs. VVP1
`
`
`0
`
`1
`
`6
`
`012345
`
`6
`
`012345
`
`VVDDCAP (V)
`
`VVDDCAP (V)
`
`8
`VVH (V)
`Figure 9. IVH vs. VVH (VH as Supply)
`
`
`12
`
`14
`
`16
`
`
`
`
`
`04609-055
`
`6
`
`5
`
`4
`
`1
`
`2
`
`3
`VVH (V)
`Figure 10. IVH vs. VVH (VH Not as Supply)
`
`
`0
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`50
`
`0
`
`0
`
`IVH (μA)
`
`10
`
`4
`
`6
`
`8
`VVH (V)
`Figure 6. VVDDCAP vs. VVH
`
`
`12
`
`14
`
`16
`
`
`
`
`
`04609-052
`
`6
`
`5
`
`4
`
`1
`
`2
`
`3
`VVP1 (V)
`Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
`
`
`0
`
`2
`
`5.0
`
`4.5
`
`4.0
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0
`
`0
`
`IVP1 (mA)
`
`Rev. B | Page 11 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 11
`
`

`

`04609-066
`
`
`
`3000
`
`4000
`
`1000
`
`2000
`CODE
`Figure 14. DNL for ADC
`
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0
`
`–0.2
`
`–0.4
`
`–0.6
`
`–0.8
`
`–1.0
`
`0
`
`DNL (LSB)
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0
`
`–0.2
`
`–0.4
`
`–0.6
`
`INL (LSB)
`
`
`
`04609-056
`
`15.0
`
`ADM1066
`
`
`
`14
`
`12
`
`10
`
`8 6 4 2 0
`
`5.0
`
`4.5
`
`4.0
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0
`
`VPDO1 CHARGE PUMPED
`
`VPDO1 (V)
`
`2.5
`
`5.0
`
`7.5
`ILOAD (μA)
`Figure 11. VPDO1 (FET Drive Mode) vs. ILOAD
`
`
`10.0
`
`12.5
`
`VP1 = 5V
`
`VP1 = 3V
`
`04609-063
`
`
`
`3000
`
`4000
`
`1000
`
`2000
`CODE
`Figure 15. INL for ADC
`
`
`9894
`
`04609-064
`
`
`
`25
`
`81
`
`2047
`
`2048
`CODE
`Figure 16. ADC Noise, Midcode Input, 10,000 Reads
`
`
`2049
`
`–0.8
`
`–1.0
`
`0
`
`12000
`
`10000
`
`8000
`
`6000
`
`4000
`
`2000
`
`0
`
`HITS PER CODE
`
`
`
`04609-057
`
`6
`
`
`
`04609-058
`
`60
`
`Rev. B | Page 12 of 36
`
`1
`
`2
`
`3
`ILOAD (mA)
`Figure 12. VPDO1 (Strong Pull-Up VP) vs. ILOAD
`
`
`4
`
`5
`
`VP1 = 5V
`
`VP1 = 3V
`
`10
`
`20
`
`30
`ILOAD (μA)
`Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
`
`
`40
`
`50
`
`0
`
`0
`
`4.5
`
`4.0
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0
`
`0
`
`VPDO1 (V)
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 12
`
`

`

`ADM1066
`
`VP1 = 3.0V
`
`VP1 = 4.75V
`
`
`
`
`
`04609-065
`
`80
`
`100
`
`04609-061
`
`80
`
`100
`
`–20
`
`0
`
`40
`20
`TEMPERATURE (°C)
`Figure 19. DAC Output vs. Temperature
`
`
`60
`
`VP1 = 3.0V
`
`VP1 = 4.75V
`
`–20
`
`0
`
`40
`20
`TEMPERATURE (°C)
`Figure 20. REFOUT vs. Temperature
`
`
`60
`
`1.005
`
`1.004
`
`1.003
`
`1.002
`
`1.001
`
`1.000
`
`0.999
`
`0.998
`
`0.997
`
`0.996
`
`0.995
`–40
`
`2.058
`
`2.053
`
`2.048
`
`2.043
`
`2.038
`–40
`
`DAC OUTPUT
`
`REFOUT (V)
`
`DAC
`BUFFER
`OUTPUT
`
`20kΩ
`
`47pF
`
`PROBE
`POINT
`
`
`
`04609-059
`
`CH1 200mV
`
`M1.00μs
`
`CH1 756mV
`
`Figure 17. Transient Response of DAC Code Change into Typical Load
`
`
`100kΩ
`
`DAC
`BUFFER
`OUTPUT
`
`1V
`
`PROBE
`POINT
`
`
`
`04609-060
`
`CH1 200mV
`
`M1.00μs
`
`CH1 944mV
`
`Figure 18. Transient Response of DAC to Turn-On from HI-Z State
`
`
`
`
`
`
`1
`
`1
`
`
`
`
`
`Rev. B | Page 13 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 13
`
`

`

`VDDCAP
`
`INTERNAL
`DEVICE
`SUPPLY
`
`
`
`04609-022
`
`OUT
`4.75V
`LDO
`
`OUT
`4.75V
`LDO
`
`OUT
`4.75V
`LDO
`
`OUT
`4.75V
`LDO
`
`OUT
`4.75V
`LDO
`
`IN
`
`EN
`
`IN
`
`EN
`
`IN
`
`EN
`
`IN
`
`EN
`
`IN
`
`EN
`
`SUPPLY
`COMPARATOR
`
`Figure 21. VDD Arbitrator Operation
`
`ADM1066
`
`
`
`POWERING THE ADM1066
`The ADM1066 is powered from the highest voltage input on
`either the positive-only supply inputs (VPn) or the high voltage
`supply input (VH). This technique offers improved redundancy
`because the device is not dependent on any particular voltage
`rail to keep it operational. The same pins are used for supply
`fault detection (discussed later in the Supply Supervision
`section). A VDD arbitrator on the device chooses which supply
`to use. The arbitrator can be considered an OR’ing of five LDOs
`together. A supply comparator chooses the highest input to
`provide the on-chip supply. There is minimal switching loss
`with this architecture (~0.2 V), resulting in the ability to power
`the ADM1066 from a supply as low as 3.0 V. The supply on the
`VXn pins cannot be used to power the device.
`
`An external capacitor to GND is required to decouple the on-chip
`supply from noise. This capacitor should be connected to the
`VDDCAP pin, as shown in Figure 21. The capacitor has another
`use during brownouts (momentary loss of power). Under these
`conditions, when the input supply (VPn or VH) dips transiently
`below VDD, the synchronous rectifier switch immediately turns
`off so that it does not pull VDD down. The VDD capacitor can
`then act as a reservoir to keep the device active until the next
`highest supply takes over the powering of the device. A 10 μF
`capacitor is recommended for this reservoir/decoupling function.
`
`When two or more supplies are within 100 mV of each other,
`the supply that first takes control of VDD keeps control. For
`example, if VP1 is connected to a 3.3 V supply, VDD powers up
`to approximately 3.1 V through VP1. If VP2 is then connected
`to another 3.3 V supply, VP1 still powers the device, unless VP2
`goes 100 mV higher than VP1.
`
`VP1
`
`VP2
`
`VP3
`
`VP4
`
`VH
`
`
`
`
`
`
`
`
`
`Rev. B | Page 14 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 14
`
`

`

`
`
`
`
`INPUTS
`SUPPLY SUPERVISION
`The ADM1066 has 10 programmable inputs. Five of these are
`dedicated supply fault detectors (SFDs). These dedicated inputs
`are called VH and VPn (VP1 to VP4) by default. The other five
`inputs are labeled VXn (VX1 to VX5) and have dual functionality.
`They can be used as either supply fault detectors, with similar
`functionality as VH and VPn, or CMOS/TTL-compatible logic
`inputs to the devices. Therefore, the ADM1066 can have up to 10
`analog inputs, a minimum of five analog inputs and five digital
`inputs, or a combination. If an input is used as an analog input,
`it cannot be used as a digital input. Therefore, a configuration
`requiring 10 analog inputs has no available digital inputs. Table 6
`shows the details of each input.
`
`OV
`COMPARATOR
`
`GLITCH
`FILTER
`
`FAULT
`OUTPUT
`
`ADM1066
`
`The resolution is given by
`Step Size = Threshold Range/255
`
`Therefore, if the high range is selected on VH, the step size can
`be calculated as follows:
`(14.4 V − 4.8 V)/255 = 37.6 mV
`
`Table 5 lists the upper and lower limit of each available range,
`the bottom of each range (VB), and the range itself (VR).
`Table 5. Voltage Range Limits
`VB (V)
`Voltage Range (V)
`0.573
`0.573 to 1.375
`1.25
`1.25 to 3.00
`2.5
`2.5 to 6.0
`4.8
`4.8 to 14.4
`The threshold value required is given by
`VT = (VR × N)/255 + VB
`
`VR (V)
`0.802
`1.75
`3.5
`9.6
`
`+ –
`
`+ –
`
`RANGE
`SELECT
`
`ULTRA
`LOW
`
`VPn
`
`VREF
`
`LOW
`
`MID
`
`where:
`
`VT is the desired threshold voltage (UV or OV).
`VR is the voltage range.
`N is the decimal value of the 8-bit code.
`VB is the bottom of the range.
`
`
`
`04609-023
`
`UV
`COMPARATOR
`
`FAULT TYPE
`SELECT
`
`Figure 22. Supply Fault Detector Block
`
`PROGRAMMING THE SUPPLY FAULT DETECTORS
`The ADM1066 has up to 10 supply fault detectors (SFDs) on its
`10 input channels. These highly programmable reset generators
`enable the supervision of up to 10 supply voltages. The supplies
`can be as low as 0.573 V and as high as 14.4 V. The inputs can
`be configured to detect an undervoltage fault (the input voltage
`drops below a preprogrammed value), an overvoltage fault (the
`input voltage rises above a preprogrammed value), or an out-of-
`window fault (undervoltage or overvoltage). The thresholds can
`be programmed to an 8-bit resolution in registers provided in
`the ADM1066. This translates to a voltage resolution that is
`dependent on the range selected.
`
`Reversing the equation, the code for a desired threshold is given by
`N = 255 × (VT − VB)/VR
`
`If, for example, the user wants to set a 5 V OV threshold on
`VP1, the code to be programmed in the PS1OVTH register
`(discussed in the AN-698 Application Note) is given by
`N = 255 × (5 − 2.5)/3.5
`
`Therefore, N = 182 (1011 0110 or 0xB6).
`
`
`
`
`
`
`
`Table 6. Input Functions, Thresholds, and Ranges
`Input
`Function
`Voltage Range (V)
`VH
`High V Analog Input
`2.5 to 6.0
`
`
`4.8 to 14.4
`VPn
`Positive Analog Input
`0.573 to 1.375
`
`
`1.25 to 3.00
`
`
`2.5 to 6.0
`VXn
`High Z Analog Input
`0.573 to 1.375
`
`Digital Input
`0 to 5
`
`Maximum Hysteresis
`425 mV
`1.16 V
`97.5 mV
`212 mV
`425 mV
`97.5 mV
`N/A
`
`Voltage Resolution (mV)
`13.7
`37.6
`3.14
`6.8
`13.7
`3.14
`N/A
`
`Glitch Filter (μs)
`0 to 100
`0 to 100
`0 to 100
`0 to 100
`0 to 100
`0 to 100
`0 to 100
`
`Rev. B | Page 15 of 36
`
`Samsung Electronics Co., Ltd.
`Ex. 1061, p. 15
`
`

`

`ADM1066
`