US005630096A
`Patent Number:
`11
`45 Date of Patent:
`
`5,630,096
`May 13, 1997
`
`FOREIGN PATENT DOCUMENTS
`549139 6/1993 European Pat. Off..
`OTHER PUBLICATIONS
`IBM Technical Disclosure Bulletin, vol. 33, No. 6A, pp.
`269-272, Nov. 1990.
`IBM Technical Disclosure Bulletin, vol. 33, No. 6A, pp.
`265-266, Nov. 1990.
`IBM Technical Disclosure Bulletin, vol. 31, No. 9, pp.
`351-354, Feb. 1989.
`IBM Technical Disclosure Bulletin, vol. 33, No. 3A, pp.
`441-442, Aug. 1990.
`Micron Semiconductor, Inc., Spec Sheet, MT48LC2M8S1
`S. cover page and pp. 33 and 37, 1993.
`Primary Examiner-Frank J. Asta
`Attorney, Agent, or Firm-Burns, Doane, Swecker & Mathis
`57
`ABSTRACT
`A controller for a synchronous DRAM is provided for
`maximizing throughput of memory requests to the synchro
`nous DRAM. The controller maintains the spacing between
`the commands to conform with the specifications for the
`synchronous DRAMs while preventing gaps from occurring
`in the data slots to the synchronous DRAM. Furthermore,
`the controller allows memory requests and commands to be
`issued out of order so that the throughput may be maximized
`by overlapping required operations which do not specifically
`involve data transfer. To achieve this maximized throughput,
`memory requests are tagged for indicating a sending order.
`Thereafter, the memory requests may be arbitrated when
`conflicting memory requests are queued and this arbitration
`process is then decoded for simultaneously updating sched
`uling constraints. The memory requests may be further
`qualified based on the scheduling constraints and a con
`mand stack of memory request is then developed for modi
`fying update queues. The controller also functions by receiv
`ing a controller clock signal and generating an SDRAM
`clock signal by dividing this controller clock signal.
`
`20 Claims, 6 Drawing Sheets
`
`- OC
`
`United States Patent 19
`Zuravleff et al.
`
`54 CONTROLLER FOR ASYNCHRONOUS
`DRAM THAT MAXIMIZES THROUGHPUT
`BY ALLOWING MEMORY REQUESTS AND
`COMMANDS TO BE ISSUED OUT OF
`ORDER
`
`75
`
`Inventors: William K. Zuravleff, Mountainview:
`Timothy Robinson, Boulder Creek,
`both of Calif.
`73 Assignee: Microunity Systems Engineering, Inc.,
`Sunnyvale, Calif.
`
`(21) Appl. No.: 437,975
`22 Filled:
`May 10, 1995
`(51] Int. Cl. .................. G06F 1300
`52 U.S. Cl. ................................... 395/481: 364/DIG. 1;
`365/233; 395/432; 395/477; 395/478; 395/485;
`395/494; 395/496
`58 Field of Search ............................. 365/233:395/432,
`395/477,478,481,485, 494, 496
`
`56
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,685,088
`8/1987 annucci.
`4,691.302
`9/1987 Mattanusch.
`4,734,888 3/1988 Tielert.
`4,740,924 4/1988 Tielert.
`4,790,418 12/1988 Masterson.
`5,077,693 12/1991 Hardee et al. .
`5,179,667
`1/1993 Iyer.
`5,193,193 3/1993 Iyer.
`5,253,214 10/1993 Herrmann.
`5,253,357 10/1993 Allen et al. .
`5,276.856
`1/1994 Norsworthy et al. .
`5,278,967
`1/1994 Curran.
`5,283,877 2/1994 Gastinel et al..
`5,287,327 2/1994 Takasugi.
`5,301278 4/1994 Bowater et al..
`5,311,483 5/1994 Takasugi.
`5,381536 i? 1995 Phelps et al. ........................... 395/375
`5,513,148 4/1996 Zagar ...................................... 365,233
`
`
`
`
`
`
`
`N
`
`OUT
`
`
`
`CONTROLLER
`CLOCK
`
`BANK
`DATA PATH
`
`DATA PATH
`
`RETURN DATA
`DATA PATH
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 1
`
`

`

`U.S. Patent
`
`May 13, 1997
`
`Sheet 1 of 6
`
`5,630,096
`
`N
`
`RETURN DATA
`DATA PATH
`
`CONTROLER
`CLOCK
`
`
`
`CONTROL
`BLOCK
`
`FIG. 1
`
`
`
`COMMAND
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 2
`
`

`

`U.S. Patent
`
`May 13, 1997
`
`Sheet 2 of 6
`
`5,630,096
`
`
`
`4:... it
`
`PROCESSOR
`
`
`
`16MB SDRAM
`D A CLK
`
`16MB SDRAM
`D A CLK
`
`
`
`
`
`
`
`314
`
`64MB SDRAM
`D A CK
`
`64MB SDRAM
`D A CK
`
`D
`
`4:... it
`
`PROCESSOR
`
`CK
`
`
`
`FIG. 3(a)
`
`FIG. 3(b)
`
`300
`
`
`
`
`
`
`
`MICRO
`PROCESSOR /
`CK
`
`320
`
`16MB SDRAM
`D A CK
`
`
`
`
`
`
`
`500
`
`322
`
`64MB SDRAM
`)
`A
`
`MICRO
`PROCESSOR A/C
`CK
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 3
`
`

`

`U.S. Patent
`
`May 13, 1997
`
`Sheet 3 of 6
`
`5,630,096
`
`MCRO
`Poisor A/C
`
`330
`
`
`
`
`
`
`
`52
`
`8
`
`
`
`co-
`PSOR A/C
`CK
`
`
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`
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`
`16MB SDRAM
`D A CK
`
`6MB SDRAM
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`A CK
`
`16MB SDRAM
`
`16MB SDRAM
`) A CK
`
`
`
`500
`
`350
`
`
`
`MICRO
`PROCESSOR A/C
`CK
`
`WICRO
`PROCESSOR A/C
`CLK
`
`
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 4
`
`

`

`0
`500000
`1000000
`1500000
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`CONTROLLER CLOCK
`
`|
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`RESET
`
`RESTART GO
`
`READY
`
`CONTROLLER INPUT BUS
`
`CONTROLLER RETURN BUS REQUEST
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`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 5
`
`

`

`U.S. Patent
`
`May 13, 1997
`
`Sheet S of 6
`
`5,630,096
`
`
`
`
`
`
`
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`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 6
`
`

`

`U.S. Patent
`
`May 13, 1997
`
`Sheet 6 of 6
`
`5,630,096
`
`
`
`
`
`
`
`
`
`
`
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`SS}}{00\}
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 7
`
`

`

`5,630,096
`
`1.
`CONTROLLER FOR A SYNCHRONOUS
`DRAM THAT MAXIMIZES THROUGHPUT
`BY ALLOWING MEMORY REQUESTS AND
`COMMANDS TO BE SSUED OUT OF
`ORDER
`
`O
`
`5
`
`30
`
`35
`
`BACKGROUND
`The present invention is directed to a controller for
`maximizing throughput of memory requests from an exter
`nal device to a synchronous DRAM. More particularly, the
`present invention is directed to a controller which prioritizes
`multiple memory requests from the external device and
`issues reordered memory requests to the synchronous
`DRAM so that the throughput from the external device to the
`synchronous DRAM is maximized.
`Synchronous DRAMs are relatively new devices which
`are similar to conventional DRAMs but the synchronous
`DRAMs have some important differences. The architecture
`of the synchronous DRAMs is similar to conventional
`20
`DRAMs. For instance, the synchronous DRAMs have mul
`tiplexed address pins, control pins such as RAS, CAS, CS,
`WE, and bidirectional data pins. Also, the synchronous
`DRAMs activate a page as does the conventional DRAM
`and then subsequent accesses to that page occur faster.
`25
`Accordingly, a precharge operation must be performed
`before another page is activated.
`One difference between synchronous DRAMs and con
`ventional DRAMs is that all input signals are required to
`have a set-up and hold time with respect to the clockinput
`in synchronous DRAMs. The hold time is referenced to the
`same clock input. The outputs also have a clock to output
`delay referenced to the same clock. Thereby, the synchro
`nous characteristics are provided. Furthermore, the synchro
`nous DRAMs are pipelined which means that the latency is
`generally greater than one clock cycle. As a result, second
`and third synchronous DRAM commands can be sent before
`the data from the original write request arrives at the
`synchronous DRAM. Also, the synchronous DRAMs have
`two internal banks of data paths which generally correspond
`to separate memory arrays sharing I/O pins. The two internal
`banks of memory paths are a JEDEC standard for synchro
`nous DRAMs. An example of a known synchronous DRAM
`is a 2 MEGx8 SDRAM from Micron Semiconductor, Inc.,
`model no. MT48LC2M8SS1S.
`In the synchronous DRAMs, almost all I/O timings are
`referenced to the input clock. Minimum parameters such as
`CAS latency remain but are transformed from electrical
`timing requirements to logical requirements so that they are
`an integral number of clock cycles. The synchronous
`50
`DRAMs for at least by-four and by-eight parts are a JEDEC
`standard with defined pin outs and logical functions.
`Because the synchronous DRAMs are internally pipelined,
`the pipe stage time is less than the minimum latency so that
`spare time slots can be used for other functions. For instance,
`the spare time slots can be used for bursting out more data
`(similar to a nibble mode) and issuing another "command”
`with limitations.
`Certain problems arise when using synchronous DRAMs
`which must be addressed. For instance, the clock to output
`delay can equal the whole cycle. Also, because the synchro
`nous DRAMs are pipelined, a second request must be given
`before the first one is complete to achieve full performance.
`Furthermore, the output electrical/load/timing specifications
`of synchronous DRAMs are difficult to meet. Therefore, a
`65
`controller is desired for interfacing the synchronous DRAMs
`with devices which read and write, such as microprocessors,
`
`45
`
`55
`
`2
`and meeting JEDEC standards for synchronous DRAMs so
`that versatile synchronous DRAMs may be provided and
`applied in many design applications.
`
`SUMMARY
`An object of the present invention is to control a syn
`chronous DRAM by interfacing an external device, such as
`a microprocessor, for reading and writing to the synchronous
`DRAM.
`Another object of the present invention is to provide a
`controller for a synchronous DRAM which can buffer and
`process multiple memory requests so that greater
`throughput, or an equivalent throughput at less latency, can
`be achieved by the synchronous DRAM.
`A still further object of the present invention is to provide
`a controller for issuing and completing requests out of order
`with respect to the received or issued order so that the
`throughput of the synchronous DRAM is improved by
`overlapping required operations, which do not specifically
`involve data transfer, with operations involving data trans
`fer.
`A still further object of the present invention is to provide
`a controller for a synchronous DRAM that schedules
`memory request commands as closely together as possible
`within the timing constraints of the synchronous DRAM so
`that the throughput of the memory requests is maximized.
`These objects of the present invention are fulfilled by
`providing a controller for a synchronous DRAM comprising
`a sorting unit for receiving memory requests and sorting said
`memory requests based on their addresses and a throughput
`maximizing unit for processing said memory requests to the
`synchronous DRAM in response to scheduling which maxi
`mizes the use of data slots by the synchronous DRAM. The
`controller is able to prioritize and issue multiple requests to
`the synchronous DRAM in a different order than was
`received or issued such that the out of order memory
`requests improve the throughput to the synchronous DRAM.
`In particular, the controller issues memory requests as
`closely together as possible while maintaining the timing
`constraints of the synchronous DRAM based on its speci
`fications.
`The objects of the present invention are also fulfilled by
`providing a method for controlling a synchronous DRAM
`comprising the steps of receiving memory requests and
`sorting said memory requests based on their addresses, and
`maximizing throughput of said memory requests to the
`synchronous DRAM so that use of data slots by the syn
`chronous DRAM is maximized. Similarly, this method con
`trols the memory requests issued to the synchronous DRAM
`so that they are spaced as closely as possible while main
`taining the timing constraints of the synchronous DRAM
`based on its specifications.
`Further scope of applicability of the presentinvention will
`become apparent from the detailed description given here
`inafter. However, it should be understood that the detailed
`description and specific examples, while indicating pre
`ferred embodiments of the invention, are given by way of
`illustration only, since various changes and modifications
`within the spirit and scope of the invention will become
`apparent to those skilled in the art from this detailed descrip
`tion.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention will become more fully understood
`from the detailed description given hereinbelow and the
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 8
`
`

`

`5,630,096
`
`10
`
`15
`
`20
`
`25
`
`3
`accompanying drawings which are given by way of illus
`tration only, and thus are not limitative of the present
`invention, wherein:
`FIG. 1 illustrates a controller for a synchronous DRAM
`according to an embodiment of the present invention;
`FIG. 2 illustrates a block diagram for prioritizing and
`issuing multiple requests to the synchronous DRAM by the
`controller illustrated for an embodiment of the present
`invention;
`FIGS. 3(a)-3(h) illustrate part configurations of the syn
`chronous DRAM for embodiments of the present invention;
`and
`FIGS. 4(a)-4(c) illustrate timing diagrams for commands
`to the synchronous DRAM.
`DETALED DESCRIPTION
`FIG. 1 illustrates a controller for a synchronous DRAM
`according to an embodiment of the present invention. In
`FIG. 1, signals corresponding to memory requests and
`commands from an external device, such as a microproces
`sor for example, are input to the controller at a bank sortunit
`10. The bank sort unit 10 processes address, control, and
`data signals and sorts the databased on the address before
`sending the data to bank datapaths 20 and 30. The output of
`the bank data paths 20 and 30 are multiplexed by a multi
`plexer 40 and input to a pad driver 50 before being input to
`the synchronous DRAM 100. The memory requests and
`commands are tagged to indicate their received order. The
`tags are used to indicate the order of the memory requests
`and commands for achieving increased throughput or
`re-ordering the memory requests and commands as will be
`further described. The tags may be associated with the
`memory requests and commands at the external device or
`may be generated by the bank sortunit 10. Areturn datapath
`60 receives data from the bank data paths 20 and 30 and the
`synchronous DRAM 100 via the pad driver 50 and is used
`to process and re-order the data, if necessary, based on the
`tag information.
`The controller also includes a control block 70 which
`receives a controller clock. The control block 70 outputs a
`slower SDRAM clock which is based on the controller
`clock. More specifically, the SDRAM clockis derived in the
`control block 70 by dividing the controller clock with a
`programmable divisor between 4 and 32, inclusive, and
`applying wave shaping circuits having programmable offset
`and duty cycle inputs. The SDRAM clockis then input to the
`synchronous DRAM 100.
`The controller may be implemented in BiCMOS technol
`ogy which includes bipolar (ECL) style logic with CMOS
`50
`pad drivers having integrated low swing differential to full
`swing (LVTTL) voltage level converters in a preferred
`embodiment. Because the logic is implemented in the bipo
`lar (ECL) style circuits, very high speeds are possible with
`cycle times being in excess of 1 GHz. The controller is
`designed to run at a clock frequency greater than the
`SDRAM clock frequency. Both the SDRAM clock and
`sampling point for incoming data can be controlled to the
`accuracy of the controller clock so that a fully synchronous
`circuit can be maintained which has a sample point resolu
`tion greater than the SDRAM clock.
`The programmable sample point overcomes the problem
`of the SDRAM clock to output delay being greater than or
`equal to one SDRAM clock period by providing a sampling
`point which can be placed at a particular controller clock
`edge. In the present controller, no analog delay elements are
`required or used. If analog delay elements were to be used
`
`65
`
`4
`in a different controller, which has a single clock frequency
`for the controller and the synchronous DRAM for example,
`the data generally would have to be resynchronized to the
`single clock after sampling. As a result, the data would be
`delayed by another entire SDRAM clock period before the
`data is available for use by the processor if analog delay
`elements are used. In addition, the return data path 60 runs
`at the same timing as the SDRAM clockbut can be offset in
`time from the SDRAM clock edges by a programmable
`number of controller clock edges. The programmable clock
`and sampling points can also be used to provide adequate
`timing margins for different printed circuit board trace
`lengths or different loading conditions from various part
`configurations.
`At the input from the external device, or within the
`controller, each memory request is "tagged” or assigned an
`integer to indicate the order in which the memory request
`was received as part of the control stream. This tag has three
`purposes. One purpose is for the tag to be passed with the
`loaded data back to the external device so that loads which
`are returned out of order will be indicated. A second purpose
`is that the tag may be used to send the earliest request to the
`synchronous DRAM when multiple pending requests may
`be serviced. A third purpose is that the tag may be used to
`service the earliest pending request only if the return of load
`data is required to be in order such as during system
`integration or debug. The controller functions to translate
`memory load and store requests into synchronous DRAM
`commands. For example, a simple load might be translated
`to the synchronous DRAM as the following sequence of
`commands: precharge, activate (for the high portion of
`addresses), and read (for the low portion of addresses). The
`controller also functions to enforce timing requirements and
`to queue a minimum of two requests. Furthermore, the
`controller functions to interrupt normal operation for
`required refresh, power on reset (load mode register), power
`down, and power up. The main purpose of the controller is
`to allow or provide greater throughput, or equivalent
`throughput at less latency, from the synchronous DRAMs.
`This controller is applicable to computer systems where
`processors can request data much faster than the memory
`can provide the data (generally four to fifty times faster).
`Also, the controller is applicable to processors which do not
`stall for an individual memory request or processors which
`do not stop to wait for data where possible. The main goal
`of the controller is to achieve a high throughput of the
`memory requests and commands. Another importantissue is
`latency, but minimizing latency is secondary to maximizing
`throughput in the present controller. Another goal of the
`controller is to provide flexibility in timing and
`configuration, but this is also secondary to maximizing
`throughput.
`One feature of the controller is to buffer multiple memory
`requests, and in an example of the present embodiment, two
`memory requests can be buffered per bank Buffering up to
`one request per bank allows for the opportunity of the banks
`being in parallel. By buffering two requests to the same
`bank, the same page address match computation and the
`actual memory data transfer may be placed in parallel.
`Another feature of the controller is to issue and complete
`requests out of order with respect to the order received or the
`order issued by the external device. Out of order issue/
`completion can improve throughput by overlapping required
`operations which do not specifically involve data transfer
`with operations involving data transfer.
`The controller for state machines implemented in digital
`logic allows for out of order issue and completion by using
`
`30
`
`35
`
`40
`
`45
`
`55
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 9
`
`

`

`S
`dynamic constraint based, maximum throughputscheduling.
`In general, the memory requests are resolved into their
`required sequences of precharge/bank activate/read-write
`Sequences and placed in a queue where one queue per bank
`exists. Dynamic constraint based logic determines which
`requests are ready to issue and scheduling logic chooses the
`requests thereafter, but not necessarily in the order that the
`requests are received. The requests are chosen according to
`the requests which can be issued to the synchronous DRAM
`without causing reduction in throughput. For example, bank
`1 may be precharged while bank 0 is bursting outdata. Also,
`the scheduling and logic select requests such that the
`throughput is maximized. For example, a read to a page and
`bank is chosen when directly following a read to that same
`page and bank.
`
`10
`
`5,630,096
`
`6
`The functions for each of the units described above do not
`have to be accomplished within four pulses of the controller
`clock, or a certain number of pulses of the controller clock.
`However, these steps must be completed within one
`SDRAM clock pulse. The SDRAM clock pulse relates to the
`controller clock and is determined by dividing the controller
`clock with the programmable divisor. A command stack of
`memory requests is developed for each bank of the data
`paths. The command update unit 210 updates the per bank
`command stack. An illustration of the update performed is
`provided in Table 1 below for a two-deep control stack.
`
`TABLE 1.
`
`COMMAND UPDATE
`
`Incoming
`Request
`
`go rw mp pop pnp
`incoming transactions, no pop's
`
`TOS
`
`Next
`
`TOS
`
`Next
`
`st
`
`tr
`
`tap
`
`nr nnp
`
`st
`
`tr
`
`tinp
`
`nr anp
`
`1 X X
`1 X X
`pop's
`
`O
`O
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`O
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`O X X X X
`X X X X
`
`1
`2
`
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`tr
`tinp
`rw
`mp
`
`1.
`
`O X X
`X X X X O X X X X
`O
`O X X
`2 X X X X
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`1.
`X X X X
`tr
`O X X
`1.
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`t
`0
`m ninp
`simultaneous incoming transactions and
`pops
`
`1.
`2
`
`X X
`1.
`1 X X
`do nothing
`
`O X X
`O X X
`O X X
`
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`1.
`
`X X X X
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`1
`2
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`tr
`0
`rw
`up
`
`O X X X X O X X X X
`1 X X X X
`1.
`tr
`trip X X
`2 X X X X
`2
`tr
`top m ninp
`
`FIG. 2 further illustrates how multiple requests are pri
`oritized and issued to the synchronous DRAMs. Each of the
`units illustrated in FIG. 2 are incorporated into the control
`ler. For example, a command update unit 210, a bank
`qualification unit 220 and a constraint update unit 240 may
`45
`be incorporated into each of the bank data paths 20 and 30
`of FIG. 1 and a bank arbitration unit 230 may be incorpo
`rated into the control block 70. There is one bank arbitration
`unit 230 and a plurality (N) of other command update, bank
`qualification and constraint update units 210, 220 and 240
`50
`where N=the number of banks. The bank qualification unit
`220 qualifies the per bank requests with the current syn
`chronous DRAM status (active or precharged) and ongoing
`scheduling constraints. The bank qualification unit 220
`further interprets memory requests and commands, such as
`load and store, into synchronous DRAM commands, such as
`activate, read, write and precharge. The bankarbitration unit
`230 is connected to the bank qualification unit 220 and
`arbitrates between multiple sources of memory requests.
`The constraint update unit 240 is connected to the bank
`arbitration unit 230 for decoding the decision to synchro
`nous DRAM standard commands while simultaneously
`updating scheduling constraints per each separate bank. The
`command update unit 210 is connected to the constraint
`update unit 240 for updating the per bankmemory requests
`queues and popping the top element off to reveal the next
`request when necessary.
`
`65
`
`55
`
`InTable 1, go represents the existence of a new command
`from the external device, rw represents a read or write
`request where rw-1 indicates a read request and rw-0
`indicates a write request, np represents a new page where the
`transaction is a new page (row) address, pop represents an
`input transaction for popping the stack, pnp represents an
`input transaction for clearing the np bit if set (this allows a
`page activate to clear the np bit without popping the stack),
`and strepresents the number of elements in the stack. Also,
`TOS indicates top of stack and next indicates the next entries
`in the stack.
`In all of the tables, the inputs are on the left of the vertical
`bar and the outputs are to the right. An input of “X” means
`"don't care” and an output of “X” means unspecified.
`Outputs may assume symbolic values representing specific
`numeric values and may also assume the value of an input
`where the name of the input appears in the table.
`The bank qualification unit 220 qualifies the top of the
`stack with constraints of the synchronous DRAM. The
`constraints on the synchronous DRAM may be obtained, for
`example, from the specification sheet of the device used,
`such as from the Micron Semiconductor Specification Sheet
`for MT48LC2M8S1S. The memory requests and commands
`are qualified per each bank of data path. Bank control inputs
`(st), read (tr) and new page (tinp), are combined with bank
`active signals and qualifiers (ok to read, write, activate, and
`precharge) to develop a per bank command request as
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 10
`
`

`

`8
`
`TABLE 3
`
`ON
`
`B
`
`Current
`Bank
`X
`X
`
`Current
`Bank
`1.
`1
`
`5,630,096
`
`7
`illustrated in Table 2 below. The first three inputs of Table 2
`correspond to the first three outputs in Table 1 from the
`command update unit 210. The control inputs indicate that
`there is a request pending (st-0), a read request is pending
`when the read qualifier is active and a new page address is 5
`requested when the new page qualifier is active.
`
`TABLE 2
`BANK QUALIFICATION
`
`TOS
`
`OK to OK to
`Read
`Write
`Bank
`Bank
`
`OK to
`Activate
`Bank
`
`OK to
`Prechg
`Bank
`
`Precharge
`f
`
`B
`
`st
`
`tr
`
`tnp
`
`Active
`
`O
`
`O
`
`0
`
`O
`
`Idle
`
`State
`
`new page
`
`>0 X 1.
`>0 X
`1.
`>0 X 1.
`>0 X
`1.
`write
`
`>0
`>0
`>0
`>0
`read
`
`0
`0
`0
`O
`
`0
`0
`0
`O
`
`O
`O
`1.
`1
`
`O
`
`O
`1.
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`X
`1.
`X
`O
`
`1
`1
`
`X
`X
`O
`O
`>0
`X
`1.
`1.
`0
`>0
`X
`X
`0
`0
`>0
`X
`O
`1.
`0
`1
`>0
`if no command, precharge if active, otherwise idle
`
`O X X
`O X X
`O X X
`O X X
`
`O
`
`1.
`1.
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`1.
`0
`X
`X
`
`1.
`X
`O
`X
`
`X
`O
`X
`
`X
`X
`X
`X
`
`X
`X
`1.
`0
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`X
`1.
`1
`O
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`X
`X
`X
`X
`
`X
`1.
`O
`X
`
`BA1
`Bl
`BP1
`Bl
`
`BA1
`BW1
`B1
`Bl1
`
`BA
`BR1
`B
`B1
`
`B1.
`BP1
`B1
`B1.
`
`In Table 2, OK to Read Bank 0 is a constraint for reading
`from bank 0 which indicates that it is possible to read in this 40
`SDRAM cycle, Write Bank 0 is a constraint for writing to
`bank 0 which indicates that it is possible to write in this
`SDRAM cycle, OK to Activate Bank 0 is a constraint for
`activating bank 0 which indicates that it is possible to
`activate in this SDRAM cycle and Prechg Bank 0 is a
`constraint for precharging bank 0 which indicates that it is
`possible to precharge in this SDRAM cycle.
`
`so
`
`Next, the bank arbitration unit 230 arbitrates between
`commands from different banks so that the throughput is
`maximized. The arbitration is performed after the qualifica-
`o
`tion so that the data slots between the commands are used as 55
`much as possible for memory requests. The arbitration is
`performed between banks and between system conditions
`such as power up, power down, and refresh. Table 3 below
`illustrates that one of the conflicting memory requests or
`commands is selected to maintain throughput based on 60
`previous reads or writes (with read always being picked over
`write) for preventing unused data slots. The first two inputs
`of Table 3 correspond to the outputs from the bank qualifi-
`cation unit 220 in Table 2. In addition, a least recently used 65
`bit (rub) of the current bank is used as a "tie-breaker' for
`choosing a request.
`
`s
`
`Supervisory
`B State B State
`State
`Bank O Bank 1
`S.
`Bw
`BR1
`SI
`BA1
`BR1
`s
`E.
`W.
`X
`SI
`BR1
`BP1
`X
`SI
`BA1
`BW1
`X
`SI
`PE
`BW1
`X
`SI
`BW
`BA1
`:
`s
`Y.
`E.
`O
`X
`SI
`BA1
`BP1
`both banks want to do the same thing so preference is given to
`the least recently used bank
`SI
`BR1
`BR1
`s
`E.
`E.
`SI
`BW1
`BW1
`SI
`BA1
`BA1
`s
`E.
`O
`SE
`BP1
`BP1
`arbitrate control state when one or more banks request idle
`BI
`B1.
`SI
`X
`b
`B1
`SI
`X
`1.
`B1
`SI
`X
`O
`
`O
`1.
`1.
`O
`
`1.
`
`O
`1
`
`O
`i
`1.
`O
`i
`
`BW1
`
`C
`
`C-State
`R1
`R1
`:
`R1
`W1
`W1
`W1.
`y
`A1
`
`R1
`s
`W1
`A1
`
`P1
`
`1.
`R1
`W1
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 11
`
`

`

`9
`
`TABLE 3-continued
`BANKARBTTRATION
`
`5,630,096
`
`10
`1. These two inputs along with the supervisory state have
`three bit wide field widths. The current bank select bit is at
`the input and the next bank select bit at the output and
`C-state represents the arbitrated control state.
`
`B State
`Bank O
`
`B State
`Bank 1
`
`Supervisory
`State
`
`Current
`Bank
`
`Current
`Bank
`
`C-State
`
`5
`
`X
`S
`BA1
`BI1
`X
`SI
`BP1
`BI1
`X
`S.
`BI1
`BR1
`:
`s
`R EX,
`X
`SI
`BI
`BP1
`reset sequence reqeusts, if active, have precedence
`X
`X
`SP
`X
`X
`X
`SRF
`X
`X
`X
`SPD
`X
`X
`X
`SM
`X
`X
`X
`SW
`X
`X
`X
`SL
`X
`
`O
`O
`1.
`
`1.
`
`cb
`cb
`cb
`cb
`cb
`cb
`
`A1
`a
`P1
`The constraint update unit 240 is used to update CO
`R1
`straints. Table 4 below illustrates how constraints are
`y 10 updated in each bankin response to the C-State output from
`P1
`the bank arbitration. The output counter indicates the num
`ber of SDRAM cycles one must wait before a read, write,
`activate or precharge operation can be performed.
`
`P
`RF1
`PD
`M1
`1.
`I1
`
`15
`
`20
`
`In Table 3, B-State Bank 0 represents the bank state of
`bank 0 and B-state Bank 1 represents the bank state of bank
`
`TABLE 4
`
`CONSTRAINT UPDATE
`
`BL
`(Burst Length)
`
`tRCD
`(RJC Delay)
`
`C State
`
`Current Bank
`
`Counter
`
`X
`X
`X
`X
`
`2
`3
`X
`X
`
`Al
`A1
`R1
`W1
`
`1.
`1.
`X
`
`trCD-1
`tRCD-1
`BL-1
`BL-1
`
`tAA
`(CAS
`Latency)
`
`X
`X
`X
`X
`
`BL
`
`X
`X
`X
`X
`
`tRCD
`
`C-State Current Bank
`
`Counter
`
`2
`3
`X
`X
`
`A.
`A1
`R1
`W1
`
`tRCD-1
`tRCD-1
`tAA - BL-1.
`BL-1
`
`X
`X
`
`tRCm1
`(Read Cycle
`Time)
`
`tRRD
`(Row-Row
`Delay)
`
`tRP
`(RAS
`Precharge) C-State Current Bank
`
`OK to
`Read
`
`O
`O
`O
`O
`
`OK to
`Write
`
`O
`O
`O
`O
`
`OK to
`Activate
`
`O
`O
`1.
`O
`1.
`O
`
`OK to
`Precharge
`
`M.
`RF
`P
`P
`A1
`A.
`
`X
`X
`1.
`1.
`O
`O
`
`Counter
`
`tRCn
`tRCm1
`O
`tRP-1
`O
`tRRD-1
`
`C-State Current Bank
`
`Counter
`
`X
`X
`O. ... 1
`>
`X
`X
`
`tWR
`(Write
`Recovery
`Time)
`
`X
`X
`X
`X
`X
`X
`
`tAA
`
`O . . . i.
`0... 1
`>
`X
`
`X
`X
`X
`X
`O . . .
`>1
`
`.
`
`BL
`
`<4
`4
`X
`X
`
`X
`X
`X
`X
`
`R1
`R
`R1
`W
`
`1.
`1.
`1
`
`O
`tAA+ 2
`tAA-BL-3
`WRBL-2
`
`1
`O
`O
`O
`
`Samsung Electronics Co., Ltd.
`Ex. 1060, p. 12
`
`

`

`5,630,096
`
`5
`
`10
`
`15
`
`20
`
`11
`FIGS.3(a)-3(h) illustrate some examples of part configu
`rations supported by the controller. The part configurations
`of FIGS. 3(a), 3(c), 3(e) and 3(g) use 16 Mbit parts to
`support 4MBytes, 2MBytes, 8MBytes and 4MBytes of total
`memory respectively. The part configurations of FIGS. 3(b),
`3(d), 3(f) and 3(h) use 64Mbit parts to support 16 MBytes,
`8 MBytes, 32 MBytes and 16 MBytes of total memory
`respectively. According to JEDEC specifications, the syn
`chronous DRAM has two banks. As a result, the maximum
`number of banks is two times the number of parts used. With
`more banks, a more random stream of data can be handled
`faster. However, as the number of banks used increases, the
`hardware complexity increases due to the larger number of
`decisions which must be made at the same time.
`In FIGS. 3(a)-3(h), a microprocessor 300 is connected to
`synchronous DRAMs for the various configurations. The
`configurations of FIG. 3(a) and 3(b) support two 16 Mbit
`synchronous DRAMs 310 and 312 and two 64 Mbit syn
`chronous DRAMs 314 and 316, respectively. The configu
`rations of FIGS. 3(c) and 3(d) support one 16 Mbit syn
`chronous DRAMs 320 and one 64 Mbit synchronous
`DRAMs 332, respectively. In FIGS. 3(e) and 3(f), configu
`rations of four synchronous DRAMs 330,332,334 and 336
`and four synchronous DRAMs 340, 342, 344 and 346 are
`respectively supported. FIGS. 3(g) and 3(h) support con
`25
`figurations of two synchronous DRAMs 350 and 352 and
`two synchronous DRAMs 354 and 356, respectively.
`FIG. 4(a) illustrates the timing signals to the synchronous
`DRAM over a relatively large time frame. The controller
`clock (the fast clock) and the slower SDRAM clock are
`illustrated for the power up period and subsequent stores and
`loads in addition to signal at the SDRAM pins.
`FIG. 4(b) illustrates an example of the reordering of a
`store request that occurs in the controller before being issued
`in the synchronous DRAM. As illustrated by the controller
`input bus, three writes are to be performed to bank 0 and one
`write is to be performed to bank 1. Also illustrated are the
`scheduled no opera