(12) United States Patent
`Mayega et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7.061214 B2
`Jun. 13, 2006
`
`US007061214B2
`
`(54)
`
`(75)
`
`(73)
`
`(*)
`
`(21)
`(22)
`(65)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`SINGLE INDUCTORDUAL OUTPUT BUCK
`CONVERTER WITH FREQUENCY AND
`TIME VARYING OFFSET CONTROL
`
`Inventors: Valerian Mayega, Dallas, TX (US);
`Jun Chen, Allen, TX (US); James L.
`Krug, Carrollton, TX (US); David W.
`Evans, Allen, TX (US)
`Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 191 days.
`Appl. No.: 10/722,270
`
`Notice:
`
`Filed:
`
`Nov. 25, 2003
`
`Prior Publication Data
`US 2005/O110471 A1
`May 26, 2005
`
`Int. C.
`(2006.01)
`G05F I/577
`U.S. Cl. ...................................................... 323A267
`Field of Classification Search ................ 323/265,
`323/267, 282
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,038.264 A * 8/1991 Steigerwald ............. 363.21.02
`
`
`
`516
`
`saf
`
`6/2000 Li ............................... 307/39
`6,075,295 A
`4/2001 Lenk
`6,222,352 B1
`2/2003 Ivanov
`6,522,110 B1
`2005/0105227 A1* 5/2005 Chen et al. ................... 361/82
`* cited by examiner
`
`Primary Examiner Adolf Berhane
`(74) Attorney, Agent, or Firm J. Dennis Moore; W. James
`Brady, III; Frederick J. Telecky, Jr.
`
`(57)
`
`ABSTRACT
`
`A single-inductor dual-output buck converter and control
`method that facilitates power conversion by converting a
`single DC power source/supply into two separate DC out
`puts, each of which can be configured to provide a selected/
`desired voltage by selection of respective duty cycles. The
`topology of the inverter includes a pair of diodes or Switches
`that can selectively re-circulate inductor current. The con
`verter is generally operated at a fixed frequency with four
`stages of operation. A first and third stage of operation
`provide power to a first and second output, respectively. A
`second and fourth stage of operation re-circulate inductor
`current and can partially recharge a battery type power
`source. The power output for each stage (voltage and
`current) can be selectively obtained by computing and
`employing appropriate time periods for the stages of opera
`tion that correspond to appropriate duty cycles.
`
`23 Claims, 17 Drawing Sheets
`
`NDUCTOR
`
`512 - Ya
`506-A
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 1
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 1 of 17
`
`US 7.061214 B2
`
`Vn
`
`
`
`Vn
`
`V
`
`EISA
`
`M 10
`
`FIG. 1B
`(PRIOR ART)
`
`
`
`12(OFF) A
`
`C Vout
`
`16
`
`FIG. 1C
`(PRIOR ART)
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 2
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 2 of 17
`
`US 7.061214 B2
`
`DODE
`VOLTAGE
`
`SWITCH
`CURRENT
`
`INDUCTOR
`CURRENT
`
`INDUCTOR
`VOLTAGE
`
`DODE
`CURRENT
`
`OUTPUT S- - -12- -
`VOLTAGE
`
`RPPLE
`
`DC
`A-s as
`
`a
`
`FIG. 2
`(PRIOR ART)
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 3
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 3 of 17
`
`US 7.061214 B2
`
`36
`
`12a
`
`DRIVER
`
`14
`
`
`
`FIG. 3
`(PRIOR ART)
`
`
`
`FG. 4
`(PRIOR ART)
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 4
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 4 of 17
`
`US 7.061214 B2
`
`
`
`NDUCTOR
`
`512-ba
`506-A
`S3
`
`FIG. 5
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 5
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 5 Of 17
`
`US 7.061214 B2
`
`e see ee s a
`
`as a na a
`
`a ss is a s s a
`
`e s a s is a sees e - - -s - e
`
`is is a a s -
`
`- - - -
`
`- a - a s
`
`- - - - -
`
`
`
`FIG. 6
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 6
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 6 of 17
`
`US 7.061214 B2
`
`516
`
`S4 f
`
`518
`W
`
`508
`
`R
`SO
`
`510
`
`7
`S1
`
`p1 504
`
`INDUCTOR
`
`VO1
`
`VIN
`
`S3
`
`514-7
`
`S2
`-N-512
`
`VO2
`C2
`
`LOAD2
`
`524
`M
`C1
`
`2
`1. 526
`LOAD1
`
`520 M 522 - V
`
`STAGE 1
`
`W
`
`FIG. 7
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 7
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 7 Of 17
`
`US 7.061214 B2
`
`516
`
`saf
`
`5O2 A
`
`VIN
`
`W
`
`S1
`
`SO
`
`INDUCTOR
`
`p1
`
`VO1
`
`S2
`re- 512
`
`- S3
`514-y
`
`VO2
`C2
`
`LOAD2
`
`524
`M
`C1
`
`y 526
`LOAD1
`
`520 M 522-Y
`
`STAGE 2
`
`W
`
`FIG. 8
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 8
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 8 of 17
`
`US 7.061214 B2
`
`516
`
`saf
`
`518
`W
`
`510
`
`7
`S1
`
`p1 504
`
`INDUCTOR
`
`VO1
`
`508
`
`r
`SO
`
`502 A
`
`T
`
`VIN
`
`S3
`
`514-y
`
`S2
`
`-
`VO2
`C2
`
`G-512
`
`M 524 p1 526
`LOAD2 IC
`LOAD1
`
`52O M 522-Y
`
`STAGE 3
`
`V
`
`FIG. 9
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 9
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 9 Of 17
`
`US 7.061214 B2
`
`
`
`STAGE 4
`
`FIG. 10
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 10
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 10 of 17
`
`US 7.061214 B2
`
`1.O
`
`0.5
`
`O
`O
`
`2.0
`
`1.O
`
`O
`O
`
`Vo
`
`lot
`
`1 OO
`F.G. 11
`
`Vo2
`
`lo2
`
`1OO
`FIG. 12
`
`200
`
`200
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 11
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 11 of 17
`
`US 7.061214 B2
`
`CONTROL SIGNALS
`
`SO
`
`S1
`
`S2
`
`DUTY1
`
`DUTY2
`
`96.0
`
`96.5
`
`97.0
`
`FIG. 13
`
`CONTROL/RAMP
`SIGNALS
`
`
`
`RAMP1
`
`RAMP2
`
`96.O
`
`96.5
`
`97.O
`
`F.G. 14
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 12
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 12 of 17
`
`US 7.061214 B2
`
`INDUCTOR CURRENT
`
`96.O
`
`96.5
`
`97.O
`
`FIG. 15
`
`565
`
`
`
`RAMP AND FEEDBACK
`VOLTAGES
`
`1601
`
`1602
`
`500
`
`96.O
`
`96.5
`
`97.0
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 13
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 13 of 17
`
`US 7.061214 B2
`
`SO
`
`S1
`
`S2
`
`DUTY1
`
`DUTY2
`
`VCLK
`
`VCLKZ
`
`96.O
`
`96.5
`
`97.0
`
`FIG. 17
`
`
`
`900 mA
`
`INDUCTORCURRENT
`
`800 mA
`
`96.O
`
`96.5
`FIG. 18
`
`97.0
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 14
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 14 of 17
`
`US 7.061214 B2
`
`RAMP AND FEEDBACK
`VOLTAGES
`
`96.0
`
`96.5
`
`97.0
`
`FIRST OUTPUT VOLTAGE
`
`
`
`600
`
`550
`
`500
`
`2.0
`
`1.8
`
`1.6
`
`60
`
`1OO
`
`150
`
`170
`
`FIG. 20
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 15
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 15 Of 17
`
`US 7.061214 B2
`
`14
`
`1.2
`
`1.0
`60
`
`2.0
`1.0
`
`O.O
`60
`
`600m
`
`400m
`
`200m
`6O
`
`SECOND OUTPUT
`VOLTAGE
`
`100
`
`150
`
`170
`
`FIRST OUTPUTCURRENT
`
`100
`
`150
`
`170
`
`SECOND OUTPUT
`CURRENT
`
`100
`FIG. 23
`
`150
`
`170
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 16
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 16 of 17
`
`US 7.061214 B2
`
`START
`
`
`
`PROVIDE SINGLE-INDUCTORDUAL-
`OUTPUT CONVERTER
`
`2402
`
`ENTERA FIRST STAGE TO PROVIDE
`POWER TO A FIRST OUTPUT FROMA
`POWER SOURCE
`
`2404
`
`ENTERA SECOND STAGE TO RE-
`CIRCULATE INDUCTORCURRENT
`
`2406
`
`ENTERATHIRD STAGE TO PROVIDE
`POWER TO ASECOND OUTPUT FROM THE - 2408
`POWER SOURCE
`
`ENTERA FOURTH STAGE TO RE-
`CIRCULATE INDUCTOR CURRENT
`
`2410
`
`FIG. 24
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 17
`
`

`

`U.S. Patent
`
`Jun. 13, 2006
`
`Sheet 17 Of 17
`
`US 7.061214 B2
`
`START
`
`
`
`OBTAN POWER SOURCE VOLTAGE AND
`OUTPUT PARAMETERS
`
`2502
`
`COMPUTE AFIRST DUTY CYCLE FROM
`THE OUTPUT PARAMETERS
`
`2504
`
`COMPUTE ASECOND DUTY CYCLE FROM
`THE OUTPUT PARAMETERS
`
`250s
`
`DETERMINE OPERATIONAL TIMES FOR
`STAGES
`
`2508
`
`CONTROL/OPERATE CONVERTER
`ACCORDING TO THE DETERMINED
`OPERATIONAL TIMES
`
`2510
`
`FIG. 25
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 18
`
`

`

`US 7,061214 B2
`
`1.
`SINGLE INDUCTOR DUAL OUTPUT BUCK
`CONVERTER WITH FREQUENCY AND
`TIME VARYING OFFSET CONTROL
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to power conver
`Sion, and more particularly, to systems and methods for
`operating a single inductor dual output buck converter with
`fixed frequency and time varying offset control.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`2
`The base principle of operation in the above buck con
`verter 10 is often utilized in hysteretic dc-dc converters, as
`illustrated in prior art FIG. 3, and designated at reference
`numeral 30. The circuit 30 is similar in various respects to
`the buck converter 10 of FIG. 1A and employs a unity gain
`buffer 32 serially coupled to an analog comparator circuit 34
`having a hysteresis VH. The comparator 34 compares the
`input reference voltage VREF to the circuit output voltage
`VOUT and provides an output signal at node 36, which is a
`function of the comparison and constitutes a generally
`square wave. An exemplary output voltage waveform for the
`circuit 30 is illustrated in FIG. 4.
`The hysteresis VH of the comparator 34 impacts the
`operation of the circuit 30 in the following manner. As the
`output VOUT falls below a voltage VREF-VH, the com
`parator 34 trips and the output thereof at node 36 goes from
`Zero to the supply, ideally, which then is fed to the circuit
`output VOUT (wherein, VOUT is a function of the output of
`the comparator and the duty cycle of the driver). Similarly,
`as VOUT increases to a voltage VOUT+VH, the comparator
`34 again trips and the output thereof at node 36 decreases to
`Zero volts, which is fed to the circuit output VOUT. There
`fore the hysteresis VH of the comparator 34 dictates an
`amount of voltage ripple (2*VH) about the target reference
`voltage VREF, as illustrated in FIG. 4, and, in conjunction
`with the output capacitor dictates a natural frequency of the
`ripple voltage at the output VOUT.
`Single output buck converters work well in applications
`and/or devices that employ a single input voltage. However,
`Some applications and/or devices utilize two power sources.
`For example, a digital signal processor (DSP) generally
`employs two power supplies; one power supply (1.8V) is to
`power an I/O ring and the other (1.2V) is to power a digital
`core. Dual Voltage outputs of the power converter are also
`reported to reduce power dissipation. Two single output
`buck converters can be employed in Such instances, but at a
`relatively high cost in terms of power utilization, area
`utilization, and component costs. Typically, inductors are the
`highest cost component and employing two buck converters
`requires two inductors. Additionally, more Switches are then
`employed, which can result in greater power consumption.
`Single inductor dual output converters are available, but
`have limited output power availability. Conventional control
`algorithms that are used to operate these converters result in
`relatively high peak-to-peak currents that increase output
`Voltage ripple for both outputs and also increase electro
`magnetic interference (EMI) radiation, which reduces their
`suitability for wireless applications. Furthermore, the con
`trol of one output often interferes with the control of a
`second output, particularly at full output load currents. This
`interference is also referred to as cross talk.
`
`SUMMARY OF THE INVENTION
`
`The following presents a simplified Summary in order to
`provide a basic understanding of one or more aspects of the
`invention. This summary is not an extensive overview of the
`invention, and is neither intended to identify key or critical
`elements of the invention, nor to delineate the scope thereof.
`Rather, the primary purpose of the Summary is to present
`Some concepts of the invention in a simplified form as a
`prelude to the more detailed description that is presented
`later.
`The present invention facilitates power conversion by
`providing systems and methods for controlling a single
`inductor dual output buck converter. The present invention
`facilitates sourcing of high output currents, with relative
`
`15
`
`Switching power Supply circuits are utilized in a number
`of different circuit applications. There are three basic switch
`ing power Supply topologies in common use; buck con
`verter, boost converter, and buck boost converter. These
`topologies are generally non-isolated, that is, the input and
`output voltages share a common ground. There are, how
`ever, isolated derivations of these non-isolated topologies.
`The differing topologies refer to how the switches, output
`inductor and output capacitor associated therewith are inter
`connected. Each topology has unique properties that include
`the steady-state Voltage conversion ratios, the nature of the
`input and output currents, and the character of the output
`Voltage ripple. Another property is the frequency response of
`the duty cycle-to-output voltage transfer function.
`A single output buck converter topology is also referred to
`as a buck converter, buck power stage or a step-down power
`stage (because the output is always less than the input). The
`input current for a buck power stage is said to be discon
`tinuous or pulsating if a Switching current pulses from Zero
`or some negative value to Some positive output current value
`every switching cycle. The output current for a buck power
`stage is said to be continuous or non-pulsating because the
`output current is Supplied by an output inductor/capacitor
`combination. In the latter event, the inductor current never
`reaches a Zero or negative value.
`An exemplary basic buck converter circuit is illustrated in
`prior art FIG. 1A, and designated at reference numeral 10.
`When a power switch 12 is activated, the switch behaves
`like a closed circuit, as illustrated in prior art FIG. 1B, and
`the input voltage VIN is applied to an inductor 14, and
`power is delivered to an output load 16. The output load
`voltage is VOUT=VIN-VL, wherein the VL, the voltage
`across the inductor 14, is given by L(di/dt). The output
`voltage VOUT also is formed across a capacitor 18, thus the
`capacitor charges and the output Voltage increases each time
`the switch 12 is closed.
`When the Switch 12 is deactivated, or turned off, the
`Switch 12 behaves as an open circuit, as illustrated in prior
`art FIG. 1C, and the voltage across the inductor 14 reverses
`due to inductive flyback, thus making a circuit diode 20
`forward biased. The circuit loop generated by the diode 20
`allows the energy stored in the inductor 14 to be delivered
`to the output load 16, wherein the output current is smoothed
`by the capacitor 18. Typical waveforms for a buck converter
`are shown in FIG. 2. The power switch 12 is switched at a
`relatively high frequency (e.g., between about 20 KHZ and
`about 300 KHZ for most converters) to produce a chopped
`output voltage, however, the inductor 14 and capacitor 18
`together operate as an LC filter to produce a relatively
`Smooth output Voltage having a DC component with a small
`ripple Voltage overlying the DC value (see, e.g., output
`voltage waveform of FIG. 2). The ripple voltage can be
`controlled by varying the duty cycle of the power switch
`control Voltage.
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 19
`
`

`

`US 7,061214 B2
`
`3
`peak-to-peak currents being Small as a result of a continuous
`mode of operation. Additionally, the present invention pro
`vides a “current on demand” feature. The systems and
`methods mitigate cross talk and employ battery current
`recirculation thereby reducing energy consumption and
`improving efficiency. The present invention employs an
`OFFSET ramp generation scheme that allows each output to
`have complete un-truncated duty cycles when both outputs
`are at full load.
`The present invention includes a single inductor dual
`output buck converter that can re-circulate current during
`non-power providing periods. The topology of the inverter
`includes a pair of diodes or switches that selectively re
`circulate inductor current. The converter is generally oper
`ated at a fixed frequency with four stages of operation. A first
`and third stage of operation provide power to a first and
`second output, respectively. A second and fourth stage of
`operation re-circulate inductor current and can partially
`recharge a battery type power source. The power output for
`each stage (voltage and current) can be selectively obtained
`by computing and employing appropriate time periods for
`the stages of operation that correspond to appropriate duty
`cycles.
`To the accomplishment of the foregoing and related ends,
`the invention comprises the features hereinafter fully
`described and particularly pointed out in the claims. The
`following description and the annexed drawings set forth in
`detail certain illustrative aspects and implementations of the
`invention. These are indicative, however, of but a few of the
`various ways in which the principles of the invention may be
`employed. Other objects, advantages and novel features of
`the invention will become apparent from the following
`detailed description of the invention when considered in
`conjunction with the drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`15
`
`25
`
`30
`
`35
`
`4
`FIG. 11 is a graph illustrating a first output of the buck
`converter in accordance with an aspect of the present inven
`tion.
`FIG. 12 is a graph illustrating a second output of the buck
`converter in accordance with an aspect of the present inven
`tion.
`FIG. 13 is a graph illustrating exemplary control signals
`and duty cycles in accordance with an aspect of the present
`invention.
`FIG. 14 is a graph illustrating two exemplary ramp signals
`that can be employed in accordance with an aspect of the
`present invention.
`FIG. 15 is a graph illustrating exemplary inductor current
`obtained during operation of the converter in accordance
`with an aspect of the present invention.
`FIG. 16 is a graph illustrating Superimposed ramp signals
`and feedback voltages of the converter in accordance with
`an aspect of the present invention.
`FIG. 17 is a graph illustrating exemplary control signals
`and duty cycles for the buck converter of the second
`simulation in accordance with an aspect of the present
`invention.
`FIG. 18 is a graph illustrating exemplary inductor current
`obtained during operation of the converter in accordance
`with an aspect of the present invention.
`FIG. 19 is a graph illustrating Superimposed ramp signals
`and feedback voltages of the converter in accordance with
`an aspect of the present invention.
`FIG. 20 is a graph illustrating simulated voltage output for
`a first output of the single inductor dual output buck con
`verter in accordance with an aspect of the present invention.
`FIG. 21 is a graph illustrating simulated output for a
`second output of the single inductor dual output buck
`converter in accordance with an aspect of the present inven
`tion.
`FIG. 22 is a graph illustrating simulated current output for
`the first output of the single inductor dual output buck
`converter in accordance with an aspect of the present inven
`tion.
`FIG. 23 is another graph illustrating simulated current
`output for the second output of the single inductor dual
`output buck converter in accordance with an aspect of the
`present invention.
`FIG. 24 is a flow diagram illustrating a method of
`operating a single-inductor dual-output buck converter in
`accordance with an aspect of the present invention.
`FIG. 25 is a flow diagram illustrating a method of
`operating a single-inductor dual-output buck converter in
`accordance with an aspect of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The present invention will now be described with respect
`to the accompanying drawings in which like numbered
`elements represent like parts. The figures provided herewith
`and the accompanying description of the figures are merely
`provided for illustrative purposes. One of ordinary skill in
`the art should realize, based on the instant description, other
`implementations and methods for fabricating the devices
`and structures illustrated in the figures and in the following
`description.
`The present invention facilitates power conversion by
`providing systems and methods for controlling a single
`inductor dual output buck converter. The present invention
`facilitates sourcing of high output currents, with relative
`peak-to-peak currents being Small as a result of a continuous
`
`45
`
`FIG. 1A is a schematic diagram illustrating an exemplary
`basic buck converter.
`FIG. 1B is a schematic diagram illustrating operation of
`40
`the exemplary buck converter.
`FIG. 1C is a schematic diagram further illustrating opera
`tion of the exemplary buck converter.
`FIG. 2 is a graph illustrating typical waveforms for the
`exemplary buck converter.
`FIG. 3 is a diagram illustrating base operation of the
`exemplary buck converter.
`FIG. 4 is a graph illustrating an exemplary output Voltage
`waveform.
`FIG. 5 is a schematic diagram illustrating a single induc
`tor dual output buck converter in accordance with an aspect
`of the present invention.
`FIG. 6 is a graph illustrating two exemplary ramp signals
`that can be employed in accordance with an aspect of the
`present invention.
`FIG. 7 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a first stage of operation in accordance
`with an aspect of the present invention.
`FIG. 8 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a second stage of operation in
`accordance with an aspect of the present invention.
`FIG. 9 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a third stage of operation in accor
`dance with an aspect of the present invention.
`FIG. 10 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a fourth stage of operation in
`accordance with an aspect of the present invention.
`
`50
`
`55
`
`60
`
`65
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 20
`
`

`

`5
`mode of operation. Additionally, the present invention pro
`vides a “current on demand” feature. The systems and
`methods mitigate cross talk and employ battery current
`re-circulation thereby reducing energy consumption and
`improving efficiency. The present invention employs an
`OFFSET ramp generation scheme that allows each output to
`have complete un-truncated duty cycles when both outputs
`are at full load.
`The present invention includes a single inductor dual
`output buck converter that can re-circulate current during
`non-power providing periods. The topology of the inverter
`includes a pair of diodes or switches that selectively re
`circulate inductor current. The converter is generally oper
`ated at a fixed frequency with four stages of operation. A first
`and third stage of operation provide power to a first and
`second output, respectively. A second and fourth stage of
`operation re-circulate inductor current and can partially
`recharge a battery type power source. The power output for
`each stage (voltage and current) can be selectively obtained
`by computing and employing appropriate time periods for
`the stages of operation that correspond to appropriate duty
`cycles.
`Switch mode buck converters have become popular due to
`two attractive features: first, they are more efficient than
`traditional low drop out regulators (LDO) (e.g., up to 95%)
`and second, they can provide relatively high currents with
`lower power dissipation on chip than an LDO can. However,
`buck converters can have relatively costly components,
`which can include an inductor, capacitor, and/or a Schottky
`diode.
`As the demand for integration and system on chip (SOC)
`solutions increase, the exploration of power management
`integrations in deep sub-micron becomes useful. The SOC
`Solutions usually require more than one power source/supply
`operating at different Voltages. In wireless cell phone plat
`forms, where battery life is important, Voltage regulators are
`desired to be relatively efficient. However, the SOC solu
`tions, being cost sensitive, cannot afford the cost of extra
`external components for multiple Switching power Supplies
`(the most expensive component being an inductor).
`Beginning with FIG. 5, a schematic diagram of a single
`inductor dual output buck converter in accordance with an
`aspect of the present invention is provided. The converter is
`operable to controllably provide multiple output voltages
`from a single input power source. Desired output voltage
`levels can be obtained by selection of component parameters
`and control and operation of the converter during use.
`The converter, during operation, receives an input power
`source/supply 502 (VIN) and provides a first output 504
`(VO1) and a second output 506 (VO2). The converter
`includes a single inductor 518 and five controllable
`switches, a first switch 508 (S0), a second switch 510 (S1),
`a third switch 512 (S2), a fourth switch 514 (S3), and a fifth
`switch 516 (S4). The fourth switch 514 and the fifth switch
`516 are employed for re-circulation purposes and can be
`replaced with diodes in alternate aspects of the present
`invention. The first output 504 includes a first capacitor 524
`and a first load 526, in parallel, and the second output 506
`includes a second capacitor 520 and a second load 522, also
`in parallel.
`The converter employs synchronous rectification in order
`to improve efficiency. Additionally, current re-circulation is
`applied to the power source 502 instead of one or both of the
`outputs 504 and 506, which can reduce cross talk from
`memory current remaining in the inductor 518 from a
`previous stage. Additionally, if output current requirements
`of both outputs 504 and 506 are satisfied, the current remains
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 7,061214 B2
`
`10
`
`15
`
`6
`in battery re-circulation mode and the energy of the inductor
`can be provided to power Support circuitry.
`The first switch 508 controllably connects a positive
`terminal of the power source 502 to the inductor 518 (a first
`terminal of the inductor 518). The second switch 510
`controllably connects a second terminal of the inductor 518
`to the first output 504 and the third switch 512 controllably
`connects the second terminal of the inductor 518 to the
`second output 506. The fourth switch 514 controllably
`connects the first terminal of the inductor 518 to ground and
`the fifth switch 516 controllably connects the second termi
`nal of the inductor 518 to the positive terminal of the power
`Source 502.
`The converter is controlled by using two ramp signals and
`by offsetting the signals by a predetermined and calculated
`factor, which with the feedback signals of the respective
`outputs operates the converter in four stages of operation.
`FIG. 6 is a graph illustrating two exemplary ramp signals
`that can be employed in accordance with an aspect of the
`present invention. A first ramp (RAMP1) signal 601 is the
`cycle which when positive, power is Supplied to the second
`output 506, and a second ramp signal (RAMP2) 602 is the
`cycle in which when positive power is supplied to the first
`output 504. The ramp signals 601 and 602 are generated by
`signal generators (not shown) and provided to comparators
`along with respective feedback signals of VOUT1 and
`VOUT2 that drive logic and a driver that operates the
`switches of the converter. Generally, when the first ramp
`signal is positive 603, the switches are controlled and/or
`configured to operate the converter in third and fourth stages
`of operation according to time periods T3 and T4, respec
`tively. Similarly, when the second ramp signal is positive
`604, the switches are controlled and/or configured to operate
`in first and second stages of operation according to time
`periods T1 and T2, respectively. The four stages of operation
`are described below with respect to FIGS. 7, 8, 9, and 10.
`FIG. 7 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a first stage of operation in accordance
`with an aspect of the present invention. In this stage, the first
`Switch 508 and the Second Switch 510 are turned ON and the
`third switch 512 is turned OFF. The re-circulation switches
`(514 and 516) are also turned OFF for this stage. Accord
`ingly, the power source 502 supplies power/current that
`flows through the inductor 518 and charges the first capaci
`tor 524 and supplies power to the first load 526. This
`operation corresponds to the converter working in the top
`half 603 of the first ramp 601. A duty cycle or operation time
`for this stage in this example is less than 50% and the first
`output 504 is turned ON during this stage but is turned OFF
`at the end of the positive portion of the first ramp 601.
`However, it is appreciated that the duty cycle can be adjusted
`to have other suitable values, described infra, and still be in
`accordance with the present invention. The converter
`remains in this stage until output power requirements for the
`first load 526 are attained.
`Continuing with FIG. 8, another schematic diagram illus
`trating the buck converter of FIG. 5 in a second stage of
`operation in accordance with an aspect of the present
`invention is provided. The second stage is entered from the
`first stage. In the second stage, the first 508, the second 510,
`and the third 512 Switches are turned OFF and the fourth 514
`and the fifth 516 Switches are turned ON. The fourth 514 and
`fifth 516 switches being ON permit inductor current and/or
`ground current to re-circulate to the power source 502 (e.g.,
`a battery), which can, in some instances, store this power
`and thus conserve overall power consumption.
`
`Samsung Electronics Co., Ltd.
`Ex. 1059, p. 21
`
`

`

`US 7,061214 B2
`
`8
`The following discussion provides a derivation of the duty
`cycle equations for the converter of FIG. 5. Vin is the power
`source 502, V is the voltage on the first output 504, and
`V is the voltage on the second output 506 of FIG. 5. V,is
`the diode forward voltage, which is the voltage across the
`fifth switch 516. “T” is the converter operating period or
`complete cycle and t, t, t, and t are the times the
`converter operates in the first, second, third, and fourth
`stages, respectively, as described Supra.
`(Vin–Vol)ti-(Vin+2W)t+(Vo2-Vin)ts+(Vin+2V)t.
`
`Eq. 1
`
`7
`FIG. 9 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a third stage of operation in accor
`dance with an aspect of the present invention. The third stage
`is entered from the second stage. For the third stage, the first
`Switch 508 and the third Switch 512 are turned ON and the
`second switch 510, the fourth switch 514, and the fifth
`switch 516 are turned OFF. As a result, the power source 502
`provides power/current through the first switch 508, the
`inductor 518, and the third switch 512 to the second output
`506, thereby charging the second capacitor 520 and provid
`ing power to the second load 522. The power provided from
`the power source 502 can be mitigated if excess current
`remains in the inductor 518 from the previous stages. The
`converter remains in this stage until output power require
`ments for the second load 522 are met.
`FIG. 10 is a schematic diagram illustrating the buck
`converter of FIG. 5 in a fourth stage of operation in
`accordance with an aspect of the present invention. The
`fourth stage is entered from the third stage and is Substan
`tially similar in operation to the second stage. In the fourth
`stage of operation, the first 508, the second 510, and the third
`512 Switches are turned OFF and the fourth 514 and the fifth
`516 switches are turned ON. As with the second stage, the
`fourth 514 and fifth 516 switches being ON permit inductor
`current and/or ground current to re-circulate to the power
`Source 502 (e.g., a battery), which can, in Some instances,
`store this power and thus conserve overall power consump
`tion. The converter can continue to the first stage if contin
`ued operation is desired.
`A complete cycle for the converter is a single pass through
`the four stages of operation described above. The duty cycle
`for the first output 504 is defined as the ON time of Stage 1,
`or percentage of the complete cycle spent in the first and
`second stages of operation. Likewise, the duty cycle for the
`second output 506 is defined as the ON time of Stage 3, or
`percentage of the complete cycle spent in the third and
`fourth stages of operation. The exemplary ramp signals
`illustrated in FIG. 6 depict duty cycles of about 50% for both
`the first output 504 and the second output 506. However, the
`duty cycles can vary to provide power requirements. For
`example, if the second output has relatively low or no power
`requirements, its duty cycle can be relatively small or Zero
`and the first outputs duty cycle can be relatively large (e.g.,
`greater than 50%). Furthermore, the second and fourth
`stages of operation permit inductor current to re-circulate
`during non-duty cycle periods. A controller (not shown) can
`control the switches and thereby, the duty cycles to provide
`or meet the power requirements. Additionally, the controller
`can dynamically modify the duty cycles to meet changing
`power requirements. For example, the controller can cause
`the converter to only provide power to the first output for a
`period of time and then later provide controlled power to
`both outputs.
`The control described above permits each duty cycle to be
`calculated and p