United States Patent (19)
`Herdt et al.
`
`US005563839A
`Patent Number:
`11
`45) Date of Patent:
`
`5,563,839
`Oct. 8, 1996
`
`(54 SEMICONDUCTOR MEMORY DEVICE
`HAVING ASLEEP MODE
`
`5,262,998 11/1993 Mnich et al. ........................... 36.5/227
`5,345,424 6/1994 Landgraf ................................. 36.5/227
`
`75 Inventors: Christian E. Herdt, Monument; Albert
`S. Weiner, Colorado Springs, both of
`Colo.
`(73) Assignee: Simtek Corporation, Colorado Springs,
`Colo.
`21 Appl. No.: 413,360
`22 Filed:
`Mar. 30, 1995
`(51
`int. Cl. ........................................... CC 7700
`52) U.S. Cl
`36.5/227: 365/229
`58 Field of search a
`365f226, 227
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`56)
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`References Cited
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`U.S. PATENT DOCUMENTS
`4,758,945 7/1988 Remedi
`498421 1/1991 Tan.
`5,121,359 6/1992 Steele.
`
`364/200
`36.5/229
`
`OTHER PUBLICATIONS
`Simtek Data Book, Mar. 7, 1994, pp. 1-14.
`Primary Examiner Tan T. Nguyen
`Attorney, Agent, or Firm-Sheridan Ross & McIntosh
`57
`ABSTRACT
`The present invention provides a computer memory device
`having a sleep mode characterized by extremely low current
`consumption and relatively large turn on delay. The inven
`tion includes circuitry for disabling current sinking elements
`internal to said device in response to a sleep signal. In one
`embodiment, the invention includes circuitry for disconnect
`random access memory (nvSRAM) array from a source of
`power in response to a sleep signal. This embodiment is
`capable of first transferring the data stored in a volatile
`portion of the array to a nonvolatile portion of the array
`before entering sleep mode to prevent loss of the data.
`
`ing the bit lines and memory cell loads of a nonvolatile static
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`30 Claims, 4 Drawing Sheets
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 1
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`U.S. Patent
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`Oct. 8, 1996
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`Sheet 1 of 4
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`5,563,839
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 2
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`U.S. Patent
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`Oct. 8, 1996
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`Sheet 2 of 4
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`5,563,839
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 3
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`U.S. Patent
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`Oct. 8, 1996
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`Sheet 3 of 4
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`5,563,839
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`|TTTTTTTTTT??????
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 4
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`U.S. Patent
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`Oct. 8, 1996
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`Sheet 4 of 4
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`5,563,839
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 5
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`

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`5,563,839
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`1
`SEMCONDUCTOR MEMORY DEVICE
`HAVING ASLEEP MODE
`
`FIELD OF THE INVENTION
`The present invention relates generally to computer
`memory devices, and, more particularly, to computer
`memory devices having a low current sleep mode.
`
`2
`mode known as the standby mode. This current drain tends
`to deplete the computer's battery and results in significantly
`less operating time between recharges.
`Therefore, a need exists for an invSRAM device that is
`capable of conserving more power than nvSRAMs with
`standby current reduction.
`
`SUMMARY OF THE INVENTION
`The invention is concerned with a computer memory
`device having a low current operating mode, called a sleep
`mode. This mode is achieved by disabling, or turning off,
`current sinking elements internal to the memory device in
`response to a sleep signal. Among the current sinking
`elements disabled are elements that require more time to
`reach an operational state after power is applied to the
`memory than the normal address access time of the memory.
`By disabling these elements, the invention is capable of
`reducing the current consumed by the memory to levels that
`make the device particularly useful in those applications
`which require reduced power consumption.
`In the preferred embodiment, the invention includes a
`nonvolatile static random access memory (nvSRAM) cell
`having both a static random access memory (SRAM) portion
`and a nonvolatile portion. Both portions are capable of
`retaining a digital data bit delivered to them, but the SRAM
`portion will lose its retained data bit if power to the cell is
`removed while the nonvolatile portion will not lose its
`retained data bit if power to the cell is removed. The
`nvSRAM cell is capable of transferring a bit of data from the
`SRAM portion to the nonvolatile portion in response to a
`store signal and transferring a bit of data from the nonvola
`tile portion to the SRAM portion in response to a recall
`signal.
`The nvSRAM cell of the preferred embodiment has at
`least one memory cell load operatively connected thereto for
`facilitating the delivery of power to the cell. This memory
`cell load sinks current whenever a voltage is applied to it. To
`avoid this current sinking, the invention is capable of
`disconnecting the load from a source of power in response
`to a sleep signal. Because the data retained within the SRAM
`portion of the nvSRAM cell will be lost when the voltage is
`removed from the memory cell load, the preferred embodi
`ment of the invention allows a user to deliver a store signal
`to the cell before entering the sleep mode. This causes a
`transfer of the data from the SRAM portion to the nonvola
`tile portion, thereby protecting the data from loss. In an
`alternative embodiment, the invention automatically deliv
`ers a store signal to the nvSRAM cell whenever sleep mode
`is entered.
`The nvSRAM cell of the preferred embodiment also has
`at least one bit line operatively connected thereto for pro
`viding a pathway for data between the cell and the exterior
`environment. Any time a voltage is present on this bit line,
`a semiconductor junction will be reverse biased and a small
`leakage current to an underlying substrate will result. The
`invention is capable of disconnecting the bit line from a
`source of power in response to a sleep signal. In a preferred
`embodiment, the invention is capable of holding the bit line
`at the same voltage level as the underlying substrate in
`response to a sleep signal.
`The preferred embodiment of the invention also includes
`power monitoring circuitry for monitoring the power being
`supplied to the device. The power monitoring circuitry is
`capable of creating a store signal when there is a loss of
`power being supplied to the device and a recall signal when
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`BACKGROUND OF THE INVENTION
`A computer memory is a storage device that receives,
`retains and transmits digital information in a computer.
`Computer memories come in many different types which
`vary according to how long they can store data, how fast
`they are able to receive and transmit data, and how much
`they cost, among other things. The present invention is
`applicable to many different types of computer memory,
`such as read only memory (ROM) and random access
`memory (RAM), but in the preferred embodiment the inven
`tion concerns a subset of RAM known as static random
`access memory (SRAM).
`A random access memory is generally comprised of an
`array of data storage locations, known as memory cells,
`where individual data elements, known as bits, can be
`retained. Each data storage location is addressable so that
`data from the exterior environment can be written into the
`data storage location, or data can be read from the data
`storage location and provided to the exterior environment.
`The time it takes to access the data in any particular storage
`location, i.e., at a particular address, is substantially inde
`pendent of the particular address of that location, hence the
`name random access memory.
`The word “static' in static random access memory refers
`to the ability of the memory to retain data without having to
`constantly refresh or re-write the memory cells. The oppo
`site of this is a "dynamic' random access memory which
`requires constant refreshing of the memory cells to maintain
`the data contained therein.
`An important characteristic of any computer memory
`device is whether the device is volatile or nonvolatile. A
`volatile memory device, such as an SRAM, will lose all of
`its stored data if the power being supplied to the device is
`terminated. A nonvolatile memory, in contrast, will retain its
`data even if power is removed. In general, nonvolatile
`memory devices operate much slower than volatile devices
`performing the same functions, and, therefore, are not gen
`erally used in applications requiring both fast read and write
`operations.
`Memory devices exist which combine a faster volatile
`memory portion with a slower nonvolatile memory portion
`to obtain the benefits of both types of memory. These
`devices use the volatile memory portion during high speed
`operation and transfer the data stored in the volatile portion
`to the nonvolatile portion if there is concern that power to
`the nonvolatile portion will be lost. The data so transferred
`can later be recalled to the volatile portion when needed.
`Devices having these characteristics are generally called
`nonvolatile static random access memories (nvSRAMs).
`60
`Nonvolatile SRAMs have wide applicability in the com
`puter industry and may be used in many different computer
`based products. Such memories may be used, for example,
`in portable laptop computers or other portable computer
`products. A problem which arises when these memories are
`used in portable computers is the sizable current drain that
`they create even when not in use or in a current reduction
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 6
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`5,563,839
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`3
`the power being supplied to the device is restored. The
`invention provides circuitry for deactivating, in response to
`a sleep signal, many of the current sinking elements internal
`to the power monitoring circuitry.
`Lastly, the preferred embodiment of the present invention
`includes at least one input buffer for buffering signals being
`transmitted into the nvSRAM device. The input buffer is
`known to sink current whenever the input signal being
`applied to it is at an intermediate level between power
`supply and ground. The invention provides circuitry for
`disabling the input buffers in response to a sleep signal.
`Based on the foregoing, the present invention is capable
`of significantly reducing the power consumed by the nvS
`RAM device whenever a sleep signal is supplied to the
`device from an external source.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic diagram of the present invention.
`FIG. 2 is a schematic diagram of a first portion of the
`embodiment of the invention illustrated in FIG. 1, including
`memory cells having memory cell loads and bit lines.
`FIG. 3 is a schematic diagram of a second portion of the
`embodiment of the invention illustrated in FIG. 1, including
`circuitry for initiating an automatic store operation in
`response to a loss of system power and an automatic recall
`operation in response to a restoration of said power.
`FIG. 4 is a schematic diagram of a third portion of the
`embodiment of the invention illustrated in FIG. 1, including
`input buffers for buffering data transmitted into the memory
`device.
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`the array 12 to be transferred to the SRAM portion of the
`array 12 when the power being provided to the device 10
`transitions from an inappropriate level for SRAM operation
`to an acceptable level for SRAM operation. The device 10
`further includes input buffers 20 for use in transferring data
`from the exterior environment to the device 10.
`To interface the device 10 with the exterior environment,
`the device includes a plurality of inputs. Specifically, the
`device 10 includes a power input 22 for providing power
`from a power supply 24 to the device 10. Backup power
`input 26 provides power from an external capacitor 28 that
`can be used, in the event the power supply 24 fails, to
`accomplish a store operation. A store input 30 permits a user
`to force astore operation to occur in the array12. The device
`also includes input pads 32 to facilitate the transfer of data,
`including clocks, addresses, and user input data, from the
`exterior environment to the input buffers 20. Asleep input 34
`is provided to permit a user to place the device in the sleep
`mode of operation by asserting a sleep signal.
`With the foregoing general description of the device 10 in
`mind, it has been recognized that the array 12, power
`monitoring circuitry 18 and input buffers 20 each include
`circuitry that, during operation of the device 10, utilizes
`current to a degree that is undesirable in a number of
`applications. The device 10 includes circuitry that, in
`response to the sleep signal, reduces this undesirable current
`consumption by disabling circuitry in the noted portions of
`the device 10 that are consuming current. However, before
`describing the circuitry that disables the current consuming
`circuitry, the components and operation of the array 12,
`power monitoring circuitry 18 and input buffers 20 will be
`described as well as the components therein that are disabled
`in response to the sleep signal.
`As previously discussed, the array 12 includes a plurality
`of the cell 14. With reference to FIG. 2, each cell 14 includes
`a volatile static random access memory (SRAM) portion 38
`that is capable of receiving a bit of data from an exterior
`environment, retaining this bit of data and transmitting this
`bit of data bit back to the exterior environment. The transfer
`of a bit of data between the SRAM portion 38 and the
`exterior environment is accomplished using bit lines 40. The
`loads 44 are operative for supplying power to the SRAM
`portion 38 which, in turn, is operative for driving the bit
`lines 40. Due to its volatile characteristic, the SRAM portion
`38 will lose the retained bit of data whenever power is
`removed therefrom. The bit lines 40 and loads 44 are both
`significant current sinks that have time constants appreciably
`greater than the normal address access time of the device 10
`and which are disabled during sleep mode.
`Each cell 14 also includes a nonvolatile portion 46 that is
`connected to the SRAM portion 38 so that the data retained
`within the SRAM portion can be transferred to the nonvola
`tile portion 46 in response to a store signal that initiates a
`store cycle. Similarly, the data stored within the nonvolatile
`portion 46 can be transferred back to the SRAM portion 38
`in response to a recall signal that initiates a recall cycle.
`FIG. 3 illustrates the power monitoring circuitry 18 for
`monitoring the status of power that is being supplied to
`device 10. The power monitoring circuitry 18 is capable of
`initiating a store cycle whenever a loss of system power is
`detected and a recall cycle whenever a restoration of system
`power is detected after a loss of power has occurred. As
`shown in FIG. 3, the circuitry 18 is separated into a power
`down monitoring circuitry 50 for determining when there
`has been a loss of power that prevents reliable operation of
`the SRAM portion 38 of the cells 14 in the array 12 and
`
`DETAILED DESCRIPTION
`The invention is concerned with a computer memory
`device having a low current operating mode, called a sleep
`mode. This mode is achieved by disabling, or turning off,
`current sinking elements internal to the memory device in
`response to a sleep signal. Among the current sinking
`elements disabled are elements that require more time to
`reach an operational stated after power is applied to the
`memory, than the normal address access time of the memory.
`By disabling these elements, the invention is capable of
`reducing the current consumed by the memory to levels
`below those achieved by the prior art standby mode and is
`particularly useful in those situations when immediate
`access to the memory cells is not critical.
`FIG. 1 illustrates an embodiment of the invention and,
`more specifically, an invSRAM device with sleep mode
`capability, which is hereinafter referred to as device 10. For
`ease of description and to enhance understanding, FIG. 1 is
`broken down into three separate portions in FIGS. 2, 3, and
`4.
`As seen in FIGS. 1-4, device 10 includes nonvolatile
`static random access memory (nvSRAM) array 12 with one
`nvSRAM memory cell 14 thereof illustrated. To control the
`application of power to the array, among other things, the
`device includes a memory array control 16. The device 10
`further includes power monitoring circuitry 18 that operates
`so that if the power being provided to the device 10 is
`inadequate for retaining data in the SRAM portion of the
`array 12, a store operation is initiated that causes the data in
`the SRAM portion of the array 12 to be transferred to the
`nonvolatile portion of the array 12. In addition, the power
`monitoring circuitry 18 can initiate a recall operation that
`causes data previously stored in the nonvolatile portion of
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`Ex. 1056, p. 7
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`generating a store signal indicative thereof that causes data
`retained in the SRAM portion to be transferred to the
`nonvolatile portion using capacitor backup power; an iso
`lation switch circuitry 52 that disconnects the device 10
`from the power supply 24 in response to the signal produced
`by the power down monitoring circuitry 50 and connects the
`device 10 to the power supply 24 in response to a restoration
`of power; and power up monitoring circuitry 54 for deter
`mining when adequate power is present for SRAM opera
`tions and generating a signal indicative thereof that is used
`to initiate a recall operation. All three of these sub-circuits
`include current sinking elements which are disabled during
`sleep mode and which have time constants appreciably
`greater than the normal address access time of the device 10.
`As illustrated in FIG. 3, isolation switch circuitry 52
`includes a relatively large n-channel MOSFET 56 opera
`tively connected between power supply 24 and external
`capacitor 28 for connecting and disconnecting device 10
`from power supply 24. An n-channel MOSFET is used to
`avoid the occurrence of a destructive condition known as
`latch-up when powering up device 10. During normal opera
`tion, the n-channel MOSFET 56 is biased "on' creating a
`relatively low resistance between power supply 24 and
`external capacitor 28. This allows capacitor 28 to charge up
`to substantially the same voltage as power supply 24, which
`in the preferred embodiment is 5 volts.
`With reference to FIG. 3, power down monitoring cir
`cuitry 50 includes reference voltage source 58 and differ
`ential amplifier 60. The negative input terminal of differen
`tial amplifier 60 is operatively connected to external
`capacitor 28 and the positive input terminal is operatively
`connected to the output of reference voltage source 58.
`When enabled, reference voltage source 58 outputs a regu
`lated reference voltage at a level somewhere between Zero
`35
`volts and the voltage level applied at power input 22. When
`disabled, reference voltage source 58 outputs an unregulated
`voltage substantially equal to the voltage applied at power
`input 22. In the preferred embodiment, the voltage level
`applied at power input 22 is 5 volts and the regulated
`reference voltage level is 4.2 volts.
`Differential amplifier 60, when enabled, compares the
`voltage across capacitor 28 to the regulated reference volt
`age and creates an output signal whenever the reference
`voltage is greater. This output signal is indicative of a loss
`of power from power supply 24 and is used by device 10 to
`initiate a store cycle. Reference voltage source 58 and
`differential amplifier 60 are both significant current sinks
`that have time constants appreciably greater than the normal
`address access time of the device 10 and that are disabled
`during sleep mode.
`Isolation switch circuitry 52 monitors the output of power
`down monitoring circuitry 50, and, when a signal is detected
`which indicates a loss of power from the power supply 24,
`compares the voltage of power supply 24 to the voltage
`across external capacitor 28. If the voltage across capacitor
`28 is greater, the isolation switch circuitry 52 isolates device
`10 from power supply 24 by turning of n-channel MOSFET
`56. Device 10 then uses the charge stored in external
`capacitor 28 to complete the store cycle initiated by the
`output signal of power down monitoring circuitry 50.
`Device 10 is isolated from power supply 24 to ensure that
`the charge stored in capacitor 28 is not lost through an
`extraneous path created by the failure of supply 24.
`As illustrated in FIG. 3, isolation switch circuitry 52
`includes n-channel MOSFET 56, switch pump 62, differen
`tial amplifier 64, and logic circuitry 66. Switch pump 62 is
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`operatively connected to the gate terminal of n-channel
`MOSFET 56 for applying an elevated voltage level to its
`gate terminal whenever a relatively low resistance is
`required between power supply 24 and device 10, i.e.,
`whenever adequate power is being delivered to device 10.
`Switch pump 62 is required because the application of a
`logic high signal to the gate of n-channel MOSFET 56,
`rather than the elevated voltage level produced by the switch
`pump 62, results in a voltage drop between power supply 24
`and external capacitor 28 which is undesirable. Differential
`amplifier 64 is operatively connected at its negative input
`terminal to power Supply 24 and at its positive input terminal
`to external capacitor 28 for creating an output signal indica
`tive of whether the capacitor voltage is greater than the
`supply voltage. Differential amplifier 64 is also operatively
`connected at an enable input to the output of power down
`monitoring circuitry 50. Logic circuitry 66 is responsive to
`the output signal of differential amplifier 64 and the output
`signal of power down monitoring circuitry 50 for determin
`ing when n-channel MOSFET 56 should be turned on and
`off and for communicating this information to switch pump
`62.
`After there has been a loss of power and device 10 has
`been isolated from power supply 24, differential amplifier 64
`continues to compare the voltage of power supply 24 to that
`across external capacitor 28. When the power from supply
`24 is restored, differential amplifier 64 outputs a signal
`indicative of this restoration. Logic circuitry 66 detects this
`signal from differential amplifier 64 and signals switch
`pump 62 to turn on n-channel MOSFET 56, thereby recon
`necting power supply 24 to external capacitor 28 and
`charging up the capacitor. The power down monitoring
`circuitry 50 detects that the voltage across capacitor 28 has
`exceeded the regulated reference voltage and produces an
`output signal indicative of such. Differential amplifier 64
`detects this signal from the power down monitoring circuitry
`50 and stops comparing the supply voltage to the capacitor
`voltage. Both switch pump 62 and differential amplifier 64
`are current sinks that have time constants appreciably
`greater than the normal address access time of the device 10
`and that are disabled during sleep mode.
`The power up monitoring circuitry 54 is responsible for
`initiating recall cycles. A recall cycle is generally required
`when power has been restored to device 10 after a power
`down condition or when device 10 has emerged from a sleep
`cycle. To initiate a recall cycle after power has been restored
`to device 10, three conditions must be met. First, power up
`monitoring circuitry 54 must determine whether there is a
`signal present at the output of power down monitoring
`circuitry 50. If a signal is present, this indicates that system
`power has not yet been restored and therefore a recall cycle
`should not be initiated. Power up monitoring circuitry 54
`must also determine whether the voltage across external
`capacitor 28 had dropped a certain predetermined amount
`below the reference voltage of reference voltage source 58
`before power was restored. If the capacitor voltage had not
`dropped below that level, then the data stored within the
`SRAM portion 46 of the memory was not lost and a recall
`cycle is not required. Lastly, power up monitoring circuitry
`54 must determine whether power down monitoring cir
`cuitry 50 is sufficiently stabilized before it may initiate a
`recall cycle.
`To initiate a recall cycle after device 10 has emerged from
`sleep mode, three conditions must be met. First, power up
`monitoring circuitry 54 must determine that device 10 is no
`longer in sleep mode. Second, power up monitoring circuitry
`54 must determine that the regulated reference voltage being
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`Samsung Electronics Co., Ltd.
`Ex. 1056, p. 8
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`

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`7
`output by reference voltage source 58 has sufficiently sta
`bilized. Third, power up monitoring circuitry 54 must deter
`mine that adequate operating power is available.
`In the preferred embodiment, as illustrated in FIG. 3,
`power up monitoring circuitry 54 includes stabilization
`circuitry 68, voltage reset circuitry 70, negative transition
`detection circuitry 72, and logic circuitry 74. Stabilization
`circuitry 68 monitors the output of reference voltage source
`58 to determine whether it has stabilized within a specific
`voltage range. If the voltage has stabilized within the spe
`cific range, stabilization circuitry 68 outputs a signal indica
`tive of such. Voltage reset circuitry 70 monitors the voltage
`across external capacitor 28 and determines whether this
`voltage has dropped a certain amount below the reference
`voltage of reference voltage source 58 before system power
`was restored. If the voltage had dropped the required
`amount, voltage reset circuitry 70 outputs a signal indicative
`of such. Negative transition detection circuitry 72 deter
`mines when device 10 is just leaving a sleep mode and
`outputs a signal indicative of such. Logic circuitry 74 is
`responsive to the output signals of power down monitoring
`circuitry 50, voltage reset circuitry 70, and stabilization
`circuitry 68 for initiating a recall cycle after power has been
`restored to device 10 after a power down condition. Simi
`larly, logic circuitry 74 is responsive to the output signals of
`stabilization circuitry 68 and negative transition detection
`circuitry 72 for initiating a recall cycle after device 10 has
`emerged from sleep mode. Voltage reset circuitry 70 is a
`significant current sink that has a time constant appreciably
`greater than the normal address access time of the device 10
`and is disabled during sleep mode.
`With reference to FIG. 4, device 10 includes one or more
`input buffers 20 for receiving data, such as clock signals,
`addresses, and user input data, from an exterior environment
`and transferring this data to the internal circuitry of device
`10. Input buffers are used by a memory device so that the
`device itself does not influence the circuit which is deliver
`ing data to the device. As seen in the figure, the invention
`uses a NOR gate 76 as an input buffer. NOR gate 76 has a
`first input operatively connected to an input pad 32 for
`receiving data from the exterior environment and an output
`for delivering the data to the internal circuitry of device 10.
`The input buffers 20 are significant current sinks if the input
`signals being applied to them are at an intermediate level
`between power supply and ground and are disabled during
`sleep mode. The input buffers, however, have a time con
`stant within a factor of two of the normal address access time
`of the device 10.
`With the foregoing description of the components and
`operation of the array 12, power monitoring circuitry 18 and
`input buffers 20 in mind, the circuitry that disables, in
`response to a sleep signal, the current consuming compo
`nents of the above portions will be described.
`In the preferred embodiment, as illustrated in FIG. 1,
`device 10 includes an active high sleep signal line 78
`communicating with an exterior environment through sleep
`input 34. This signal line will be logic high when device 10
`is in sleep mode and logic low otherwise. Device 10 also
`includes inverter 80 connected at an input to active high
`sleep signal line 78 for providing an active low sleep signal
`line 82 at an output. Active low sleep signal line 82 will be
`logic low when device 10 is in sleep mode and logic high
`otherwise. The invention uses these two signal lines to
`disable the various current sinking elements when in sleep
`mode.
`Memory loads 44 are known to sink current whenever a
`voltage is applied to them. Device 10 provides circuitry for
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`35
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`40
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`45
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`60
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`5,563,839
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`10
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`8
`removing the voltage from the memory cell loads 44 when
`ever a sleep signal is asserted. In one embodiment, as
`illustrated in FIG. 2, this circuitry comprises logic gate 84 in
`memory array control 16 operatively connected at an output
`to memory loads 44 in memory array 12 and responsive to
`active high sleep signal line 78 connected at an input for
`disconnecting the memory loads 44 from a source of power
`26 whenever a sleep signal is asserted. It should be appre
`ciated that logic gate 84 can include any means for termi
`nating the application of a voltage to the loads 44 in response
`to a sleep signal and is not limited to the specific means
`illustrated in FIG. 2. In another embodiment, the memory
`loads 44 are held at substantially the same voltage as the
`underlying substrate in response to a sleep signal.
`Whenever the voltage being supplied to the memory loads
`44 is terminated, any data stored in the SRAM portion 38 of
`the cell 14 will be lost. To prevent this loss from occurring,
`the preferred embodiment of the present invention allows a
`user to initiate a store cycle, using store input 30, before
`entering sleep mode. In an alternative embodiment, the store
`cycle may be initiated automatically by device 10 whenever
`a sleep signal is asserted on active high sleep signal line 78.
`Bit lines 40 are used by device 10 to carry data bits
`between SRAM portion 38 and the exterior environment.
`When a voltage that is different from the voltage of the
`underlying substrate is present on one of these bit lines, a
`semiconductor junction is reverse biased and a small leakage
`current to the underlying substrate will result. This leakage
`current is generally negligible if only one or a few bit lines
`are involved, but can represent a significant current sink for
`memories having larger arrays. Device 10 provides circuitry
`for significantly reducing the difference between the voltage
`on the bit lines and the voltage on the underlying substrate
`in response to a sleep signal. This effectively eliminates the
`reverse junction leakage current during sleep mode. In one
`embodiment, as illustrated in FIG. 2, the circuitry comprises
`logic gates 86 in memory array control 16 having an output
`operatively connected to the gate terminals of bit line bias
`transistors 42 located within memory array 12. During
`normal operation, the bit line bias transistors 42 are biased
`“ON”, thereby resistively connecting the bit lines 40 to a
`source of power 26. During sleep mode, the bit line bias
`transistors 42 are turned "OFF", thereby isolating the bit
`lines 40 from the source of power 26 and allowing a "zero
`junction bias' condition to develop at the corresponding
`semiconductor junctions. In a preferred embodiment, the bit
`lines 40 are held at the same voltage level as the underlying
`substrate in response to a sleep signal which also creates a
`"zero junction bias' condition at the corresponding semi
`conductor junctions.
`Device 10 provides circuitry for disabling the entire
`power down monitoring circuitry 50 in response to a sleep
`signal. This is accomplished by connecting the active low
`sleep signal line 82 to the enable inputs of both reference
`voltage source 58 and differential amplifier 60. This arrange
`ment causes the application of a logic low signal to the
`enable inputs whenever device 10 is in sleep mode, thereby
`disabling the two current sinking elements.
`Device 10 also includes circuitry for disabling the entire
`isolation switch circuitry 52 in response to a sleep signal. As
`illustrated in FIG. 3, logic circuitry 66 is connected at an
`enable input port to active high