(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2010/0205470 A1
`(43) Pub. Date:
`Aug. 12, 2010
`MOSHAYED et al.
`
`US 20100205470A1
`
`(54) FLASH BACKED DRAM MODULE WITH
`STATE OF HEALTH AND/OR STATUS
`INFORMATION ACCESSIBLE THROUGHA
`CONFIGURATION DATABUS
`
`(75) Inventors:
`
`Mark MOSHAYEDI, Newport
`Coast, CA (US); Douglas Finke,
`Orange, CA (US)
`
`Correspondence Address:
`WILMERHALEABOSTON
`6O STATE STREET
`BOSTON, MA 02109 (US)
`
`(73) Assignee:
`
`STEC, Inc., Santa Ana, CA (US)
`
`(21) Appl. No.:
`
`12/369,052
`
`(22) Filed:
`
`Feb. 11, 2009
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F I/28
`(2006.01)
`GO6F 3/42
`(52) U.S. Cl. ......................................... 713/340; 710/105
`(57)
`ABSTRACT
`A memory device includes: Volatile memory; an interface for
`connecting to a backup power source; non-volatile memory;
`a first configuration data bus for accessing parameters
`describing Substantially permanent characteristics of the
`Volatile memory; a second configuration data bus for access
`ing at least one of state of health information of the backup
`power source and status information of the memory device,
`wherein the first configuration data bus and the second con
`figuration data bus implement a same bus protocol; a control
`ler programmed to detect a loss of power of a primary power
`Source and move data from the Volatile memory to the non
`Volatile memory, wherein configuration information of the
`controller is at least one of readable and writable through the
`first configuration data bus; and wherein at least one of the
`state-of-health information and the status information is at
`least one of readable and writable through the second con
`figuration data bus.
`
`
`
`REG
`
`ORAMARRAY
`
`120
`
`DDR2NTEFACE (
`
`164
`
`FET
`
`MUX -" 110
`
`DR2CK
`
`O FET
`MUX
`
`CLK 161
`PLL
`
`NVCACHENABL
`NVIMMPG
`RESETN
`CACHEDIRTY
`DRAMAVAILABLE
`MVDIMMRADY
`
`150 <
`
`SCSA
`NVDIMSDAVNVDEMSCL
`SA2:0
`
`TST RX
`TEST TX
`
`130
`
`131
`
`WOLATLE
`CONTROL
`
`170<
`
`WBACKSDA
`WBACKSC.
`WBACK RSE
`WBACK
`
`PS
`REG/
`FETS
`SW
`
`171
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 1
`
`

`

`Patent Application Publication
`
`US 2010/0205470 A1
`
`
`
`
`
`
`
`| 914
`
`- X
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 2
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 2 of 9
`
`US 2010/0205470 A1
`
`
`
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`VOJSTXIOVEA
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 3
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 3 of 9
`
`US 2010/0205470 A1
`
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 4
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 4 of 9
`
`US 2010/0205470 A1
`
`
`
`RESET=1
`
`NVDIMMPG=1
`
`. NVCACHE ENABLEEO
`ANDNVDIMMPG=0
`
`NVCACHE ENABLE=1
`ANDNVDIMMPG=0
`
`UNFINISHEDERASE
`
`DIRTY-1
`AND WIPE=0
`
`DIRTY-0 DRIy
`AND WEPE-1
`
`BACKUP
`
`NVCACHELENABLE=0
`ANDNVDIMMPG=1
`NVCACHE ENABLE=1
`ANDNVDIMMPG=0
`
`NVDIMMPG=1
`
`BACKUP
`COMPLETE
`
`FALLING EDGE ON
`NVCACHE ENABLE
`
`COMPLETE
`
`NVCACHELENABLE=0
`ANDNVDIMMPG=1
`AND DIRTY=1
`AND ERASE=1
`
`NVDIMMPG=0
`
`FIG. 4
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 5
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 5 of 9
`
`US 2010/0205470 A1
`
`CURRENT ADDRESS READ
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 6
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 6 of 9
`
`US 2010/0205470 A1
`
`BYTE WRITE
`
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`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 7
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 7 of 9
`
`US 2010/0205470 A1
`
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 8
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 8 of 9
`
`US 2010/0205470 A1
`
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 9
`
`

`

`Patent Application Publication
`
`Aug. 12, 2010 Sheet 9 of 9
`
`US 2010/0205470 A1
`
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`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 10
`
`

`

`US 2010/0205470 A1
`
`Aug. 12, 2010
`
`FLASH BACKED DRAMMODULE WITH
`STATE OF HEALTH AND/OR STATUS
`INFORMATION ACCESSIBLE THROUGHA
`CONFIGURATION DATABUS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`0001. This application is related to U.S. patent application
`Ser. No.
`l, filed Feb. 11, 2009 with Attorney Docket
`Number 2202374-121 US 1 and titled A Staged-Backup Flash
`Backed DRAM Module; U.S. patent application Ser. No.
`l, filed Feb. 11, 2009 with Attorney Docket Number
`2202374-123 US 1 and titled A Segmented-Memory Flash
`Backed DRAM Module; U.S. patent application Ser. No.
`l, filed Feb. 11, 2009 with Attorney Docket Number
`2202374-124 US 1 and titled A State of Health Monitored
`Flash Backed DRAM Module; U.S. patent application Ser.
`No.
`l, filed Feb. 11, 2009 with Attorney Docket Num
`ber 2202374-125 US 1 and titled A Flash Backed DRAM
`Module Storing Parameter Information of the DRAM Mod
`ule in the Flash; U.S. patent application Ser. No.
`l,
`filed Feb. 11, 2009 with Attorney Docket Number 2202374
`127 US 1 and titled A Flash Backed DRAM Module with a
`Selectable Number of Flash Chips; U.S. patent application
`Ser. No.
`l, filed Feb. 11, 2009 with Attorney Docket
`Number 2202374-128 US 1 and titled A Flash Backed DRAM
`Module Including Logic for Isolating the DRAM; and PCT
`Patent Application No.
`, filed Feb. 11, 2009 with
`Attorney Docket Number 2202374-121 WO1 and titled A
`Flash Backed DRAM Module.
`
`TECHNICAL FIELD
`
`0002 The disclosed subject matter relates to a flash
`backed dual in-line memory module (DIMM) module.
`
`BACKGROUND
`0003 Digital processing devices, such as, for example,
`RAID systems sometimes use memory caches, for example,
`to improve performance of read and write operations. Caches
`are often implemented using volatile memory. However, if the
`power source of the volatile memory fails, the data stored in
`the volatile memory can be lost. In addition, a volatile
`memory device, such as a DRAM memory module typically
`requires certain parameters that describe properties of
`DRAM devices making up the module to be placed in a
`separate non-volatile memory located on the memory mod
`ule. One example of this is Serial Presence Detect (SPD).
`However, the storing of this information can require the addi
`tion of an entire non-volatile memory to the volatile memory
`just for this purpose.
`
`SUMMARY
`
`0004. This disclosure relates to a flashbacked dual in-line
`memory module (DIMM) module including a non-volatile
`memory, a volatile memory, and a controller. During normal
`operation the DIMM is powered by a primary power source.
`When the primary power source is interrupted, a backup
`power source Supplies sufficient temporary power to the
`DIMM so that the controller can transfer data from the vola
`tile memory into the non-volatile memory before power from
`the backup power source is depleted. When the primary
`
`power Source becomes available again, the controller trans
`fers the data that was stored in the non-volatile memory back
`into Volatile memory.
`0005. In one aspect, a memory device includes: volatile
`memory; an interface for connecting to a backup power
`Source arranged to power the Volatile memory upon a loss of
`power of a primary power source; non-volatile memory; a
`first configuration data bus for accessing parameters describ
`ing Substantially permanent characteristics of the Volatile
`memory; a second configuration data bus for accessing at
`least one of state of health information of the backup power
`Source and status information of the memory device, wherein
`the first configuration data bus and the second configuration
`data bus implement a same bus protocol; a controller, in
`communication with the first configuration data bus, the sec
`ond configuration data bus, the Volatile memory, and the
`non-volatile memory, that is programmed to detect a loss of
`power of the primary power source and in response move data
`from the volatile memory to the non-volatile memory,
`wherein first configuration information of the controller is at
`least one of readable and writable through the first configu
`ration data bus; and wherein at least one of the state of health
`information and the status information is at least one of read
`able and writable through the second configuration data bus.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0006 FIG. 1 is a block diagram of a dual in-line memory
`module (DIMM).
`0007 FIG. 2 is a block diagram of a capacitor based
`backup power Supply that can be used to power components
`of FIG. 1 in the event of a power failure.
`0008 FIG. 3 is block diagram of a battery based backup
`power Supply that can be used to power components of FIG.
`1 in the event of a power failure.
`0009 FIG. 4 is a block diagram illustrating example states
`and transitions of the DIMM illustrated in FIG. 1.
`0010 FIG. 5 shows various read operation timing dia
`grams of an Inter-Integrated Circuit (I2C) interface of the
`DIMM illustrated in FIG. 1.
`0011
`FIG. 6 shows various write operation timing dia
`grams of an Inter-Integrated Circuit (I2C) interface of the
`DIMM illustrated in FIG. 1.
`0012 FIG. 7 shows the architecture of the DIMM illus
`trated in FIG. 1.
`0013 FIG. 8 shows the architecture of a power supply
`used to power the DIMM illustrated in FIG. 1.
`0014 FIG. 9 is a more detailed illustration the backup
`power supply of FIG. 2.
`
`DETAILED DESCRIPTION
`(0015 Referring to FIG. 1, the described embodiment of
`the invention is a dual in-line memory module (DIMM) 100
`that includes volatile memory 120, non-volatile memory 130,
`isolation logic 140, and a controller 110. DIMM 100 is con
`nected to a primary power Source (not show) to support nor
`mal operation and is also connected to a backup power source
`200 (see FIG. 2). When DIMM 100 is operating under power
`Supplied by the primary power source, an external system
`(e.g. a RAID system) stores data in and reads data from
`volatile memory 120 through interface 105. However, when
`the power from the primary power source 200 is interrupted,
`a backup power Source Supplies Sufficient temporary power to
`DIMM 100 so that controller 110 can cause isolation logic
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 11
`
`

`

`US 2010/0205470 A1
`
`Aug. 12, 2010
`
`140 to isolate volatile memory 120 from the external system
`and then transfer data from volatile memory 120 into non
`volatile memory 130 before power from backup power source
`200 is depleted. When the primary power source becomes
`available again, controller 110 transfers the data that was
`stored in non-volatile memory 130 back into volatile memory
`120 and causes isolation logic 140 to reconnect volatile
`memory 120 to the external system.
`0016 Volatile memory 120 is a DRAM array that includes
`various DRAM chips, e.g., DRAM chips 121 and 122. Non
`volatile memory 130 includes various flash memory devices,
`e.g., flash devices 131 and 132. Due to constraints of DIMM
`100, all the data stored in volatile memory 120 cannot be
`moved to non-volatile memory 130 at one time. One of these
`constraints is that the flash devices of non-volatile memory
`130 cannot be written into as fast as the DRAM devices of
`volatile memory 120 can be read from. To account for this
`discrepancy, data is moved from volatile memory 120 to
`non-volatile memory 130 one DRAM chip at a time. In addi
`tion, during the transfer of data from volatile memory 120 to
`non-volatile memory 130, DRAM chips not being actively
`transferred are put into a low power state that maintains the
`data stored in them but consumes less power than a normal
`operating state. In the DRAM chips of volatile memory 120,
`this low power state is self-refresh mode. By putting the
`DRAM chips that are not being actively transferred into a low
`power state, module 100 requires less power during the
`backup operation than it would otherwise. This allows, for
`example, for a smaller and less expensive backup power
`Source to be used.
`0017 FIG. 2 shows a block diagram of such a power
`source. Specifically, FIG. 2 shows a electrochemical double
`layer (EDL) capacitor backup supply module 200 that inter
`acts with DIMM 100 using interface lines (e.g., power, I/O.
`etc.) 170 (EDL capacitors are also know as super capacitors
`and ultra capacitors). Capacitor 210 Supplies the backup
`power to DIMM 100 upon a power failure of the primary
`power source of DIMM 100. Charger and monitor 220 charge
`capacitor 210 and perform state-of-health monitoring of
`capacitor 210 so that, for example, DIMM 100 can be alerted
`if capacitor 210 is failing and can no longer provide backup
`power. In some cases, a battery may be selected instead of a
`capacitor. For example, FIG. 3 shows a block diagram of a
`battery backup power supply module 300 that can be used
`instead of module 200.
`0018 Non-volatile memory 130 is embedded with the
`serial presence detect (SPD) information for volatile memory
`120 (e.g., information that describes the size and speed of
`DRAM chips in volatile memory 120). By using non-volatile
`memory 130 to store the SPD information of volatile memory
`120, volatile memory 120 avoids the need for having a sepa
`rate EEPROM module for storing this information. Avoiding
`the addition of a separate EEPROM saves costs, reduces the
`size module 100, and reduces the number of components
`required.
`0019 DIMM 100 includes two I2C buses between the
`external system and controller 110. I2C busses are typically
`used to attach low-speed peripherals to various devices when,
`for example, simplicity and low manufacturing cost are more
`important than speed. The first I2C bus is for accessing the
`Serial Presence Detect (SPD) EEPROM (the “SPDI2C bus”).
`This is defined by the standard JEDEC spec. The second I2C
`bus is used to access other module 100 information, such as,
`status information and state-of-health (SoH) information for
`
`controller 110, non-volatile memory 130, and backup power
`source 200 (the “NVDIMM I2C bus'). The status informa
`tion can include, for example, current state of the flash
`memory (written, erased, erasing, defective, etc.); number of
`bad blocks Swapped out; number of spare blocks remaining;
`total number of download cycles completed; number of ECC
`errors in last download; number of ECC errors in last restore;
`status of last download (in progress, completed no errors,
`completed with errors, etc.); status of last restore (in progress,
`completed no errors, completed with errors, etc); flash header
`information. The SoH information can include, for example,
`current state of the backup power source (charged, dis
`charged, charging, etc.), whether any capacitors making up a
`backup power source have failed (and if so, which capacitors
`have failed), and type of backup power source (e.g., capacitor
`or battery).
`
`Block Diagram Details
`0020 Flash memory 130 provides the nonvolatile storage
`on the DIMM and is implemented using Secure Digital (SD)/
`MultiMediaCard+ (MMC+). Controller 110 can support vari
`ous arrangements, for example, four independent SD/MMC+
`interfaces to four SD mass storage devices each operating
`with 20 Mbyte/sec bandwidth using a 4-bit data bus or four
`MMC+ mass storage devices each operation with 40 Mbyte/
`sec bandwidth using an 8-bit data bus. One advantage of using
`SD/MMC technology is the complexity of managing flash
`memory is hidden from controller 110 using a simple, low pin
`count interface. The flash memories can be implemented in a
`single device, for example, the SanDisk iNAND, or can be
`constructed using a discrete SD controller with separate
`NAND memory devices on the same DIMM. In either case,
`the SD/MMC controller is responsible for ECC and badblock
`management according to the NAND technology used.
`(0021
`Serial Presence Detect (SPD) data is stored in the
`first 256 bytes of the flash memory attached to the first
`SD/MMC+ interface (i.e., flash chip 131). The typical write
`protection mechanism is implemented using flags stored
`within the flash configuration space. Controller 110 imple
`ments a read-cache, write-through mechanism for the SPD
`data, where the SPD information can be stored in a cache on
`controller 110 (in addition to on a flash chip 131). During
`system power up, controller 110 fetches the SPD data from
`the flash memory. Read operations on the SPD I2C interface
`use the cached data while write operations are immediately
`written to the flash memory. During the write operation to the
`flash memory, the SPD I2C interface will ignore any read or
`write requests.
`0022. The status information data is stored in the second
`256 bytes of the flash memory attached to the first SD/MMC+
`interface. This interface allows the user to monitor and con
`figure the operation of the non-volatile functions. The region
`is also used to track the system state during the last power
`cycle. Controller 110 implements a read-cache, write-cache
`mechanism for the configuration data, where the status infor
`mation can be stored in a cache on controller 110 (in addition
`to on a flash chip 131). During system power up, the FPGA
`fetches the data from the flash memory. Read and write opera
`tions on the NVDIMM I2C interface use the cache data.
`Cache data is written back during power-off and power-loss
`(backup) events. Registers accessible through the NVDIMM
`I2C interface are described in Appendix A.
`0023 Controller 110 is an advanced embedded processor
`with a custom 133 MHz DDR controller, four custom
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 12
`
`

`

`US 2010/0205470 A1
`
`Aug. 12, 2010
`
`SD/MMC+ host interfaces, the SPD I2C interface, and the
`NVDIMM I2C interface. The microprocessor can be, for
`example, a soft 32-bit Altera NIOS RISC processor executing
`firmware from the internal memory instance in the FPGA
`(programmable read-only memory (PROM) 115). The pro
`cessor controls the operating state of module 100 data move
`ment between the DDR and SD/MMC+ interfaces and com
`munication on the SPD and NVDIMM I2C interfaces. The
`custom DDR interface allows controller 110 to manipulate
`the DRAM array on a per byte-lane basis. The interface has
`individual control of the CKE signals allowing each device in
`the DRAM array to be controlled. The controller uses the first
`8 bytes in each byte lane in the array to set the internal phase
`alignment of the bus. The four custom SD/MMC+ interfaces
`are designed for embedded applications where features Such
`as hot plug are not required. The interface Supports 1-bit, 4-bit
`and 8-bit operation at clock speeds up to 50 MHz. The inter
`faces also can operate together synchronizing four
`SD/MMC+ cards allowing high-bandwidth read and write
`operations without large amounts of data buffering. For appli
`cations requiring the SD/MMC+ cards to be removed, the
`FPGA host interface allows the cards to be reordered for
`situations where the cards are not installed in the correct
`order.
`0024. Volatile Memory 120 is a DRAM array. Various
`examples configurations including 8 bits of error correcting
`code (ECC) for every 64 bits of actual data are shown in the
`table below. In the example with two Giga bytes of
`NVDIMM, one rank can be turned on and off depending on
`current memory requirements. Turning off a rank when it is
`unneeded saves power. When data (actual data and ECC) is
`moved from volatile memory 120 to non-volatile memory
`130, non-volatile memory 130 stores the actual data and ECC
`without a distinction between the two stored in the non
`volatile memory 130. When the data is moved back from
`non-volatile memory 130 to volatile memory 120, controller
`110 restores the actual data and ECC back into volatile
`memory 120 as is appropriate for the particular DRAM
`devices being used.
`
`NVDIMM DRAM
`Total
`Device
`
`Configuration
`
`# of
`DRAMs
`
`Ranks
`
`256Mbyte 512 Mbit
`512 Mbyte
`1 Gbit
`1 Gbyte
`1 Gbit
`2 Gbyte
`1 Gbit
`
`32M words x 16 bits
`64M words x 16 bits
`128 M words x 8 bits
`128 M words x 8 bits
`
`5
`5
`9
`18
`
`1
`1
`1
`2
`
`0025 PLL 161 is a high performance, low skew, PLL
`based, Zero-delay buffer that distributes a differential input
`clock signal to the DRAM array. The DDR clock from the
`edge connector is multiplexed with the DDR2 clock from
`controller 110 to prevent PLL 161 from entering into its low
`power State and tristating its outputs. In this example design,
`the selected PLL must operate at the desired system rate as
`well as a slower DDR controller rate. In general, PLLs bypass
`themselves and operate as a small-delay buffer at the slowest
`clock rates
`0026 Control and address signals are re-driven through
`registers 162 to the DRAM devices on the following rising
`clock edge (data access is delayed by one clock). Controller
`110 uses tristates to access the address and control signals.
`When controller 110 controls DRAM 120, the register is
`
`isolated from the edge connector using FET bus switches 163
`and controller 110 can directly drive the register inputs. When
`the system controls the DRAM array, the FET bus switches
`163 are on and the FPGA tristates its outputs. The CKE
`signals are treated differently from the other control signals.
`The Switching between the two operational modes is glitch
`less to ensure DRAM 120 remains in self-refresh mode. For
`these signals, FET switches 163 are used to multiplex
`between the edge connector (leading to the system) and con
`troller 110.
`(0027. The high-bandwidth FET mulitplexers 163 and 164
`are designed to Support high-bandwidth applications such as
`memory interleaving, bus isolation and low-distortion signal
`gating. The FET multiplexers 163 and 164 isolate module 100
`from the system bus during a power-loss event. The FET
`multiplexers use a charge pump to elevate the gate Voltage of
`the pass transistor, to provide a low and flat on-state resis
`tance. The low and flat on-state resistance allows for minimal
`propagation delay and Supports rail-to-rail Switching on the
`data input/output (I/O) ports. The FET multiplexers also fea
`ture low data I/O capacitance to minimize capacitive loading
`and signal distortion on the data bus.
`0028 Depending on the configuration of module 100, not
`all data stored in volatile memory 120 is backed up to non
`volatile memory 130. Instead, module 100 can be configured
`to backup (and later restore) data stored in select portions of
`volatile memory 120. Information stored in non-volatile
`memory is typically key/directory information used to deter
`mine the location of information (e.g., files) in a file system.
`Key/directory information is critical information that essen
`tially all users will choose to backup. However, other types of
`information can also be stored in volatile memory 120. For
`example, Software program information that does not change
`(e.g., a “...exe file) can be stored in volatile memory 120.
`Controller 110 includes registers that allow a user to segment
`volatile memory 120. A starting address is stored in one
`register and an ending address is stored in a second register.
`All data stored between these two addresses will be backuped
`and restored. Data stored outside of these addresses will not
`be backuped/restored. The values of these registers are con
`trolled through the NVDIMMI2C bus. Users, may choose for
`example, specify the starting and ending addresses such that
`only key/directory information is backedup/restored. One
`reason for choosing to only restore key/directory information
`is to improve restore time by not wasting time restoring
`information that does not need to be restored from non-vola
`tile memory 130 (e.g., a “.exe' has very likely not changed
`and can be loaded from the host system when required).
`0029 Module 100 can be configured to support various
`numbers of flash chips (e.g., 1-4) and is its firmware is pro
`grammed depending on the selected number. The number of
`flash chips used can be based on, for example, the size of
`volatile memory that needs to be backed up and the time in
`which the backup must occur (e.g., the amount of time backup
`power can be Supplied) or on reaching a desired restore speed
`(i.e., more flash devices allow for a quicker restore time). For
`example, for a controller that can Support up to four flash
`chips, the controller would have four busses. Each of the
`busses can be connected (or not connected) to a flash chip
`depending on the selected number offlash chips. The selected
`number of flash chips (e.g., 1, 2, or 4) are connected to the
`busses and soldered onto a printed circuit board (PCB). For a
`module 100 that is designed to accommodate up to four flash
`chips, if only two flash chips were installed, the remaining
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 13
`
`

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`US 2010/0205470 A1
`
`Aug. 12, 2010
`
`space for the not-installed two flash chips remains empty and
`controller 110 is programmed to only attempt to communi
`cate with the two installed flash chips. For a constant backup
`time or restore time, the number of flash chips can be
`increased in proportion with the size of the volatile memory.
`Alternatively, the backup time and restore time can be
`reduced by increasing the number of flash chips.
`Signal Descriptions
`0030 Module 100 implements a 72 bit DDR2 memory
`interface with a 244 pin mini-DIMM connector. The connec
`tor signal assignments are defined in JEDEC Standard 21C
`Page 4.20.14-2, DDR2 Registered Mini-DIMM Design
`Specification (currently available from www.jdec.org).
`Appendix B shows signal assignments for the mini-DIMM
`connector used by module 100. Each of these signals can be
`part of signals 150 or 170. Signals corresponding to each of
`the 244 pins are not illustrated in FIG. 1 to avoid making FIG.
`1 unreadable.
`0031. The NVDIMM RESET signal initializes controller
`110 and forces the controller to restart its state machine.
`Controller 110 is also reset when the standard RESET IN
`input is asserted (along with, for example, Volatile memory
`120 and register 162). When the controller 110 is held in reset
`by NVDIMM RESET, module 100 operates normally. That
`is, the when NVDIMM RESET is asserted, FET switches
`163 are held on thus allowing the system to access the DRAM
`memory 120 without further interaction.
`0032. The NVDIMM PG signal reports the state of the
`power in the user system. When the signal is high, the system
`power rails are operating within specification. When the sig
`nal goes low, power loss is imminent and controller 110
`moves data to flash memory 130. The system puts all DRAM
`devices (e.g., 121-122) into self-refresh operation before
`deasserting NVDIMM PG if the DRAM device data is to be
`moved to flash memory (as indicated by the NVCACHE
`ENABLE signal). If NVCACHE ENABLE is low when
`NVDIMM PG deasserts, then the data in the DRAM devices
`is ignored during the power loss event.
`0033. The NVCACHE ENABLE signal reports the exist
`ence of cache data in the DRAM devices that should be
`moved to flash memory if the system power fails. If
`NVCACHE ENABLE is high when NVDIMM PG deas
`serts, controller 110 moves the data in the DRAM devices to
`flash memory. If NVCACHE ENABLE is low when
`NVDIMM PG deasserts, the DRAM contents are ignored
`and are not stored in flash memory 130. That last sequence
`used by the system to shut down normally (e.g., without a
`power failure in response to a user requesting a shut down).
`When NVDIMM PG is low, NVCACHE ENABLE is
`ignored by controller 110 to prevent spurious transitions on
`the signal from affecting any backup events.
`0034. During restore operations, the NVCACHE EN
`ABLE is used by the system to signal to controller 110 that
`flash memory 130 may be erased. A dirty tag within the flash
`memory is not cleared until a handshake with NVCACHE
`ENABLE is completed. This allows, for example, the system
`to handle another power loss event during the restore opera
`tion.
`0035. After the data is moved from flash memory 130 to
`DRAM 120, the DRAM AVAILABLE signal is asserted
`indicating the system may access the data. When the system
`decides flash memory 130 should be purged (e.g., to prevent
`data to be restored again after a power loss event), the system
`
`deasserts (falling edge) NVCACHE ENABLE to reset the
`flash memory. The system waits for NVDIMM READY to
`assert before asserting NVCACHE ENABLE again. The
`system can continue to use module 100 before NVDIMM
`READY asserts, but the data will not be backed up during a
`power-loss event.
`0036. The CACHE DIRTY signal indicates that flash
`memory 130 contains a data image of DRAM 120. During the
`BACKUP state, the CACHE DIRTY signal indicates the
`start of the backup process. During POWER UP state, the
`CACHE DIRTY indicates that flash memory 130 contains a
`backup image. The signal is held high until the NVCACHE
`ENABLE signal is deasserted (falling edge), indicating the
`cache data has been read from DRAM 120.
`0037. The DRAM AVAILABLE signal indicates when
`the system can access DRAM 120. When DRAM AVAIL
`ABLE is low, controller 110 has control of DRAM 120. When
`the signal is high, the system can take the DRAM devices
`(e.g., 121-122) out of self-refresh and access the data. In the
`event of a power up with data in flash memory 130. DRAM
`AVAILABLE will remain deasserted until the flash data is
`moved to DRAM 120. Once the signal asserts, the system
`may read and write to DRAM 120, but cannot assert
`NVCACHE ENABLE until module 100 is ready. A delay
`between the assertion of DRAM AVAILABLE and
`NVCACHE ENABLE may arise, for example, after a restore
`operation because non-volatile memory 130 is being erased
`or the backup power Source is being recharged. The system
`may choose to only read from (as opposed to reading from
`and writing to) volatile memory 120 during this time.
`0038. The NVDIMM READY signal indicates that mod
`ule 100 is capable of handling a power-loss event. The signal
`does not assert until the external power source is in good
`health and fully charged. When configured to fully erase flash
`memory 130, the NVDIMM READY signal will also not
`assert until flash memory 130 is fully initialized to a known
`state. This feature allows the design to Support flash memory
`devices that cannot support full-speed burst write operations
`without erasing the flash memory. During normal system
`operation (idle state), the system cannot assert NVCACHE
`ENABLE until NVDIMM READY is asserted. During
`backup operation, NVDIMM READY is deasserted. During
`restore operation, NDIMM READY is deasserted. If control
`ler 110 determines at any time that a power loss event cannot
`be handled correctly, for example, if the EDL capacitor bank
`failed a self-test operation, controller 110 deasserts the
`NVDIMM READY to notify the system to move any cache
`data from the DIMM memory (e.g., to move the data to
`permanent storage Such as a hard drive of the system).
`0039. The NVDIMM SEATED is a pull-up pin on the
`DIMM pin out that allows the system to detect module 100.
`The system also can also detect module 100 by attempting to
`read from the NVDIMMI2C interface to see if the I2C slave
`responds.
`0040. The NVDIMMI2C slave interface on controller 110
`provides a full-feature user interface to controller 110. A user
`can configure and control controller 110 as well as access
`detailed status information using the NVDIMM SDA and
`NVDIMM SCL (signals 152).
`0041 V3P3 AUX is the auxiliary 3.3V voltage rail that
`Supplies power to the nonvolatile logic during normal system
`operation. During a power loss condition, module 100
`switches from this supply and operates from VBACK171 (the
`
`Samsung Electronics Co., Ltd.
`Ex. 1044, p. 14
`
`

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`US 2010/0205470 A1
`
`Aug. 12, 2010
`
`Voltage rail that is the power Supply used during the backup
`operation) until controller 110 turns itself off.
`0042 Module 100 also includes a third I2C interface that
`is located between controller 110 and backup power source
`200 (the “backup power supply I2C interface'). The backup
`power supply I2C interface allows controller 110 to commu
`nicate with the external backup power Supply module using
`VBACK SDA and VABACK SCL. Through the interface,
`controller 110 can determine the type of backup power
`method (e.g., EDL capacitor or battery) as well as determine
`the