(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2010/0257304 A1
`Rajan et al.
`(43) Pub. Date:
`Oct. 7, 2010
`
`US 2010O257304A1
`
`(54)
`
`(75)
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`(73)
`
`(21)
`(22)
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`(63)
`
`APPARATUS AND METHOD FOR POWER
`MANAGEMENT OF MEMORY CIRCUITS BY
`A SYSTEM OR COMPONENT THEREOF
`
`Inventors:
`
`Suresh Natarajan Rajan, San Jose,
`CA (US); Michael John Sebastian
`Smith, Palo Alto, CA (US); David
`T. Wang, San Jose, CA (US)
`Correspondence Address:
`FSH & RICHARDSON P.C.
`PO BOX 1022
`MINNEAPOLIS, MN 55440-1022 (US)
`Assignee:
`GOOGLE INC., Mountain View,
`CA (US)
`12/816,756
`
`Appl. No.:
`
`Filed:
`
`Jun. 16, 2010
`Related U.S. Application Data
`Continuation of application No. 1 1/538,041, filed on
`Oct. 2, 2006, which is a continuation-in-part of appli
`
`cation No. 1 1/524,811, filed on Sep. 20, 2006, now Pat.
`No. 7,590,796, which is a continuation-in-part of
`application No. 1 1/461,439, filed on Jul. 31, 2006, now
`Pat. No. 7,580,312.
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 2/08
`(2006.01)
`G06F 12/00
`(2006.01)
`G06F I3/372
`(52) U.S. C. ... 711/6: 711/105: 710/117: 711/E12.016:
`711 FE12.OO1
`
`ABSTRACT
`(57)
`An apparatus and method are provided for communicating
`with a plurality of physical memory circuits. In use, at least
`one virtual memory circuit is simulated where at least one
`aspect (e.g. power-related aspect, etc.) of Such virtual
`memory circuit(s) is different from at least one aspect of at
`least one of the physical memory circuits. Further, in various
`embodiments, such simulation may be carried out by a system
`(or component thereof), an interface circuit, etc.
`
`1OO
`
`MEMORY CIRCUIT
`
`
`
`
`
`108
`
`104A
`MEMORY CIRCUIT
`
`104B
`
`110
`
`
`
`L
`
`MEMORY CIRCUIT
`
`104N
`
`INTERFACE CIRCUIT
`
`
`
`
`
`SYSTEM
`
`106
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 1
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 1 of 7
`
`US 2010/0257304 A1
`
`1OO
`
`MEMORY CIRCUIT m
`
`108
`g w
`
`C
`CD
`
`L
`
`&
`
`104A
`MEMORY CIRCUIT - 110
`104B
`on
`s a
`O
`on
`MEMORY CIRCUIT w M
`
`104N
`
`INTERFACE CIRCUIT
`
`102.
`
`SYSTEM
`
`106
`
`FIGURE 1
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 2
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 2 of 7
`
`US 2010/0257304 A1
`
`260
`
`208
`
`240
`
`w
`O
`2
`O
`O
`es
`
`:
`? C
`
`
`
`2O2C
`DRAM
`
`
`
`REGISTER
`REGISTER
`ADDRESS
`&
`CONTROL
`
`
`
`
`
`220
`
`BUFFER
`
`
`
`230
`
`DATA
`
`
`
`
`
`SYSTEM
`
`204
`
`FIGURE 2
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 3
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 3 of 7
`
`US 2010/0257304 A1
`
`350
`
`
`
`
`
`
`
`306
`
`REGISTER :
`
`
`
`
`
`320
`
`
`
`ADDRESS
`&
`CONTROL
`
`BUFFER
`
`
`
`330
`
`DATA
`
`370
`
`308
`
`304
`
`FIGURE 3
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 4
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 4 of 7
`
`US 2010/0257304 A1
`
`440
`
`O
`4.
`Z
`O
`O
`
`430
`
`
`
`ADDRESS 8.
`CONTROL DATA
`
`470
`
`460
`
`408
`
`4O6
`
`420
`
`ADDRESS, CONTROL., & DATA
`
`SYSTEM
`
`FIGURE 4
`
`404
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 5
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 5 of 7
`
`US 2010/0257304 A1
`
`540
`
`560
`
`508
`
`REGISTER
`
`REGISTER
`
`53O
`
`
`
`ADDRESS
`&
`CONTROL
`
`BUFFER
`
`s
`
`510
`
`570
`
`DATA
`
`AMB
`
`506
`
`520
`
`ADDRESS, CONTROL, & DATA
`
`SYSTEM
`
`504
`
`FIGURE 5
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 6
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 6 of 7
`
`US 2010/0257304 A1
`
`630
`
`650
`
`608
`
`606
`
`BUFFER
`
`
`
`CONTROL
`
`DATA
`
`660
`
`620
`
`ADDRESS, CONTROL., & DATA
`
`SYSTEM
`
`FIGURE 6
`
`604
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 7
`
`

`

`Patent Application Publication
`
`Oct. 7, 2010 Sheet 7 of 7
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`US 2010/0257304 A1
`
`VIRTUAL BANK, 730
`
`
`
`PHYSICAL BANK, 720
`
`708
`
`INTERFACE CIRCUIT
`
`SYSTEM
`
`FIGURE 7
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 8
`
`

`

`US 2010/0257304 A1
`
`Oct. 7, 2010
`
`APPARATUS AND METHOD FOR POWER
`MANAGEMENT OF MEMORY CIRCUITS BY
`A SYSTEM OR COMPONENT THEREOF
`
`RELATED APPLICATION(S)
`0001. The present application is a continuation of an appli
`cation entitled “APPARATUS AND METHOD FOR
`POWERMANAGEMENT OF MEMORY CIRCUITS BY A
`SYSTEM OR COMPONENT THEREOF and filed Oct. 2,
`2006 under application Ser. No. 1 1/538,041 which, in turn is
`a continuation-in-part of an application entitled “SYSTEM
`AND METHOD FOR POWER MANAGEMENT IN
`MEMORY SYSTEMS and filed Sep. 20, 2006 under appli
`cation Ser. No. 1 1/524,811, and issued as U.S. Pat. No. 7,590,
`796 on Sep. 15, 2009 which, in turn, is a continuation-in-part
`of an application entitled “POWERSAVING SYSTEMAND
`METHOD FOR USE WITH APLURALITY OF MEMORY
`CIRCUITS” and filed Jul.31, 2006 under application Ser. No.
`1 1/461,439, and issued as U.S. Pat. No. 7,580,312 on Aug. 25,
`2009 which are each incorporated herein by reference for all
`purposes. However, insofar as any definitions, information
`used for claim interpretation, etc. from the above parent appli
`cations conflict with that set forth herein, such definitions,
`information, etc. in the present application should apply.
`
`FIELD OF THE INVENTION
`0002 The present invention relates to memory, and more
`particularly to power management in memory systems that
`contain multiple memory circuits.
`
`BACKGROUND
`0003. The memory capacity requirements of various sys
`tems are increasing rapidly. However, other industry trends
`Such as higher memory bus speeds and Small form factor
`machines, etc. are reducing the number of memory module
`slots in Such systems. Thus, a need exists in the industry for
`larger capacity memory circuits to be used in Such systems.
`0004. However, there is also a limit to the power that may
`be dissipated per unit volume in the space available to the
`memory circuits. As a result, large capacity memory modules
`may be limited in terms of power that the memory modules
`may dissipate, and/or limited in terms of the ability of power
`Supply systems to deliver Sufficient power to such memory
`modules. There is thus a need for overcoming these limita
`tions and/or other problems associated with the prior art.
`
`SUMMARY
`0005. An apparatus and method are provided for commu
`nicating with a plurality of physical memory circuits. In use,
`at least one virtual memory circuit is simulated where at least
`one aspect (e.g. power-related aspect, etc.) of Such virtual
`memory circuit(s) is different from at least one aspect of at
`least one of the physical memory circuits. Further, in various
`embodiments, such simulation may be carried out by a system
`(or component thereof), an interface circuit, etc.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0006 FIG. 1 illustrates a multiple memory circuit frame
`work, in accordance with one embodiment.
`0007 FIG. 2 shows an exemplary embodiment of an inter
`face circuit including a register and a buffer that is operable to
`interface memory circuits and a system.
`
`0008 FIG.3 shows an alternative exemplary embodiment
`of an interface circuit including a register and a buffer that is
`operable to interface memory circuits and a system.
`0009 FIG. 4 shows an exemplary embodiment of an inter
`face circuit including an advanced memory buffer (AMB)
`and a buffer that is operable to interface memory circuits and
`a system.
`0010 FIG. 5 shows an exemplary embodiment of an inter
`face circuit including an AMB, a register, and a buffer that is
`operable to interface memory circuits and a system.
`0011
`FIG. 6 shows an alternative exemplary embodiment
`of an interface circuit including an AMB and a buffer that is
`operable to interface memory circuits and a system.
`0012 FIG. 7 shows an exemplary embodiment of a plu
`rality of physical memory circuits that are mapped by a sys
`tem, and optionally an interface circuit, to appear as a virtual
`memory circuit with one aspect that is different from that of
`the physical memory circuits.
`
`DETAILED DESCRIPTION
`0013 FIG. 1 illustrates a multiple memory circuit frame
`work 100, in accordance with one embodiment. As shown,
`included are an interface circuit 102, a plurality of memory
`circuits 104A, 104B, 104N, and a system 106. In the context
`of the present description, such memory circuits 104A, 104B,
`104N may include any circuit capable of serving as memory.
`0014 For example, in various embodiments, at least one
`of the memory circuits 104A, 104B, 104N may include a
`monolithic memory circuit, a semiconductor die, a chip, a
`packaged memory circuit, or any other type of tangible
`memory circuit. In one embodiment, the memory circuits
`104A, 104B, 104N may take the form of a dynamic random
`access memory (DRAM) circuit. Such DRAM may take any
`form including, but not limited to, synchronous DRAM
`(SDRAM), double data rate synchronous DRAM (DDR
`SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.), graphics
`double data rate synchronous DRAM (GDDR SDRAM,
`GDDR2 SDRAM, GDDR3 SDRAM, etc.), quad data rate
`DRAM (QDR DRAM), RAMBUS XDR DRAM (SDR
`DRAM), fast page mode DRAM (FPM DRAM), video
`DRAM (VDRAM), extended data out DRAM (EDO
`DRAM), burst EDO RAM (BEDO DRAM), multibank
`DRAM (MDRAM), synchronous graphics RAM (SGRAM),
`and/or any other type of DRAM.
`0015. In another embodiment, at least one of the memory
`circuits 104A, 104B, 104N may include magnetic random
`access memory (MRAM), intelligent random access memory
`(IRAM), distributed network architecture (DNA) memory,
`window random access memory (WRAM), flash memory
`(e.g. NAND, NOR, etc.), pseudostatic random access
`memory (PSRAM), Low-Power Synchronous Dynamic Ran
`dom. Access Memory (LP-SDRAM), Polymer Ferroelectric
`RAM (PFRAM), OVONICS Unified Memory (OUM) or
`other chalcogenide memory, Phase-change Memory (PCM),
`Phase-change Random Access Memory (PRAM), Ferrollec
`tric RAM (FeRAM), REsistance RAM (R-RAM or RRAM),
`wetware memory, memory based on semiconductor, atomic,
`molecular, optical, organic, biological, chemical, or nanos
`cale technology, and/or any other type of volatile or nonvola
`tile, random or non-random access, serial or parallel access
`memory circuit.
`0016 Strictly, as an option, the memory circuits 104A,
`104B, 104N may or may not be positioned on at least one dual
`in-line memory module (DIMM) (not shown). In various
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 9
`
`

`

`US 2010/0257304 A1
`
`Oct. 7, 2010
`
`embodiments, the DIMM may include a registered DIMM
`(R-DIMM), a small outline-DIMM(SO-DIMM), a fully buff
`ered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM),
`single inline memory module (SIMM), a MiniDIMM, a very
`low profile (VLP) R-DIMM, etc. In other embodiments, the
`memory circuits 104A, 104B, 104N may or may not be posi
`tioned on any type of material forming a Substrate, card,
`module, sheet, fabric, board, carrier or other any other type of
`solid or flexible entity, form, or object. Of course, in other
`embodiments, the memory circuits 104A, 104B, 104N may or
`may not be positioned in or on any desired entity, form, or
`object for packaging purposes. Still yet, the memory circuits
`104A, 104B, 104N may or may not be organized, either as a
`group (or as groups) collectively, or individually, onto one or
`more portions(s). In the context of the present description, the
`term portion(s) (e.g. of a memory circuit(s)) shall refer to any
`physical, logical or electrical arrangement(s), partition(s),
`Subdivisions(s) (e.g. banks, Sub-banks, ranks, Sub-ranks,
`rows, columns, pages, etc.), or any other portion(s), for that
`matter.
`0017. Further, in the context of the present description, the
`system 106 may include any system capable of requesting
`and/or initiating a process that results in an access of the
`memory circuits 104A, 104B, 104N. As an option, the system
`106 may accomplish this utilizing a memory controller (not
`shown), or any other desired mechanism. In one embodiment,
`such system 106 may include a system in the form of a
`desktop computer, a lap-top computer, a server, a storage
`system, a networking system, a workstation, a personal digi
`tal assistant (PDA), a mobile phone, a television, a computer
`peripheral (e.g. printer, etc.), a consumer electronics system,
`a communication system, and/or any other software and/or
`hardware, for that matter.
`0018. The interface circuit 102 may, in the context of the
`present description, refer to any circuit capable of communi
`cating (e.g. interfacing, buffering, etc.) with the memory cir
`cuits 104A, 104B, 104N and the system 106. For example, the
`interface circuit 102 may, in the context of different embodi
`ments, include a circuit capable of directly (e.g. via wire, bus,
`connector, and/or any other direct communication medium,
`etc.) and/or indirectly (e.g. via wireless, optical, capacitive,
`electric field, magnetic field, electromagnetic field, and/or
`any other indirect communication medium, etc.) communi
`cating with the memory circuits 104A, 104B, 104N and the
`system 106. In additional different embodiments, the com
`munication may use a direct connection (e.g. point-to-point,
`single-drop bus, multi-drop bus, serial bus, parallel bus, link,
`and/or any other direct connection, etc.) or may use an indi
`rect connection (e.g. through intermediate circuits, interme
`diate logic, an intermediate bus or busses, and/or any other
`indirect connection, etc.).
`0019. In additional optional embodiments, the interface
`circuit 102 may include one or more circuits, such as a buffer
`(e.g. buffer chip, multiplexer/de-multiplexer chip, synchro
`nous multiplexer/de-multiplexerchip, etc.), register (e.g. reg
`ister chip, data register chip, address/control register chip,
`etc.), advanced memory buffer (AMB) (e.g. AMB chip, etc.),
`a component positioned on at least one DIMM, etc.
`0020. In various embodiments and in the context of the
`present description, a buffer chip may be used to interface
`bidirectional data signals, and may or may not use a clock to
`re-time or re-synchronize signals in a well known manner. A
`bidirectional signal is a well known use of a single connection
`to transmit data in two directions. A data register chip may be
`
`a register chip that also interfaces bidirectional data signals. A
`multiplexer/de-multiplexer chip is a well known circuit that
`may interface a first number of bidirectional signals to a
`second number of bidirectional signals. A synchronous mul
`tiplexer/de-multiplexer chip may additionally use a clock to
`re-time or re-synchronize the first or second number of Sig
`nals. In the context of the present description, a register chip
`may be used to interface and optionally re-time or re-synchro
`nize address and control signals. The term address/control
`register chip may be used to distinguish a register chip that
`only interfaces address and control signals from a data regis
`ter chip, which may also interface data signals.
`0021 Moreover, the register may, in various embodi
`ments, include a JEDEC Solid State Technology Association
`(known as JEDEC) standard register (a JEDEC register), a
`register with forwarding, storing, and/or buffering capabili
`ties, etc. In various embodiments, the registers, buffers, and/
`or any other interface circuit(s) 102 may be intelligent, that is,
`include logic that are capable of one or more functions such as
`gathering and/or storing information; inferring, predicting,
`and/or storing state and/or status; performing logical deci
`sions; and/or performing operations on input signals, etc. In
`still other embodiments, the interface circuit 102 may option
`ally be manufactured in monolithic form, packaged form,
`printed form, and/or any other manufactured form of circuit,
`for that matter.
`0022. In still yet another embodiment, a plurality of the
`aforementioned interface circuits 102 may serve, in combi
`nation, to interface the memory circuits 104A, 104B, 104N
`and the system 106. Thus, in various embodiments, one, two,
`three, four, or more interface circuits 102 may be utilized for
`Such interfacing purposes. In addition, multiple interface cir
`cuits 102 may be relatively configured or connected in any
`desired manner. For example, the interface circuits 102 may
`be configured or connected in parallel, serially, or in various
`combinations thereof. The multiple interface circuits 102
`may use direct connections to each other, indirect connec
`tions to each other, or even a combination thereof. Further
`more, any number of the interface circuits 102 may be allo
`cated to any number of the memory circuits 104A, 104B,
`104N. In various other embodiments, each of the plurality of
`interface circuits 102 may be the same or different. Even still,
`the interface circuits 102 may share the same or similar inter
`face tasks and/or perform different interface tasks.
`(0023. While the memory circuits 104A, 104B, 104N,
`interface circuit 102, and system 106 are shown to be separate
`parts, it is contemplated that any of Such parts (or portion(s)
`thereof) may be integrated in any desired manner. In various
`embodiments. Such optional integration may involve simply
`packaging such parts together (e.g. stacking the parts to form
`a stack of DRAM circuits, a DRAM stack, a plurality of
`DRAM stacks, a hardware stack, where a stack may refer to
`any bundle, collection, or grouping of parts and/or circuits,
`etc.) and/or integrating them monolithically. Just by way of
`example, in one optional embodiment, at least one interface
`circuit 102 (or portion(s) thereof) may be packaged with at
`least one of the memory circuits 104A, 104B, 104N. Thus, a
`DRAM stack may or may not include at least one interface
`circuit (or portion(s) thereof). In other embodiments, differ
`ent numbers of the interface circuit 102 (or portions(s)
`thereof) may be packaged together. Such different packaging
`arrangements, when employed, may optionally improve the
`utilization of a monolithic silicon implementation, for
`example.
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 10
`
`

`

`US 2010/0257304 A1
`
`Oct. 7, 2010
`
`0024. The interface circuit 102 may be capable of various
`functionality, in the context of different embodiments. For
`example, in one optional embodiment, the interface circuit
`102 may interface a plurality of signals 108 that are connected
`between the memory circuits 104A, 104B, 104N and the
`system 106. The signals 108 may, for example, include
`address signals, data signals, control signals, enable signals,
`clock signals, reset signals, or any other signal used to operate
`or associated with the memory circuits, system, or interface
`circuit(s), etc. In some optional embodiments, the signals
`may be those that: use a direct connection, use an indirect
`connection, use a dedicated connection, may be encoded
`across several connections, and/or may be otherwise encoded
`(e.g. time-multiplexed, etc.) across one or more connections.
`0025. In one aspect of the present embodiment, the inter
`faced signals 108 may represent all of the signals that are
`connected between the memory circuits 104A, 104B, 104N
`and the system 106. In other aspects, at least a portion of
`signals 110 may use direct connections between the memory
`circuits 104A, 104B, 104N and the system 106. The signals
`110 may, for example, include address signals, data signals,
`control signals, enable signals, clock signals, reset signals, or
`any other signal used to operate or associated with the
`memory circuits, system, or interface circuit(s), etc. In some
`optional embodiments, the signals may be those that: use a
`direct connection, use an indirect connection, use a dedicated
`connection, may be encoded across several connections, and/
`or may be otherwise encoded (e.g. time-multiplexed, etc.)
`across one or more connections. Moreover, the number of
`interfaced signals 108 (e.g. vs. a number of the signals that use
`direct connections 110, etc.) may vary such that the interfaced
`signals 108 may include at least a majority of the total number
`of signal connections between the memory circuits 104A,
`104B, 104N and the systems 106 (e.g. LDM, with L and Mas
`shown in FIG. 1). In other embodiments, L may be less than
`or equal to M. In still other embodiments L and/or M may be
`ZO.
`0026. In yet another embodiment, the interface circuit 102
`and/or any component of the system 106 may or may not be
`operable to communicate with the memory circuits 104A,
`104B, 104N for simulating at least one memory circuit. The
`memory circuits 104A, 104B, 104N shall hereafter be
`referred to, where appropriate for clarification purposes, as
`the “physical memory circuits or memory circuits, but are
`not limited to be so. Just by way of example, the physical
`memory circuits may include a single physical memory cir
`cuit. Further, the at least one simulated memory circuit shall
`hereafter be referred to, where appropriate for clarification
`purposes, as the at least one “virtual memory circuit. In a
`similar fashion any property or aspect of Such a physical
`memory circuit shall be referred to, where appropriate for
`clarification purposes, as a physical aspect (e.g. physical
`bank, physical portion, physical timing parameter, etc.). Fur
`ther, any property or aspect of Such a virtual memory circuit
`shall be referred to, where appropriate for clarification pur
`poses, as a virtual aspect (e.g. virtual bank, virtual portion,
`virtual timing parameter, etc.).
`0027. In the context of the present description, the term
`simulate or simulation may refer to any simulating, emulat
`ing, transforming, disguising modifying, changing, altering,
`shaping, converting, etc., of at least one aspect of the memory
`circuits. In different embodiments, such aspect may include,
`for example, a number, a signal, a capacity, a portion (e.g.
`bank, partition, etc.), an organization (e.g. bank organization,
`
`etc.), a mapping (e.g. address mapping, etc.), a timing, a
`latency, a design parameter, a logical interface, a control
`system, a property, a behavior, and/or any other aspect, for
`that matter. Still yet, in various embodiments, any of the
`previous aspects or any other aspect, for that matter, may be
`power-related, meaning that such power-related aspect, at
`least in part, directly or indirectly affects power.
`0028. In different embodiments, the simulation may be
`electrical in nature, logical in nature, protocol in nature, and/
`or performed in any other desired manner. For instance, in the
`context of electrical simulation, a number of pins, wires,
`signals, etc. may be simulated. In the context of logical simu
`lation, a particular function or behavior may be simulated. In
`the context of protocol, aparticular protocol (e.g. DDR3, etc.)
`may be simulated. Further, in the context of protocol, the
`simulation may effect conversion between different protocols
`(e.g. DDR2 and DDR3) or may effect conversion between
`different versions of the same protocol (e.g. conversion of
`4-4-4 DDR2 to 6-6-6 DDR2).
`0029. In still additional exemplary embodiments, the
`aforementioned virtual aspect may be simulated (e.g. simu
`late a virtual aspect, the simulation of a virtual aspect, a
`simulated virtual aspect etc.). Further, in the context of the
`present description, the terms map, mapping, mapped, etc.
`refer to the link or connection from the physical aspects to the
`virtual aspects (e.g. map a physical aspect to a virtual aspect,
`mapping a physical aspect to a virtual aspect, a physical
`aspect mapped to a virtual aspect etc.). It should be noted that
`any use of Such mapping or anything equivalent thereto is
`deemed to fall within the scope of the previously defined
`simulate or simulation term.
`0030. More illustrative information will now be set forth
`regarding optional functionality/architecture of different
`embodiments which may or may not be implemented in the
`context of FIG. 1, per the desires of the user. It should be
`strongly noted that the following information is set forth for
`illustrative purposes and should not be construed as limiting
`in any manner. For example, any of the following features
`may be optionally incorporated with or without the other
`features described.
`0031
`FIG. 2 shows an exemplary embodiment of an inter
`face circuit that is operable to interface memory circuits
`202A-D and a system 204. In this embodiment, the interface
`circuit includes a register 206 and a buffer 208. Address and
`control signals 220 from the system 204 are connected to the
`register 206, while data signals 230 from the system 204 are
`connected to the buffer 208. The register 206 drives address
`and control signals 240 to the memory circuits 202A-D and
`optionally drives address and control signals 250 to the buffer
`208. Data signals 260 of the memory circuits 202A-D are
`connected to the buffer 208.
`0032 FIG.3 shows an exemplary embodiment of an inter
`face circuit that is operable to interface memory circuits
`302A-D and a system 304. In this embodiment, the interface
`circuit includes a register 306 and a buffer 308. Address and
`control signals 320 from the system 304 are connected to the
`register 306, while data signals 330 from the system 304 are
`connected to the buffer 308. The register 306 drives address
`and control signals 340 to the buffer 308, and optionally
`drives control signals 350 to the memory circuits 302A-D.
`The buffer 308 drives address and control signals 360. Data
`signals 370 of the memory circuits 304A-D are connected to
`the buffer 308.
`
`Samsung Electronics Co., Ltd.
`Ex. 1039, p. 11
`
`

`

`US 2010/0257304 A1
`
`Oct. 7, 2010
`
`0033 FIG. 4 shows an exemplary embodiment of an inter
`face circuit that is operable to interface memory circuits
`402A-D and a system 404. In this embodiment, the interface
`circuit includes an advanced memory buffer (AMB) 406 and
`a buffer 408. Address, control, and data signals 420 from the
`system 404 are connected to the AMB 406. The AMB 406
`drives address and control signals 430 to the buffer 408 and
`optionally drives control signals 440 to the memory circuits
`402A-D. The buffer 408 drives address and control signals
`450. Data signals 460 of the memory circuits 402A-D are
`connected to the buffer 408. Data signals 470 of the buffer 408
`are connected to the AMB 406.
`0034 FIG. 5 shows an exemplary embodiment of an inter
`face circuit that is operable to interface memory circuits
`502A-D and a system 504. In this embodiment, the interface
`circuit includes an AMB506, a register 508, and a buffer 510.
`Address, control, and data signals 520 from the system 504
`are connected to the AMB 506. The AMB 506 drives address
`and control signals 530 to the register 508. The register, in
`turn, drives address and control signals 540 to the memory
`circuits 502A-D. It also optionally drives control signals 550
`to the buffer 510. Data signals 560 from the memory circuits
`502A-D are connected to the buffer 510. Data signals 570 of
`the buffer 510 are connected to the AMB 506.
`0035 FIG. 6 shows an exemplary embodiment of an inter
`face circuit that is operable to interface memory circuits
`602A-D and a system 604. In this embodiment, the interface
`circuit includes an AMB 606 and a buffer 608. Address,
`control, and data signals 620 from the system 604 are con
`nected to the AMB 606. The AMB 606 drives address and
`control signals 630 to the memory circuits 602A-D as well as
`control signals 640 to the buffer 608. Data signals 650 from
`the memory circuits 602A-D are connected to the buffer 608.
`Data signals 660 are connected between the buffer 608 and
`the AMB 606.
`0036. In other embodiments, combinations of the above
`implementations shown in FIGS. 2-6 may be utilized. Just by
`way of example, one or more registers (register chip, address/
`control register chip, data register chip, JEDEC register, etc.)
`may be utilized in conjunction with one or more buffers (e.g.
`buffer chip, multiplexer/de-multiplexer chip, synchronous
`multiplexer/de-multiplexerchip and/or other intelligent inter
`face circuits) with one or more AMBs (e.g. AMB chip, etc.).
`In other embodiments, these register(s), buffer(s), AMB(s)
`may be utilized alone and/or integrated in groups and/or
`integrated with or without the memory circuits.
`0037. The electrical connections between the buffer(s),
`the register(s), the AMB(s) and the memory circuits may be
`configured in any desired manner. In one optional embodi
`ment, address, control (e.g. command, etc.), and clock signals
`may be common to all memory circuits (e.g. using one com
`mon bus). As another option, there may be multiple address,
`control and clockbusses. As yet another option, there may be
`individual address, control and clockbusses to each memory
`circuit. Similarly, data signals may be wired as one common
`bus, several busses or as an individual bus to each memory
`circuit. Of course, it should be noted that any combinations of
`Such configurations may also be utilized. For example, the
`memory circuits may have one common address, control and
`clock bus with individual data busses. In another example,
`memory circuits may have one, two (or more) address, con
`trol and clock busses along with one, two (or more) data
`busses. In still yet another example, the memory circuits may
`have one address, control and clock bus together with two
`
`data busses (e.g. the number of address, control, clock and
`data busses may be different, etc.). In addition, the memory
`circuits may have one common address, control and clockbus
`and one common data bus. It should be noted that any other
`permutations and combinations of Such address, control,
`clock and data buses may be utilized.
`0038. These configurations may therefore allow for the
`host system to only be in contact with a load of the buffer(s),
`or register(s), or AMB(S) on the memory bus. In this way, any
`electrical loading problems (e.g. bad signal integrity,
`improper signal timing, etc.) associated with the memory
`circuits may (but not necessarily) be prevented, in the context
`of various optional embodiments.
`0039. Furthermore, there may be any number of memory
`circuits. Just by way of example, the interface circuit(s) may
`be connected to 1, 2, 4, 8 or more memory circuits. In alter
`nate embodiments, to permit data integrity storage or for
`other reasons, the interface circuit(s) may be connected to an
`odd number of memory circuits. Additionally, the memory
`circuits may be arranged in a single stack. Of course, how
`ever, the memory circuits may also be arranged in a plurality
`of stacks or in any other fashion.
`0040. In various embodiments where DRAM circuits are
`employed, such DRAM (e.g. DDR2 SDRAM) circuits may
`be composed of a plurality of portions (e.g. ranks, Sub-ranks,
`banks, Sub-banks, etc.) that may be capable of performing
`operations (e.g. precharge, active, read, write, refresh, etc.) in
`parallel (e.g. simultaneously, concurrently, overlapping, etc.).
`The JEDEC standards and specifications describe how
`DRAM (e.g. DDR2 SDRAM) circuits are composed and
`perform operations in response to commands. Purely as an
`example, a 512Mb DDR2 SDRAM circuit that meets JEDEC
`specifications may be composed of four portions (e.g. banks,
`etc.) (each of which has 128Mb of capacity) that are capable
`of performing operations in parallel in response to com
`mands. As another example, a 2Gb DDR2 SDRAM circuit
`that is compliant with JEDEC specifications may be com
`posed of eight banks (each of which has 256Mb of capacity).
`A portion (e.g. bank, etc.) of the DRAM circuit is said to be in
`the active state after an activate command is issued to that
`portion. A portion (e.g. bank, etc.) of the DRAM circuit is said
`to be in the precharge state after a precharge command is
`issued to that portion. When at least one portion (e.g. bank,
`etc.) of the DRAM circuit is in the active state, the entire
`DRAM circuit is said to be in the active state. When all
`portions (e.g. banks, etc.) of the DRAM circuit are in pre
`charge state, the entire DRAM circuit is said to be in the
`precharge state. A relative time period spent by the entire
`DRAM circuit in precharge state with respect to the time
`period spent by the entire DRAM circuit inactive state during
`normal operation may be defined as the precharge-to-active
`ratio.
`0041. DRAM circuits may also support a plurality of
`power management modes. Some of these modes may repre
`sent power saving modes. As an example, DDR2 SDRAMs
`may support four power saving modes. In particular, two
`active power down modes, precharge power down mode, and
`self-refresh mode may be Supported, in one embodiment. A
`DRAM circuit may enter an active power down mode if the
`DRAM circuit is in the active state when it receives a power
`down command. A DRAM circuit may enter the precharge
`power down mode if the DRAM circuit is in the precharge
`state when it receives a pow