US007721 130B2
`
`(12) United States Patent
`Prete et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,721,130 B2
`May 18, 2010
`
`(54) APPARATUS AND METHOD FOR
`SWITCHING AN APPARATUS TO APOWER
`SAVING MODE
`
`(75) Inventors: Edoardo Prete, Munich (DE),
`Hans-Peter Trost, Munich (DE),
`Anthony Sanders, Haar (DE); Dirk
`Shiels, Mich SE Sw d
`E", (SISR, d i. Ood,
`Luyken, Munich (DE)
`(73) Assignee: Qimonda AG, Munich (DE)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent 1s is: Olisted under 35
`U.S.C. 154(b) by 656 days.
`(21) Appl. No.: 11/604,666
`
`(22) Filed:
`
`Nov. 27, 2006
`
`(65)
`
`Prior Publication Data
`US 2008/O12681.6 A1
`May 29, 2008
`ay 29,
`
`6,378,018 B1 * 4/2002 Tsernet al. ................. T10,313
`6,650,594 B1 * 1 1/2003 Lee et al. ............... 365,233.15
`2004/01484.82 A1* 7/2004 Grundy et al. .............. 711/167
`2004/0193829 A1* 9, 2004 Woo et al. ................... 711/17O
`2006/0184287 A1* 8/2006 Belady et al. .....
`... 700,291
`2006/0248355 A1 * 1 1/2006 Thayer ..........
`... 713,300
`2007/0076502 A1* 4/2007 Pyeon et al. ...
`... 365,221
`2007/0083701 A1* 4/2007 Kapil ......................... T11 106
`2007/0143542 A1* 6/2007 Watanabe et al. ........... 711 114
`2007/0283178 A1* 12/2007 Dodeja et al. ............... T13,324
`
`OTHER PUBLICATIONS
`Nasr, Marwan Rami, “FBSIM and the Fully Buffered DIMM
`Memory System Architecture.” Thesis, 2005, pp. 1-128, University
`f Marvland.
`of Marylan
`* cited by examiner
`Primary Examiner Thomas Lee
`Assistant Examiner Vincent T Tran
`(74) Attorney, Agent, or Firm Slater & Matsil, L.L.P.
`
`(57)
`
`ABSTRACT
`
`(51) Int. Cl
`(2006.01)
`G06F I/00
`An apparatus being connectable as a latch stage into a asyn
`3.08:
`ge. 2.
`chronous latch chain comprises a reception interface, wherein
`II: 79.2 upon receipt of the first signal at the reception interface, the
`(52) U.S. Cl. 71/5.7
`.
`. .
`s
`s
`apparatus Switches to one of the first power saving mode and
`. .
`(58) Field of Classification Search ................. 713/300,
`a second power saving mode, depending on the second signal
`713/323, 320; 711/170, 106, 5, 167; 36.5/221
`at the reception interface and wherein the apparatus offers a
`See application file for complete search history.
`first power consumption and a first wake-up time in the first
`References Cited
`power saving mode, and a second power consumption and a
`second wake-up time in the second power saving mode.
`U.S. PATENT DOCUMENTS
`5,357,621 A * 10, 1994 Cox ........................... 711 172
`
`(56)
`
`nOrthbOUnt - -> SOuthbOUnd
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`
`
`33 Claims, 2 Drawing Sheets
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 1
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`U.S. Patent
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`May 18, 2010
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`Sheet 1 of 2
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`US 7,721,130 B2
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`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 2
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`U.S. Patent
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`May 18, 2010
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`Sheet 2 of 2
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`US 7,721,130 B2
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`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 3
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`US 7,721,130 B2
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`1.
`APPARATUS AND METHOD FOR
`SWITCHING AN APPARATUS TO APOWER
`SAVING MODE
`
`TECHNICAL FIELD
`
`The present invention relates to an apparatus and method
`for Switching an apparatus to a power saving mode, for
`instance to an apparatus being connectable, as a latch stage
`into an asynchronous latch chain, for instance, a memory
`buffer for a memory bus in a memory system.
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`BACKGROUND
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`Modern computer systems offer a significant amount of
`computing power, as well as a large memory capacity, which
`enables fast and highly complex computations, as well as fast
`handling and processing of data. However, in modern com
`puter systems, a key issue is the power management and
`power consumption. For instance, in the field of mobile com
`puting, the available power is limited by the accumulators
`and/or the batteries available. Moreover, in the field of sta
`tionary computers, power consumption is a great issue, as the
`power dissipated has to be transported away from the com
`ponents preventing overheating of the respective circuitries
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`and components.
`Many computer systems and components of computer sys
`tems offer a power saving mode, in which components of the
`computer system are turned off or shut down. An example for
`a computer system or a subsystem of a computer system
`offering such a power saving mode is the memory system,
`which is employed in personal computers (PC), servers and
`workstations. One memory system employed in the men
`tioned computer systems is referred to as the so-called fully
`buffered DIMM system or a FBDIMM system
`(FBDIMM-Fully Buffered Dual Inline Memory Module:
`DIMM-Dual Inline Memory Module).
`Today’s concept, especially for high-speed interfaces in
`FBDIMM systems, however, offers only a single mode to
`reduce the power consumption of the system. Therefore, a
`compromise between the power saving and the time needed to
`Switchback from the power saving mode to an active mode, or
`a normal mode of operation, has to be made since this time is
`crucial for the system performance.
`In other words, measures taken to reduce the power con
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`Sumption exhibits a strong negative influence on the perfor
`mance of the computer system, especially the computing
`power and the available and effective bandwidth of bus struc
`tures, which are required for the transport of data between
`different components of the computer system, for instance,
`between a processor and the memory. In this context analog
`circuits used in interfaces exhibit, for example, a large power
`saving potential but suffer from the fact that they need a long
`time to recover again since, for instance, control loops and
`other feedback loops are needed to reach and maintain a
`stable working point and a stable working condition, before
`these interfaces can provide a reliable and fast data commu
`nication between the components attached.
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`SUMMARY OF THE INVENTION
`
`An embodiment of an apparatus being connectable, as a
`latch stage into an asynchronous latch chain comprises a
`reception interface, wherein upon receipt of a first signal at
`the reception interface the apparatus Switches to one of the
`first power saving mode and a second power saving mode,
`depending on the second signal at the reception interface,
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`wherein the apparatus offers a first power consumption and a
`first wake-up time in the first power saving mode and a second
`power consumption and a second wake-up time in the second
`power saving mode.
`An embodiment of an apparatus being connectable, as a
`latch stage into an asynchronous latch chain comprises a
`reception interface, wherein upon receipt of a first signal at
`the reception interface the apparatus Switches to one of the
`first power saving mode and a second power saving mode,
`depending on the second signal at the reception interface,
`wherein the apparatus offers a first power consumption and a
`first wake-up time in the first power saving mode and a second
`power consumption and a second wake-up time in the second
`power saving mode, wherein the first power consumption is
`higher than the second power consumption and wherein the
`first wake-up time is shorter than the second wake-up time.
`According to a further embodiment of the present inven
`tion, a memory system comprises a memory controller, a
`plurality of memory modules coupled to the memory control
`ler in an asynchronous latch chain configuration, the plurality
`of memory modules comprising a first memory module and a
`second memory module, wherein the first memory module is
`positioned nearer to the memory controller than the second
`memory module within the asynchronous latch chain,
`wherein the first memory module offers a first power con
`Sumption and a first wake-up time in a first power saving
`mode, wherein the second memory module offers a second
`power consumption and second wake-up time in a second
`power saving mode, wherein each memory module of the
`plurality of memory modules comprises a reception interface,
`wherein upon receipt of a first signal from the memory con
`troller at the reception interface, the first memory module
`Switches to the first power saving mode and the second
`memory module Switches to the second power saving mode,
`wherein the first power consumption is higher than the second
`power consumption and wherein the first wake-up time is
`shorter than the second wake-up time.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Embodiments of the present invention are described here
`inafter, making reference to the attached drawings.
`FIG. 1 shows a schematic block diagram of an embodiment
`of an apparatus according to a first embodiment of the present
`invention; and
`FIG. 2 shows a schematic block diagram of a second
`embodiment of an apparatus and an embodimentofa memory
`system according to a second embodiment of the present
`invention.
`
`DETAILED DESCRIPTION OF ILLUSTRATIVE
`EMBODIMENTS
`
`FIGS. 1 and 2 show block diagrams of an embodiment of
`an apparatus being connectable as a latch stage into an asyn
`chronous latch chain and an embodiment of a memory sys
`tem. Before a second embodiment of the present invention is
`described with respect to FIG. 2, a first embodiment of an
`apparatus being connectable as a latch stage into an asynchro
`nous latch chain is explained with respect to the schematic
`representation of an embodiment of the apparatus and an
`embodiment of a memory system shown in FIG. 1.
`FIG. 1 shows an embodiment of an apparatus 100 inte
`grated into an embodiment of a memory system according to
`the present invention. The memory system comprises, apart
`from the apparatus 100 shown in the center of FIG.1, a further
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`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 4
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`3
`apparatus 100' and a memory controller 110 forming an asyn
`chronous latch chain or a daisy chain as will be explained
`below.
`In a so-called daisy chain configuration, components of the
`daisy chain, which are also referred to as latch stages of the
`asynchronous latch chain, communicate only with their direct
`neighbors, for instance, via a wiring scheme comprising
`interfaces and signal lines of a bus structure. Hence, only
`neighboring devices are directly coupled to each other. Fur
`thermore, usually in a daisy chain no web like structures are
`formed and the coupling of the devices does not loop back, for
`instance, from the first device to the last device in the daisy
`chain.
`In other words, a typical daisy chain configuration in elec
`trical and electronic engineering is a wiring scheme in which,
`for example, a first device is coupled or wired to a second
`device, the second device is coupled to a third device, the third
`device is coupled to a fourth device, and so on. However, the
`connections of this daisy chain usually do not form webs or
`loop backs, as discussed above.
`In many daisy chain configurations, each of the devices,
`therefore, comprises circuits working as repeaters or ampli
`fiers to counteract the natural attenuation of the signals when
`they are transmitted from one device to the next device. In the
`case of digital signals being exchanged between the different
`components of a daisy chain, the digital signals may be trans
`ferred via an electrical bus as, for instance, in the case of
`memory devices. In these cases, however, a bus termination
`might be advisable to implement to prevent reflections and
`other disturbances of the signals. However, in the case of
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`digital signals, the digital signals may be electrically regen
`erated or recreated in each device in the daisy chain, as long
`as they are not modified.
`In other words, a signal transmitted over the bus is passed
`along through each devices interface circuits instead of being
`transmitted to all devices (simultaneously) by the devices
`sharing the same bus. Hence, for instance, transmitting a
`signal from the first device in the daisy chain to the third
`device in the daisy chain requires the second device to receive
`the signal from the first device and to forward or to regenerate
`the signal to be transmitted to the third device of the daisy
`chain.
`Especially in the field of memory devices, the first or cen
`tral device in the daisy chain is very often the memory con
`troller 110. Especially in the field of memory devices, the
`45
`communication in the direction of the memory controller or
`towards the memory controller 110 is referred to as “north
`bound' while the opposite direction, the communication
`from the memory controller to the further devices in the daisy
`chain is usually referred to as “southbound'.
`Although embodiments of the present invention are not
`limited to an application in the field of memory devices, this
`terminology is adapted in the framework of the present appli
`cation, as it allows a simple designation of a direction of the
`communication in the daisy chain or in an asynchronous latch
`chain.
`Turning back to FIG. 1, the apparatus 100 comprises four
`sub-interfaces 120a, 120b, 130a and 130b. To be more pre
`cise, sub-interface 120a is part of a reception interface of the
`apparatus 100, which is dedicated to receiving northbound
`signals on a bus 140 coupling the apparatus 100 and the
`memory controller 110. The second sub-interface 120b,
`which is dedicated for receiving northbound signal from the
`further apparatus 100' which is coupled to the apparatus 100
`by a bus 140'. Both buses 140 and 140' comprise in the
`embodiment of a memory system shown in FIG. 1, sub-bus
`structures for northbound and Southbound communications.
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`Accordingly, the apparatus 100 further comprises, apart from
`the sub-interface 120a coupled to the southbound bus struc
`ture of the bus 140, the further sub-interface 130a coupled to
`the southbound bus structure of the bus 140'. With respect to
`the northbound communication and the northbound bus
`structures of the buses 140 and 140' the apparatus 100 com
`prises apart from the interface 120b coupled to the north
`bound bus structure of the bus 140', the further sub-interface
`130b coupled to the northbound bus structure of the bus 140.
`While the two sub-interfaces 120a and 120b are dedicated
`to receiving signals southbound via the bus 140 and north
`bound via the bus 140', respectively, the sub-interfaces 130a
`and 130b are dedicated to transmitting or sending signals over
`the southbound bus structure of the bus 140' and the north
`bound bus structure of the bus 140, respectively.
`As a consequence, the two sub-interfaces 120a and 120b
`are part of a reception interface of the apparatus 100, while the
`sub-interfaces 130a and 130b are part of a transmission inter
`face of the apparatus 100. The further apparatus 100' of the
`memory system shown in FIG. 1 comprises also four Sub
`interfaces 120'a, 120'b, 130'a and 130'b, which are dedicated
`for receiving or sending signals via the buses 140' and 140",
`coupled to the further apparatus 100'. Compared to the appa
`ratus 100, the bus 140' is coupled to the sub-interfaces 120'a
`and 130'b of the further apparatus 100', while the bus 140" is
`coupled to the sub-interfaces 130'a and 120'b.
`The embodiment of the memory system shown in FIG. 1
`further comprises the memory controller 110, which is
`coupled to the embodiment of the apparatus 100 via the bus
`140. The southbound bus structure of the bus 140 is coupled
`to a sub-interface 150a of the memory controller 110 while
`the northbound bus structure of the bus 140 is coupled to a
`sub-interface 150b of the memory controller 110. The sub
`interface 150a is, therefore, adapted for transmitting or send
`ing signals via the southbound bus structure of the bus 140 to
`the sub-interface 120a of the apparatus 100, which is adapted
`for receiving the signals. Accordingly, the sub-interface 150b
`of the memory controller 110 is adapted to receiving signals
`sent via the northbound bus structure of the bus 140, provided
`by the sub-interface 130b of the apparatus 100.
`As a further option, the memory controller 110, the appa
`ratus 100 and the further apparatus 100" can be coupled to a
`signal line 160, which can, for instance, be an individual
`signal line or part of a unidirectional orbidirectional bus. The
`signal line 160 is coupled to an optional interface 170 of the
`memory controller 110 and two interfaces 180 and 180' of the
`apparatus 100 and the furtherapparatus 100' respectively. The
`signal line 160 can, for instance, be employed by the memory
`controller 110 to provide the apparatuses 100 and 100' with
`commands, data, status requests and other signals, so that the
`interfaces 180 and 180' of the apparatus 100 and the further
`apparatus 100' are capable of receiving signals from the
`memory controller. In this case, the interfaces 180 and 180"
`are also part of the reception interfaces of the apparatus 100
`and the further apparatus 100', respectively.
`The reception interface of the apparatus 100 comprises all
`interfaces, connectors, (mechanical) jumpers, Switches (DIP
`Switches) and terminals, which are designated for and/or
`capable of receiving signals. In the embodiment of a memory
`system shown in FIG. 1, the reception interface of the appa
`ratus 100 comprises the sub-interfaces 120a and 120b and, if
`present, the optional interface 180.
`Accordingly, the transmission interface, also referred to as
`the sending interface of the apparatus 100, comprises the
`sub-interfaces 130a and 130b, as well as, if the interface 180
`is capable of sending data, commands or other signals, the
`interface 180. Furthermore, the reception interface of the
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`Ex. 1033, p. 5
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`US 7,721,130 B2
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`apparatus 100 furthermore comprises, depending on the con
`crete implementation and if present, a signal line for a clock
`signal (CLK) and further, high speed or low speed buses or
`signal lines being capable of transmitting data towards the
`apparatus 100 (e.g. SM bus in case of a FBDIMM system), if
`present.
`Furthermore, the apparatus 100 can be connected to a
`further signal line 190, which is also an optional signal line.
`Via the signal line 190, which can, for instance be, coupled to
`an interface 180 of the apparatus 100, the apparatus 100 can
`furthermore be supplied with signals from further compo
`nents of memory system, not shown in FIG. 1.
`As the apparatus 100 is connectable as a latch stage into an
`asynchronous latch chain, the sub-interfaces 120a and 130a
`form an asynchronous latch chain interface for the South
`bound communication, whereas the sub-interfaces 120b and
`130b form an asynchronous latch chain interface for north
`bound communication.
`The apparatus 100, as well as the further apparatus 100',
`offers, apart from a normal mode of operation, in which the
`apparatus provides its functionality depending on its concrete
`implementation, at least a first power saving mode and a
`second power saving mode, wherein the apparatus 100 pro
`vides a first power consumption in the first power saving
`mode and a second consumption in the second power saving
`mode. The power consumption of the normal mode of opera
`tion is typically higher compared to the first power consump
`tion in the first power saving mode. Furthermore, in some
`embodiments the first power consumption is higher than the
`second power consumption of a second power saving mode.
`However, in some embodiments, the first power consumption
`and the second power consumption can be equal.
`The apparatus 100, furthermore, requires a first wake-up
`time to recover from the first power saving mode and to enter
`the normal mode of operation fully. Accordingly, the appara
`tus 100 requires a second wake-up time to recover from the
`second power saving mode and to re-establish the normal
`mode of operation fully. Depending on the embodiment of an
`apparatus 100, the first wake-up time and the second wake-up
`time can also be equal. However, in most cases, at least one of
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`the power consumptions and the wake-up times of the respec
`tive power saving modes differ. In other words, the first power
`consumption and the second power consumption or the first
`wake-up time and the second wake-up time can in principle,
`be identical or equal. However, the second power saving
`mode provides typically compared to the first power saving
`mode a smaller power consumption, while the second wake
`up time when compared to the first wake-up time of the first
`power saving mode is larger. The apparatus 100 offers, apart
`from the normal mode of operation, at least two different
`power saving modes, wherein the larger power saving capa
`bility of the respective power saving mode, compared to the
`normal mode of operation, the larger the wake-up time
`required for the apparatus 100 to re-reach to normal mode of
`operation.
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`In this context, it should be noted that neither the power
`consumption of a respective power saving mode nor the
`power saving capability of a respective power saving mode,
`compared to the normal mode of operations scales on a math
`ematical sense with the wake-up time of the respective power
`saving mode. In other words, the wake-up time and the set of
`power consumptions or power saving capabilities of the
`respective power saving mode do not necessarily follow
`(mathematical) a relation.
`The apparatus 100 is capable of being provided with a first
`signal indicating to Switch from the normal mode of operation
`to one of the at least two power saving modes, wherein the
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`power saving modes to be entered upon reception of the first
`signal is selected on the basis of the second signal. Both the
`first signal and the second signal are provided to the reception
`interface of the apparatus 100.
`Depending on the concrete implementation, each of the
`two signals can, for instance, be provided via the Southbound
`buses 140,140", 140" via the Sub-interfaces 120a, 120'a or via
`the signal line 160 coupled to the interfaces 180, 180' or via
`the signal line 190 coupled to the interface 180. In other
`words, the second signal indicative of the power saving mode
`to be switched to upon receipt of the first signal can be
`provided by the controller 110 (via an apparatus 100, 100' in
`the case of the apparatus 100 not being connected directly to
`the controller 110 and the signal not being transmitted over
`the optional signal line 160) or via the signal line 190 from an
`external component not shown in FIG.1. Also the first signal,
`instructing the apparatus 100 to enter the selected power
`saving mode, can be received from the controller 110 (via an
`apparatus 100, 100' in the case that the apparatus 100 is not
`coupled directly to the controller 110 and the signal is not
`transmitted on the signal line 160) or from an external com
`ponent via the signal line 190 not shown in FIG. 1.
`While the first signal is provided to an embodiment of an
`apparatus 100 in a concrete implementation to switch the
`apparatus in one power saving mode, the second signal is
`intended to provide the apparatus with information concern
`ing its position or location in the daisy chain of the imple
`mentation and optionally to provide the apparatus with infor
`mation concerning the length of the daisy chain. Hence, the
`power saving mode is determined by the position of the appa
`ratus on the daisy chain.
`As outlined before, the second signal intended to select the
`power saving mode, can be provided to the embodiment of an
`apparatus as a physical signal, via an access to a register via
`the SM bus in the case of the FBDIMMarchitecture as during
`a training phase via data, commands and other signals sent
`southbound to be stored in a register or memory cell of a
`memory of an embodiment of an apparatus 100.
`Depending on the implementation and the circumstances,
`the embodiments of the present invention in the form of the
`apparatus 100 can be provided with the second signal in the
`framework of start up sequence, providing the apparatus 100
`with necessary, required optional information concerning the
`normal mode of operation. For instance, in the case of a
`memory buffer, the second signal can comprise of informa
`tion concerning the position of the apparatus 100 in the asyn
`chronous latch chain, which can, for instance, be used in the
`case of a memory buffer to designate an address to at least one
`memory unit of a memory device being connected to the
`special embodiment of the apparatus in the form of a memory
`buffer. In other words, the second signal can be used in this
`example, not only to define the power saving mode, but also
`to define the basic address for at least one memory device
`being connected to an embodiment of the apparatus 100.
`The second signal can provide an embodiment of the appa
`ratus 100 with information concerning the position of the
`apparatus as a latch stage in the asynchronous latch chain,
`which might be helpful or required in the normal mode of
`operation. However, the second signal can furthermore com
`prise details and information concerning the length of the
`asynchronous latch chain, so that the power saving mode to be
`Switched to upon receipt of the first signal can be selected not
`only depending on the position of the latch stage in the asyn
`chronous latch chain, but also depending on the length of the
`asynchronous latch chain. For example, the Sub-interfaces
`120b and 130a of an embodiment of the apparatus can be
`Switched off completely in a power saving mode, if the
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`respective apparatus 100 is the last latch stage in the daisy
`chain, as no further apparatus are connected via these two
`Sub-interfaces.
`However, it should be noted that, although the apparatus is
`connectable as a latch stage to an asynchronous latch chain,
`different embodiments of an apparatus are not required to
`have two distinctive unidirectional bus structures comprised
`in the bus 140, 140' and 140". Furthermore, embodiments of
`the present invention are not limited to a single ended or
`differential transmission of signals at one or more Sub-inter
`faces or interfaces of the apparatus 100. Moreover, embodi
`ments of apparatus are not limited to a serial data transition, a
`parallel data transition, or a combination of both. Further
`more, an embodiment of the present invention is not limited to
`electrical communications. Further embodiments of the
`present invention can also comprise an optical, radio trans
`mission or other signal transmission, as long as an embodi
`ment of the present invention is connectable as a latch stage to
`an asynchronous latch chain.
`In this context, it should be noted that in the framework of
`the present invention, two components, devices or structures
`being coupled to each other could be either directly connected
`to each other or connected via a further or third component,
`structure or element. As an example, two devices can be
`coupled together, either directly (e.g., via a wire or a signal
`line) or via an additional component such as a resistor,
`repeater, transducer or another component.
`An embodiment of an apparatus 100, as shown in FIG. 1,
`offers the advantage of the power saving mode being
`Switched to, to be selected based on the second signal, which
`can, for instance, comprise information concerning the posi
`tion of the apparatus in the asynchronous latch chain. In other
`words, an embodiment of the present invention offers the
`possibility to select the power saving mode or the power
`down mode, based on the position of the apparatus as a latch
`stage in the asynchronous latch chain and optionally, depend
`ing on the length of the asynchronous latch chain. Hence, an
`embodiment of the present invention offers the possibility of
`choosing or selecting between different power saving modes
`having different (characteristical) power consumptions and
`wake-up times. Therefore, if an embodiment of the apparatus
`is integrated into a latch stage being located near or at the end
`of the asynchronous latch chain, the power saving mode with
`the lower power consumption but a greater wake-up time can
`be chosen, while an embodiment of an apparatus being inte
`grated in a latch stage close to the controller 110 can be
`maintained in a power saving mode, even in the power saving
`mode which enables a short wake-up time at the cost of a
`higher power consumption compared to a power saving mode
`with a longer wake-up time.
`Therefore, an embodiment of an apparatus offers a reduc
`tion of the power consumption, while at the same time a
`wake-up time or a response time of the system comprising
`embodiments of the apparatus can be reduced by choosing or
`selecting for each embodiment of the apparatus 100, the
`power saving mode to be switched to on receipt of the first
`signal individually.
`Before describing the second embodiment of the present
`invention in more detail, it should be noted that objects,
`structures and components with the same or similar function
`of the properties and features are denoted with the same
`reference signs. Unless explicitly noted otherwise, the
`description with respect to objects, structures and devices
`with similar or equal functional properties can be exchanged
`with respect to each other. Furthermore, in the following
`Summarizing reference signs will be used to simplify the
`description. Hence, unless specific embodiments or a specific
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`component or device is referred to, as an example an appara
`tus 100, 100' will be designated as apparatus 100.
`FIG. 2 shows a further embodiment of a memory system
`comprising several embodiments of an apparatus 100, in the
`form of a memory buffer. To be more precise, the memory
`buffer 100 is arranged on a module board 200 of a memory
`module 210, which is also referred to as a fully buffered
`DIMM (FBDIMM; DIMM-Dual Inline Memory Module).
`Each memory module 210 comprises at least one memory
`device 220, which can, for instance, be a commodity DRAM
`memory device. Typically, a memory module comprises 4, 8,
`16, or 32 individual memory devices 220. The memory mod
`ule 210, shown in FIG. 2, comprises 8 DRAM memory
`devices 220 on top and 10 on bottom totaling to 18-memory
`devices on both sides of the memory modules 210. Two
`DRAM memory devices 220 of the 18 memory devices can
`for instance be used for Error Correction, e.g., for storing
`Error Correcting Codes.
`The memory buffer 100 as an embodiment of an apparatus
`100 is coupled to the DRAM memory devices 220 of the
`memory module 210 and provides a signal buffering and
`processing between the interfaces of the commodity DRAM
`memory devices 220 and a module interface 230, which is
`coupled to the appropriate interfaces 120a, 120b, 130a, 130b
`(see FIG. 1) of the memory buffer 100. Therefore, the
`memory buffer provides a transition between the signals pro
`vided to the memory buffer 100 via the module interface 230
`and the specific signal requirement of the DRAM memory
`devices 220.
`In this context, it should be noted that although in FIG. 2,
`that DRAM memory devices 220 (DRAM=Dynamically
`Random Access Memory) are shown, in principle, other
`memory devices such as SRAM (SRAM=Static Random
`Access Memory), non-volatile memory devices (e.g., flash
`memory) and other memory devices such as ROM memory
`devices (ROM-Read Only Memory) can be employed. In the
`field of DRAM memory devices, DDRX memory devices can,
`for instance, be employed, wherein X is a positive integer
`indicating the standard according to which the DDRX
`memory devices are fabricated. Accordingly, as an example
`DDR memory devices or DDR1 memory devices (x=1), as
`well as DDR2, DDR3 or DDR4 memory devices can be
`employed as memory devices 220.
`According to the FBDIMM architecture up to 8 memory
`modules 210 or up to 8 DIMMs 210 can be arranged along
`with the memory controller of controller 110 in the daisy
`chain, formed by an asynchronous latch chain via the memory
`interface 230 (DDR2 connector with unique key). The
`memory controller 110 and the memory modules 210 are
`connected or coupled to each other via a bus 140, comprising
`10 differential signal lines (i.e., 10 differential signal pairs)
`for Southbound communication and 14 differential signal
`lines for northbound communication. The memory controller
`110, as well as the memory buffers 100 which are usually
`referred