JEDEC
`STANDARD
`
`FBDIMM Specification:
`
`DDR2 SDRAM Fully Buffered
`DIMM (FBDIMM) Design Specification
`
`JESD205
`
`March 2007
`
`SPECIAL DISCLAIMER: JEDEC has received information that
`certain patents or patent applications may be relevant to this
`standard, and, as of the publication date of this standard, no
`statements regarding an assurance or refusal to license such
`patents or patent applications have been provided.
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective
`users of the standard should act accordingly.
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 1
`
`

`

`
`
`NOTICE
`
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`JEDEC standards and publications contain material that has been prepared, reviewed, and approved
`through the JEDEC Council level and subsequently reviewed and approved by the EIA General
`Counsel.
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`JEDEC standards and publications are designed to serve the public interest through eliminating
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`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint.
`
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`standard are met.
`
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`2500 Wilson Boulevard
`Arlington, VA 22201-3834
`
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`Documents, USA and Canada (1-800-854-7179), International (303-397-7956)
`
`Printed in the U.S.A.
`All rights reserved
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 2
`
`

`

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`PLEA SE!
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`D O N ’T V IO LA TE
`TH E
`LA W !
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`
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`2500 W ilson Boulevard
`A rlington, V irginia 22201-3834
`or call (703) 907-7559
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`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 3
`
`

`

`JEDEC Standard No. 205
`
`Page 4
`
`Special Disclaimer
`
`JEDEC has received information that certain patents or patent
`applications may be relevant to this standard, and, as of the
`publication date of this standard, no statements regarding an
`assurance or refusal to license such patents or patent applications
`have been provided.
`
`
`
`
`
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective users
`of the standard should act accordingly.
`
`
`§
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 4
`
`

`

`JEDEC Standard No. 205
`
`
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`Product Description .................................................................................................................................. 9
`Product Family Attributes ...................................................................................................................... 9
`Environmental Parameters .................................................................................................................. 10
`
`Architecture ............................................................................................................................................. 11
`DIMM Connector Pin Description ........................................................................................................ 11
`DDR2 240-pin FBDIMM Pinout ........................................................................................................... 12
`Block Diagram: Raw Card Version A (x72 ECC DIMM, one physical rank of x8 DDR2 SDRAMs) .... 13
`Block Diagram: Raw Card Version B (x72 ECC DIMMs, two physical ranks of x8 DDR2 SDRAMs) . 14
`Block Diagram: Raw Card Version C (x72 ECC DIMM, one physical rank of x4 DDR2 SDRAMs) .... 15
`Block Diagram: RC Versions D,E,H,J (x72 ECC DIMMs, 2 physical ranks of x4 DDR2 SDRAMs) .... 16
`
`Component Details: ................................................................................................................................. 17
`Pin Assignments for x4 and x8 Ballouts without Support Balls ........................................................... 17
`Pin Assignments for Stacked x4 Ballout without Support Balls ........................................................... 18
`Pin Assignments for x4 and x8 Ballouts with Support Balls ................................................................ 19
`Pin Assignments for Stacked x4 Ballout with Support Balls ................................................................ 20
`Pin Assignments for x4 and x8 Ballouts with Support Balls ................................................................ 21
`Pin Assignments for Stacked x4 with Support Balls ........................................................................... 22
`Pin Assignments for x4 and x8 Ballouts with Support Balls ................................................................ 23
`Pin Assignments for Stacked x4 Ballouts with Support Balls .............................................................. 24
`Pin Assignments for x4 and x8 PCB Symbol ......................................................................................25
`Pin Assignments for Stacked x4 PCB Symbol .................................................................................... 26
`
`Component Details .................................................................................................................................. 27
`Supported SDRAM Component Maximum size for 256Mb to 4Gb, DDR2 SDRAM ........................... 27
`
`Architecture ............................................................................................................................................. 29
`Advanced Memory Buffer Pin Description .......................................................................................... 29
`Pin Assignments for the Advanced Memory Buffer (AMB) ................................................................. 31
`Critical AMB Specifications ................................................................................................................. 33
`
`DDR2 Fully Buffered DIMM Details ........................................................................................................ 34
`DDR2 SDRAM Module Configurations (Reference Designs) ............................................................. 34
`DDR2 Fully Buffered DIMM Design File Releases .............................................................................. 34
`Component Types and Placement ...................................................................................................... 36
`
`DDR2 Fully Buffered DIMM Biasing Details .......................................................................................... 42
`Common AMB Bias Detail ................................................................................................................... 42
`DDR Bias ........................................................................................................................................... 42
`DDR VREF BIAS ................................................................................................................................. 43
`PLL and Channel Bias ........................................................................................................................ 43
`Miscellaneous Bias ............................................................................................................................. 44
`BIAS Components ............................................................................................................................... 45
`
`DDR2 Fully Buffered DIMM Wiring Details ............................................................................................ 46
`Signal Groups ..................................................................................................................................... 46
`
`Revision 3.0 March 5, 2007
`
` Page 5
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 5
`
`

`

`JEDEC Standard No. 205
`
`
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`General Net Structure Routing Guidelines .......................................................................................... 46
`Explanation of Net Structure Diagrams ............................................................................................... 47
`System Clock and Data Channel Net Structures ................................................................................ 48
`Recommended Minimum Trace and Shape Separation Rules .......................................................... 51
`Dual Strip-line Differential Pairs Spacing ............................................................................................ 52
`Dual-strip-line Differential Pairs ........................................................................................................... 52
`Net Structure Routing for AMB Clock Output to SDRAM (Raw Card A) ............................................. 53
`Net Structure Routing for AMB Clock Output to SDRAM (Raw Cards B,C) ........................................ 54
`Net Structure Routing for AMB Clock Output to SDRAM (Raw Card D) ............................................. 55
`Net Structure Routing for AMB Clock Output to SDRAM (Raw Card E, H) ........................................ 56
`Net Structure Routing for AMB Clock Output to SDRAM (Raw Card J) .............................................. 58
`Net Structure Routing for DQ, CB, DQS, DQS (Raw Cards A, D, J) .................................................. 59
`Net Structure Routing for DQ, CB, DQS, DQS (Raw Card B) ............................................................. 61
`Net Structure Routing for DQ, CB, DQS, DQS (Raw Card C) ............................................................ 62
`Net Structure Routing for DQ, DQS, DQS (Raw Cards E, H; excluding DQS8/17, DQS8/17) ........... 63
`Net Structure Routing for CB, DQS8/17, DQS8/17 (Raw Cards E, H) ................................................ 64
`Net Structure Routing for Address/Command to SDRAM (Raw Card A) ............................................ 66
`Net Structure Routing for Address/Command to SDRAM (Raw Cards B, C) ..................................... 67
`Net Structure Routing for Address/Command to SDRAM (Raw Cards B, C) ..................................... 68
`Net Structure Routing for Address/Command to SDRAM (Raw Card D) ............................................ 69
`Net Structure Routing for Address/Command to SDRAM (Raw Cards E, H;
`excluding A4, A7, A10, BA0, BA2 and ODT) ............................................................................................. 70
`Net Structure Routing for A4, A7, A10, BA0, BA2, ODT to SDRAM (Raw Cards E, H) ...................... 71
`Net Structure Routing for Address/Command to SDRAM (Raw Card J; excluding ODT) ................... 74
`Net Structure Routing for ODT to SDRAM (Raw Card D) ................................................................... 75
`Net Structure Routing for ODT to SDRAM (Raw Card J) .................................................................... 76
`Net Structure Routing for Control to SDRAM (Raw Cards A, B) ......................................................... 77
`Net Structure Routing for Control to SDRAM (Raw Cards C) ............................................................. 78
`Net Structure Routing for Control to SDRAM (Raw Cards D, J) ......................................................... 79
`Net Structure Routing for Control to SDRAM (Raw Card E; excluding S0L and CKE1R) .................. 80
`Net Structure Routing for S0L and CKE1R to SDRAM (Raw Card E) ................................................ 81
`Net Structure Routing for Control to SDRAM (Raw Card H; excluding S0L, S1L and CKE1R) .......... 82
`Net Structure Routing for S0L, S1L and CKE1R to SDRAM (Raw Card H) ........................................ 83
`
`Cross Section Recommendation ........................................................................................................... 84
`Example Six Layer Stackup ................................................................................................................ 84
`Example Trace Geometries, Single Ended ......................................................................................... 85
`Example Trace Geometries, Differential ............................................................................................. 85
`Example Eight Layer Stackup ............................................................................................................. 86
` Example Ten Layer Stackup .............................................................................................................. 86
`
`Example Timing Budget .......................................................................................................................... 87
`Example DIMM Post-AMB Read Timing (PC2-4200/PC2-5300/PC2-6400)1 ..................................... 87
`Example DIMM Post-AMB Write Setup Timing (PC2-4200/PC2-5300/PC2-6400)1 ........................... 87
`Example DIMM Post-AMB Write Hold Timing (PC2-4200/PC2-5300/PC2-6400)1 ............................. 88
`Example DIMM Post-AMB CK-to-DQS Timing (PC2-4200/PC2-5300/PC2-6400)2 ........................... 88
`
`Revision 3.0 March 5, 2007
`
` Page 6
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 6
`
`

`

`JEDEC Standard No. 205
`
`
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`Example DIMM Post-AMB CK-to-C/A/Control Setup Timing (PC2-4200/PC2-5300/PC2-6400)1 ...... 88
`Example DIMM Post-AMB CK-to-C/A/Control Hold Timing (PC2-4200/PC2-5300/PC2-6400)1 ........ 89
`
`Design collateral for specific Raw Cards .............................................................................................. 91
`ODT values ......................................................................................................................................... 91
`
`Test Mode collateral ................................................................................................................................ 93
`Transparent Mode Pinout .................................................................................................................... 93
`
`Recommended trace keepout ................................................................................................................ 95
`Trace keep out area in connector area ............................................................................................... 95
`Trace keep out area in module top edge area .................................................................................... 95
`
`Vcc Power Delivery ................................................................................................................................. 97
`Effective Resistance Target 4.75 mOhm Nominal @ 23C(room temp) .............................................. 97
`Kelvin Measurement Ports .................................................................................................................. 97
`Suggested equipment requirements for measurements .................................................................... 98
`Rkelvin Measurement Diagram ........................................................................................................... 98
`
`VTT Provisions ........................................................................................................................................ 99
`Example Complementary CA Bus Current Path ................................................................................. 99
`Example FB-DIMM bridge connection requirement .......................................................................... 100
`Effective Resistance (mOhm) Max @ (room temp) for 533/667 FB-DIMMs .................................... 101
`
`(Shows typical Left Edge finger to RTTnetwork, use similar ports for right side) .................................... 102
`Typical Rkelvin Ports (Shows example R bridge measurement) ..................................................... 103
`
`Serial Presence Detect Definition ........................................................................................................ 105
`Example 512Mb 1 rank 533 4-4-4 SPD image .................................................................................. 105
`
`FBDIMM Label Format ........................................................................................................................... 110
`
`DIMM Mechanical Specifications .........................................................................................................112
`Summary of FB-DIMM Support/Development Hardware .................................................................. 113
`
`Diagnostic Sense Line .......................................................................................................................... 115
`General Concept ............................................................................................................................... 115
`
`Implementation Details ......................................................................................................................... 116
`Capacitor Pad Connection Concept .................................................................................................. 116
`Capacitor Connection Pad Size and Placement ............................................................................... 116
`Capacitor Connection Pad ................................................................................................................ 116
`Diagnostic Sense Line Routing Line Width and Spacing .................................................................. 116
`Diagnostic Sense Line Same Layer Isolation .................................................................................... 116
`Diagnostic Sense Line Adjacent Layer Isolation ............................................................................... 116
`Diagnostic Sense Line Reference Planes ......................................................................................... 117
`Diagnostic Sense Line Reference Plane Shape and Location .......................................................... 117
`
`Revision 3.0 March 5, 2007
`
` Page 7
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 7
`
`

`

`JEDEC Standard No. 205
`
`
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`Diagnostic Sense Line Layer Change VIA location ........................................................................... 117
`Routing around the DIMM Key Notch ............................................................................................... 118
`Layer Change Transition VIA Location ............................................................................................. 118
`Routing Around the DIMM Key Notch ............................................................................................... 118
`Diagnostic Sense Line Topologies, Segment Lengths, and Terminations ........................................ 118
`Preferred Topology ........................................................................................................................... 119
`Diagnostic Sense Line - Preferred Topology ....................................................................................119
`Alternate Topology (Forked Topology) .............................................................................................. 119
`Diagnostic Sense Line - Alternate Topology ..................................................................................... 120
`
`Conclusion ............................................................................................................................................. 121
`
`Revision Log .......................................................................................................................................... 124
`
`Revision 3.0 March 5, 2007
`
` Page 8
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 8
`
`

`

`JEDEC Standard No. 205
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`Product Description
`This specification defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/ PC2-
`6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules
`(DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed
`in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming
`convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400
`MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth.
`
` Product Description
`
`DIMM
`
`DRAM
`
`DRAM Clock
`
`PC2-4200
`
`PC2-5300
`
`PC2-6400
`
`DDR2-533
`
`DDR2-667
`
`DDR2-800
`
`266 MHz
`
`333 MHz
`
`400 MHz
`
`Single DIMM
`Bandwidth
`
`4266 MB/s
`
`5333 MB/s
`
`6400 MB/s
`
`Channel Clock
`
`Channel
`Transfer Rate
`
`133 MHz
`
`166 MHz
`
`200 MHz
`
`3.2 GT/s
`
`4.0 GT/s
`
`4.8 GT/s
`
`Reference design examples are included which provide an initial basis for Fully Buffered DIMM designs.
`Modifications to these reference designs may be required to meet all system timing, signal integrity, and ther-
`mal requirements for PC2-4200/PC2-5300/PC2-6400 support. All Fully Buffered DIMM implementations must
`use simulations and lab verification to ensure proper timing requirements and signal integrity in the design..
`Product Family Attributes
`
`DIMM organization
`
`x72 ECC
`
`DIMM dimensions (nominal)
`
`30.35mm (height) x 133.35mm (width) x 8.2 mm (max thickness)
` MO-256 variation AB
`30.35mm (height) x 133.35mm (width) x 8.8 mm (max thickness)
` MO-256 variation BB
`
`Pin count
`
`240
`
`SDRAMs supported
`
`256Mb, 512Mb, 1Gb, 2Gb, 4Gb
`
`Capacity
`
`Serial PD
`
`Supply voltages (nominal)
`
`256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB
`
`Consistent with JC 45
`
`min
`
`1.7
`
`1.4551
`
`typ
`
`1.8
`
`1.5
`
`max
`
`1.9
`
`(DRAM VDD/VDDQ, AMB VDDQ)
`
`1.5751
`
`(AMB VCC/VCCFBD)
`
`0.453*VDD
`
`0.5*VDD
`
`0.547*VDD
`
`(DRAM Interface VTT)
`This supply should track as 0.5 * 1.8 volt supply
`
`Buffer Interface
`
`DRAM Interface
`
`3.0
`
`3.3
`
`3.6
`
` (VDDSPD)
`
`High-speed Differential Point-to-point Link at 1.5 volt
`
`SSTL_18
`
`Note 1: Approximate DC values, refer to AMB Component Specification for actual DC and AC values and conditions.
`Note 2: Vtt range accomodates measurable offset due to complementary CA bus current paths. (See Vtt section)
` An Unloaded system should supply Vtt of 0.48*Vdd/0.52*Vdd to Dimm socket
`
`Revision 1.0 May 1, 2006
`
` Page 9
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 9
`
`

`

`JEDEC Standard No. 205
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
` Product Description
`
`The reference designs for the DIMM PCBs are called the “raw cards”, abbreviated R/C. After the designs
`have been verified in working systems, the JEDEC JC-45 committee will post registrations of these R/C
`designs to the JEDEC web site for use by the industry at large.
`
`Product Family Raw Card Types
`
`Raw Card
`
`DRAM Data
`Width
`
`# of Ranks
`
`# of DRAM
`
`A
`
`B
`
`C
`
`D
`
`E
`
`H
`
`J
`
`x8
`
`x8
`
`x4
`
`x4
`
`x4
`
`x4
`
`x4
`
`1
`
`2
`
`1
`
`2
`
`2
`
`2
`
`2
`
`9
`
`18
`
`18
`
`36
`
`36
`
`36
`
`36
`
`Z-axis
`
`planar
`
`planar
`
`planar
`
`Width x Height (mm)
`
`133.35 x 30.35
`
`133.35 x 30.35
`
`133.35 x 30.35
`
`stacked / dual die
`
`133.35 x 30.35
`
`planar
`
`planar
`
`133.35 x 30.35
`
`133.35 x 30.35
`
`stacked / dual die
`
`133.35 x 30.35
`
`Environmental Requirements
`DDR2 SDRAM Fully Buffered DIMMs are intended for use in standard office environments that have limited
`capacity for heating and air conditioning.
`Environmental Parameters
`
`Symbol
`
`TOPR
`
`HOPR
`
`TSTG
`
`HSTG
`
`Parameter
`
`Operating temperature
`
`Operating humidity (relative)
`
`Storage temperature
`
`Storage humidity (without condensation)
`
`Rating
`
`See Note
`
` 10 to 90
`
`-50 to +100
`
` 5 to 95
`
`Units
`
`Notes
`
`1
`
`2
`
`2
`
`2
`
`%
`
`°C
`
`%
`
`PBAR
` 105 to 69
`Barometric pressure (operating & storage)
`1. The designer must meet the case temperature specifications for individual module components.
`2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
`operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
`may affect reliability.
`
`K Pascal
`
`2
`
`Revision 1.0 May 1, 2006
`
` Page 10
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 10
`
`

`

`JEDEC Standard No. 205
`
`
` Architecture
`
`DDR2 SDRAM Fully Buffered DIMM Design Specification
`Architecture
`DIMM Connector Pin Description
`Pin Name
`Pin Description
`System Clock Input, positive line1
`SCK
`System Clock Input, negative line1
`Primary Northbound Data, positive lines
`Primary Northbound Data, negative lines
`Primary Southbound Data, positive lines
`Primary Southbound Data, negative lines
`Secondary Northbound Data, positive lines
`Secondary Northbound Data, negative lines
`Secondary Southbound Data, positive lines
`Secondary Southbound Data, negative lines
`Serial Presence Detect (SPD) Clock Input
`SPD Data Input / Output
`SPD Address Inputs, also used to select the DIMM number in the AMB
`Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
`VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V
`AMB reset signal
`Reserved for Future Use2
`AMB Core Power and AMB Channel Interface Power (1.5 Volt)
`
`SCK
`PN[13:0]
`PN[13:0]
`PS[9:0]
`PS[9:0]
`SN[13:0]
`SN[13:0]
`SS[9:0]
`SS[9:0]
`SCL
`SDA
`SA[2:0]
`
`VID[1:0]
`
`RESET
`RFU
`VCC
`VDD
`VTT
`VDDSPD
`VSS
`
`Count
`1
`
`1
`14
`14
`10
`10
`14
`14
`10
`10
`1
`1
`3
`
`2
`
`1
`16
`
`8
`
`24
`
`4
`
`1
`
`80
`
`1
`
`240
`
`DRAM Power and AMB DRAM I/O Power (1.8 Volt)
`DRAM Address/Command/Clock Termination Power (VDD/2)
`SPD Power
`
`Ground
`The DNU/M_Test pin provides an external connection on R/Cs A-D for testing
`the margin of Vref which is produced by a voltage divider on the module. It
`is not intended to be used in normal system operation and must not be
`connected (DNU) in a system. This test pin may have other features on future card designs
`and if it does, will be included in this specification at that time.
`1
`Total
`
`DNU/M_Test
`
`1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency
`2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
`
`Revision 1.0 March 5, 2007
`
` Page 11
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 11
`
`

`

`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`JEDEC Standard No. 205
`
`
` Architecture
`
`. D
`
`DR2 240-pin FBDIMM Pinout
`
`Pin
`#
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`Pin
`#
`
`121
`
`122
`
`123
`
`124
`
`125
`
`126
`
`Pin
`#
`
`Front
`Side
`
`PN3
`
`PN3
`VSS
`PN4
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`Pin
`#
`
`151
`
`152
`
`153
`
`154
`
`155
`
`156
`
`Back
`Side
`
`SN3
`
`SN3
`VSS
`SN4
`
`Pin
`#
`
`61
`
`62
`
`63
`
`64
`
`65
`
`66
`
`Front
`Side
`
`PN9
`
`VSS
`PN10
`
`PN10
`
`VSS
`PN11
`
`Pin
`#
`
`181
`
`182
`
`183
`
`184
`
`185
`
`186
`
`Back
`Side
`
`SN9
`
`VSS
`SN10
`
`SN10
`
`VSS
`SN11
`
`Pin
`#
`
`Front
`Side
`
`91
`
`92
`
`93
`
`94
`
`95
`
`96
`
`PS9
`
`VSS
`PS5
`
`PS5
`
`VSS
`PS6
`
`Pin
`#
`
`211
`
`212
`
`213
`
`214
`
`215
`
`216
`
`Back
`Side
`
`SS9
`VSS
`SS5
`
`SS5
`VSS
`SS6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`127
`
`128
`
`129
`
`130
`
`131
`
`132
`
`133
`
`134
`
`PN4
`VSS
`PN5
`
`PN5
`VSS
`PN13
`
`PN13
`
`VSS
`VSS
`RFU*
`
`157
`
`158
`
`159
`
`160
`
`161
`
`162
`
`163
`
`164
`
`37
`
`38
`
`39
`
`40
`
`41
`
`42
`
`43
`
`44
`
`SN4
`VSS
`SN5
`
`SN5
`VSS
`SN13
`
`SN13
`VSS
`VSS
`RFU*
`
`67
`
`68
`
`69
`
`70
`
`71
`
`72
`
`73
`
`PN11
`
`VSS
`
`187
`
`188
`
`KEY
`
`VSS
`
`PS0
`
`PS0
`VSS
`PS1
`
`189
`
`190
`
`191
`
`192
`
`193
`
`SN11
`
`VSS
`
`VSS
`
`SS0
`
`SS0
`VSS
`SS1
`
`97
`
`98
`
`99
`
`100
`
`101
`
`102
`
`103
`
`104
`
`PS6
`VSS
`PS7
`
`PS7
`VSS
`PS8
`
`217
`
`218
`
`219
`
`220
`
`221
`
`222
`
`223
`
`224
`
`SS6
`VSS
`SS7
`
`SS7
`VSS
`SS8
`
`Front
`Side
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VDD
`VSS
`VCC
`VCC
`VSS
`VCC
`VCC
`VSS
`VTT
`VID1
`
`15
`
`16
`
`135
`
`136
`
`Back
`Side
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VDD
`VSS
`VCC
`VCC
`VSS
`VCC
`VCC
`VSS
`VTT
`VID0
`
`138
`
`139
`
`18
`
`19
`
`20
`
`21
`
`22
`
`17 RESET 137 DNU/M_Test
`VSS
`VSS
`RFU**
`RFU**
`RFU**
`RFU**
`VSS
`VSS
`PN0
`SN0
`
`140
`
`141
`
`142
`
`23
`
`PN0
`
`143
`
`RFU*
`VSS
`VSS
`SN12
`
`SN12
`VSS
`SN6
`
`45
`
`46
`
`47
`
`48
`
`49
`
`50
`
`51
`
`52
`
`53
`
`RFU*
`VSS
`VSS
`PN12
`
`PN12
`VSS
`PN6
`
`165
`
`166
`
`167
`
`168
`
`169
`
`170
`
`171
`
`172
`
`173
`
`74
`
`75
`
`76
`
`77
`
`78
`
`79
`
`80
`
`81
`
`82
`
`PS1
`VSS
`PS2
`
`PS2
`VSS
`PS3
`
`194
`
`195
`
`196
`
`197
`
`198
`
`199
`
`200
`
`201
`
`202
`
`SS1
`VSS
`SS2
`
`SS2
`VSS
`SS3
`
`SS3
`VSS
`SS4
`
`105
`
`106
`
`107
`
`108
`
`109
`
`110
`
`111
`
`112
`
`113
`
`SS8
`VSS
`RFU**
`RFU**
`VSS
`SCK
`
`225
`
`226
`
`227
`
`228
`
`229
`
`230
`
`231
`
`232
`
`233
`
`PS8
`VSS
`RFU**
`RFU**
`VSS
`VDD
`VDD
`VSS
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VTT
`SA2
`
`SDA
`
`SCL
`
`SCK
`VSS
`VDD
`VDD
`VDD
`VSS
`VDD
`VDD
`VTT
`VDDSPD
`
`SA0
`
`SA1
`
`234
`
`235
`
`236
`
`237
`
`238
`
`239
`
`240
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`VSS
`PN1
`
`PN1
`VSS
`PN2
`
`PN2
`VSS
`
`144
`
`145
`
`146
`
`147
`
`148
`
`149
`
`150
`
`SN0
`VSS
`SN1
`
`SN1
`VSS
`SN2
`
`SN2
`VSS
`
`PN6
`VSS
`PN7
`
`PN7
`VSS
`PN8
`
`PN8
`VSS
`PN9
`
`174
`
`175
`
`176
`
`177
`
`178
`
`179
`
`180
`
`54
`
`55
`
`56
`
`57
`
`58
`
`59
`
`60
`
`SN6
`VSS
`SN7
`
`SN7
`VSS
`SN8
`
`SN8
`VSS
`SN9
`
`PS3
`VSS
`PS4
`
`PS4
`VSS
`VSS
`RFU*
`
`RFU*
`VSS
`VSS
`PS9
`
`83
`
`84
`
`85
`
`86
`
`87
`
`88
`
`89
`
`90
`
`203
`
`204
`
`205
`
`206
`
`207
`
`208
`
`209
`
`210
`
`SS4
`VSS
`VSS
`RFU*
`
`RFU*
`VSS
`VSS
`SS9
`
`114
`
`115
`
`116
`
`117
`
`118
`
`119
`
`120
`
`RFU = Reserved Future Use.
`* These pin positions are reserved for forwarded clocks to be used in future module implementations
`** These pin positions are reserved for future architecture flexibility
`1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13,
`PS9/PS9, SS9/SS9
`
`Page 12
`
`Revision1.0 March 5, 2007
`
`Samsung Electronics Co., Ltd.
`Ex. 1028, p. 12
`
`

`

`DDR2 SDRAM Fully Buffered DIMM Design Specification
`
`JEDEC Standard No. 205
`
`
`
`
`Block Diagram: Raw Card Version A (x72 ECC DIMM, one physical rank of x8 DDR2 SDRAMs)
`
`DQS4
`DQS4
`DQS13
`
`DQS5
`DQS5
`DQS14
`
`DQS6
`DQS6
`DQS15
`
`DQS7
`DQS7
`DQS16
`
`DQS8
`DQS8
`DQS17
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D4
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D5
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D6
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D7
`
`DQS
`
`DQS
`
`CS
`
`NU/
`RDQS
`D8
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`VTT
`VCC
`VDDSPD
`
`SDA
`
`VDD
`
`VREF
`VSS
`
`VTT
`
`Serial PD
`
`WP
`
`A1 A2
`A0
`SA0 SA1 SA2
`
`Terminators
`AMB
`
`SPD, AMB
`
`D0-D8, AMB
`
`D0-D8
`
`D0-D8,SPD,AMB
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D0
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D1
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D2
`
`DQS
`
`CS DQS
`
`NU/
`RDQS
`D3
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM/
`RDQS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`SN0-SN13
`SN0-SN13
`SS0-SS9
`SS0-SS9
`S0 -> CS (all SDRAMs)
`CKE0 -> CKE (all SDRAMs)
`
`ODT -> ODT (all SDRAMs)
`BA0-BA2 (all SDRAMs)
`A0-A15 (all SDRAMs)
`RAS (all SDRAMs)
`CAS (all SDRAMs)
`WE (all SDRAMs)
`CK/CK (all SDRAMs)
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`AMB
`
`S0
`
`DQS0
`DQS0
`DQS9
`
`DQS1
`DQS1
`DQS10
`
`DQS2
`DQS2
`DQS11
`
`DQS3
`DQS3
`DQS12
`
`PN0-PN13
`PN0-PN13
`PS0-PS9
`PS0-PS9
`
`