PTO/SB/14 (07-07)
`Approved for use through 06/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
`Application Data Sheet 37 CFR 1.76
`
`Attorney Docket Number
`
`NETL.040C1
`
`Application Number
`
`Title of Invention
`
`NON-VOLATILE MEMORY MODULE
`
`The application data sheet is part of the provisional or nonprovisional application for which it is being submitted. The following form contains the
`bibliographic data arranged in a format specified by the United States Patent and Trademark Office as outlined in 37 CFR 1.76.
`This document may be completed electronically and submitted to the Office in electronic format using the Electronic Filing System (EFS) or the
`document may be printed and included in a paper filed application.
`
`Secrecy Order 37 CFR 5.2
`O Portions or all of the application associated with this Application Data Sheet may fall under a Secrecy Order pursuant to
`37 CFR 5.2 (Paper filers only. Applications that fall under Secrecy Order may not be filed electronically.)
`Applicant Information:
`
`Applicant 1
`Applicant Authority ®Inventor
`Prefix Given Name
`
`°Legal Representative under 35 U.S.C. 117
`
`°Party of Interest under 35 U.S.C. 118
`
`Middle Name
`
`Family Name
`
`Suffix
`
`Chen
`Chi-She
`Residence Information (Select One) ® US Residency O Non US Residency O Active US Military Service
`US
`CA
`Country of Residenc4
`State/Province
`City Walnut
`
`Citizenship under 37 CFR 1.41(0
`Mailing Address of Applicant:
`Address 1
`
`944 Crystal Water Lane
`
`TW
`
`Address 2
`
`City
`
`Walnut
`
`State/Province
`
`CA
`
`Postal Code
`
`91789
`
`Country US
`
`Applicant 2
`Applicant Authority ® Inventor
`Prefix Given Name
`
`()Legal Representative under 35 U.S.C. 117
`
`I °Party of Interest under 35 U.S.C. 118
`
`Middle Name
`
`Family Name
`
`Suffix
`
`Solomon
`C.
`Jeffrey
`Residence Information (Select One) ® US Residency O Non US Residency O Active US Military Service
`US
`CA
`Country of Residenc4
`State/Province
`City
`Irvine
`
`Citizenship under 37 CFR 1.41(b)
`Mailing Address of Applicant:
`6 Silver Fir
`Address 1
`
`US
`
`Address 2
`
`City
`
`Irvine
`
`State/Province
`
`CA
`
`Postal Code
`
`92604
`
`Country US
`
`Applicant 3
`Applicant Authority ®Inventor
`Prefix Given Name
`
`°Legal Representative under 35 U.S.C. 117
`
`°Party of Interest under 35 U.S.C. 118
`
`Middle Name
`
`Family Name
`
`Suffix
`
`Scott
`Milton
`H.
`Residence Information (Select One) CD US Residency O Non US Residency O Active US Military Service
`US
`Irvine
`State/Province
`CA
`Country of Residenc4
`City
`
`EFS Web 2.2.2
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 1
`
`

`

`PTO/SB/14 (07-07)
`Approved for use through 06/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`NETL.040C1
`Attorney Docket Number
`
`Application Data Sheet 37 CFR 1.76
`
`Application Number
`
`Title of Invention
`
`NON-VOLATILE MEMORY MODULE
`
`Citizenship under 37 CFR 1.41(bi
`Mailing Address of Applicant:
`49 Statehouse Place
`Address 1
`
`US
`
`Address 2
`
`City
`
`Irvine
`
`State/Province
`
`CA
`
`Postal Code
`
`92602
`
`Counti4 US
`
`Applicant 4
`Applicant Authority (D Inventor OLegal Representative under 35 U.S.C. 117
`Family Name
`Middle Name
`Prefix Given Name
`
`°Party of Interest under 35 U.S.C. 118
`
`Suffix
`
`Jayesh
`Residence Information (Select One) ® US Residency
`State/Province
`Cerritos
`City
`
`Bhakta
`0 Non US Residency 0 Active US Military Service
`US
`Country of Residenc4
`CA
`
`Citizenship under 37 CFR 1.41(bi
`Mailing Address of Applicant:
`12220 Rose Street
`Address 1
`
`US
`
`Address 2
`
`City
`
`Cerritos
`
`State/Province
`
`CA
`
`Counti4 US
`90703
`Postal Code
`All Inventors Must Be Listed - Additional Inventor Information blocks
`generated within this form by selecting the Add button.
`
`may
`
`be
`
`Add
`
`Correspondence Information:
`Enter either Customer Number or complete the Correspondence Information section below.
`For further information see 37 CFR 1.33(a).
`
`q An Address is being provided for the correspondence Information of this application.
`
`Customer Number
`
`20995
`
`Email Address
`
`efiling@kmob.com
`
`Application Information:
`
`Add Email
`
`Remove Email
`
`Title of the Invention
`Attorney Docket Number NETL.040C1
`Nonprovisional
`
`Application Type
`
`NON-VOLATILE MEMORY MODULE
`
`Subject Matter
`
`Utility
`
`Suggested Class (if any)
`
`Suggested Technology Center (if any)
`
`Small Entity Status Claimed
`
`q
`
`Sub Class (if any)
`
`Total Number of Drawing Sheets (if any)
`
`12
`
`Suggested Figure for Publication (if any) 1
`
`EFS Web 2.2.2
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 2
`
`

`

`PTO/SB/14 (07-07)
`Approved for use through 06/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`NETL.040C1
`Attorney Docket Number
`
`Application Data Sheet 37 CFR 1.76
`
`Application Number
`
`Title of Invention
`
`NON-VOLATILE MEMORY MODULE
`
`Publication Information:
`El Request Early Publication (Fee required at time of Request 37 CFR 1.219)
`Request Not to Publish. I hereby request that the attached application not be published under 35 U.S.
`[zi C. 122(b) and certify that the invention disclosed in the attached application has not and will not be the subject of
`an application filed in another country, or under a multilateral international agreement, that requires publication at
`eighteen months after filing.
`
`Representative Information:
`
`Representative information should be provided for all practitioners having a power of attorney in the application. Providing
`this information in the Application Data Sheet does not constitute a power of attorney in the application (see 37 CFR 1.32).
`Enter either Customer Number or
`complete
`the Representative Name
`section below.
`If both
`are completed the Customer Number will be used for the Representative Information during processing.
`
`sections
`
`Please Select One:
`
`0 Customer Number
`
`0 US Patent Practitioner
`
`0
`
`Limited Recognition (37 CFR 11.9)
`
`Customer Number
`
`20995
`
`Domestic Benefit/National Stage Information:
`This section allows for the applicant to either claim benefit under 35 U.S.C. 119(e), 120, 121, or 365(c) or indicate National Stage
`entry from a PCT application. Providing this information in the application data sheet constitutes the specific reference required by
`35 U.S.C. 119(e) or 120, and 37 CFR 1.78(a)(2) or CFR 1.78(a)(4), and need not otherwise be made part of the specification.
`
`Prior Application Status Pending
`
`Remove
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD)
`
`Continuation of
`
`12/131873
`
`2008-06-02
`
`Prior Application Status Expired
`
`Remove
`
`Application Number
`
`Continuity Type
`
`Prior Application Number
`
`Filing Date (YYYY-MM-DD)
`
`1 2/1 31 873
`
`60/941586
`Additional Domestic Benef t/National Stage Data may be generated within this form
`by selecting the Add button.
`
`non provisional of
`
`2007-06-01
`
`Foreign Priority Information:
`This section allows for the applicant to claim benefit of foreign priority and to identify any prior foreign application for which priority is
`not claimed. Providing this information in the application data sheet constitutes the claim for priority as required by 35 U.S.C. 119(b)
`and 37 CFR 1.55(a).
`
`Application Number
`
`Country'
`
`Parent Filing Date (YYYY-MM-DD)
`
`Additional Foreign Priority Data may be generated within this form by selecting the
`Add button.
`
`Remove
`Priority Claimed
`
`0 Yes C) No
`
`EFS Web 2.2.2
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 3
`
`

`

`PTO/SB/14 (07-07)
`Approved for use through 06/30/2010. OMB 0651-0032
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB control number.
`
`Application Data Sheet 37 CFR 1.76
`
`Attorney Docket Number
`
`NETL.040C1
`
`Application Number
`
`Title of Invention
`
`NON-VOLATILE MEMORY MODULE
`
`Assignee Information:
`Providing this information in the application data sheet does not substitute for compliance with any requirement of part 3 of Title 37
`of the CFR to have an assignment recorded in the Office.
`
`Assignee 1
`If the Assignee is an Organization check here.
`
`a
`
`Organization Name
`
`Netlist, Inc.
`Mailing Address Information:
`
`51 Discovery
`
`Suite 150
`
`Irvine
`
`Address 1
`
`Address 2
`
`City
`
`Country' US
`
`Phone Number
`
`Email Address
`
`State/Province
`
`CA
`
`Postal Code
`
`Fax Number
`
`92618
`
`Additional Assignee Data may be generated within this form by selecting the Add
`button.
`
`Signature:
`A signature of the applicant or representative is required in accordance with 37 CFR 1.33 and 10.18. Please see 37
`CFR 1.4(d) for the for
`_ :the
`signatur .
`
`Signature
`
`/
`
`j
`
`Date (YYYY-MM-DD) 2008-09-29
`
`First Name
`
`Bruce
`
`Last Na
`
`Itchkawitz
`
`Registration Number
`
`47677
`
`This collection of information is required by 37 CFR 1.76. The information is required to obtain or retain a benefit by the public which
`is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This
`collection is estimated to take 23 minutes to complete, including gathering, preparing, and submitting the completed application data
`sheet form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to
`complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and
`Trademark Office, U.S. Department of Commerce, P.O. Box 1450, Alexandria, VA 22313-1450. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450.
`
`EFS Web 2.2.2
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 4
`
`

`

`NETL.040C1
`
`PATENT
`
`NON-VOLATILE MEMORY MODULE
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`This application is a continuation of U.S. Patent Application No.
`[0001]
`12/131,873, filed June 2, 2008, which claims the benefit of U.S. Provisional Application No.
`60/941,586, filed June 1, 2007. Each of these applications is incorporated in its entirety by
`
`reference herein.
`
`BACKGROUND
`
`[0002]
`random-access memory (DRAM) devices mounted on a printed circuit board (PCB). These
`
`Certain types of memory modules comprise a plurality of dynamic
`
`memory modules are typically mounted in a memory slot or socket of a computer system
`(e.g., a server system or a personal computer) and are accessed by the computer system to
`
`provide volatile memory to the computer system.
`
`[0003]
`
`Volatile memory generally maintains stored information only when it is
`
`powered. Batteries have been used to provide power to volatile memory during power
`
`failures or interruptions. However, batteries may require maintenance, may need to be
`
`replaced, are not environmentally friendly, and the status of batteries can be difficult to
`
`monitor.
`
`[0004]
`
`Non-volatile memory can generally maintain stored information while
`
`power is not applied to the non-volatile memory. In certain circumstances, it can therefore be
`
`useful to backup volatile memory using non-volatile memory.
`
`SUMMARY
`
`[0005]
`
`In certain embodiments, a memory system coupled to a computer system is
`
`provided which includes a volatile memory subsystem, a non-volatile memory subsystem,
`
`and a controller operatively coupled to the non-volatile memory subsystem. The memory
`system can also include at least one circuit configured to selectively operatively decouple the
`
`controller from the volatile memory subsystem.
`
`[0006]
`
`In some embodiments, a power module for providing a plurality of
`
`voltages to a memory system is described. The power module includes non-volatile and
`
`volatile memory, and the plurality of voltages include at least a first voltage and a second
`
`-1-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 5
`
`

`

`voltage. The power module of certain embodiments includes an input providing a third
`
`voltage to the power module and a voltage conversion element configured to provide the
`
`second voltage to the memory system. The power module also includes a first power element
`
`configured to selectively provide a fourth voltage to the conversion element. The power
`
`module further includes a second power element configured to selectively provide a fifth
`
`voltage to the conversion element. The power module can be configured to selectively
`
`provide the first voltage to the memory system either from the conversion element or from
`
`the input.
`
`[0007]
`
`The power module can be configured to be operated in at least three states
`
`in certain embodiments. In a first state, the first voltage is provided to the memory system
`
`from the input and the fourth voltage is provided to the conversion element from the first
`
`power element. In a second, state the fourth voltage is provided to the conversion element
`
`from the first power element and the first voltage is provided to the memory system from the
`
`conversion element. In a third state, the fifth voltage is provided to the conversion element
`
`from the second power element and the first voltage is provided to the memory system from
`
`the conversion element.
`
`[0008]
`
`A method of providing a first voltage and a second voltage to a memory
`
`system including volatile and non-volatile memory subsystems is provided in certain
`
`embodiments. The method includes, during a first condition, providing the first voltage to
`
`the memory system from an input power supply and providing the second voltage to the
`
`memory system from a first power subsystem. The method further includes detecting a
`
`second condition and, during the second condition, providing the first voltage and the second
`
`voltage to the memory system from the first power subsystem. The method also includes
`
`charging a second power subsystem and detecting a third condition. During the third
`
`condition, the method includes providing the first voltage and the second voltage to the
`
`memory system from the second power subsystem.
`
`[0009]
`
`In certain embodiments, a method is provided for controlling a memory
`
`system operatively coupled to a host system and which includes a volatile memory subsystem
`
`and a non-volatile memory subsystem. The method can include operating the volatile
`
`memory subsystem at a first frequency when the memory system is in a first mode of
`
`-2-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 6
`
`

`

`operation in which data is communicated between the volatile memory subsystem and the
`host system. In certain embodiments, the method further includes operating the non-volatile
`memory subsystem at a second frequency when the memory system is in a second mode of
`operation in which data is communicated between the volatile memory subsystem and the
`
`non-volatile memory subsystem. The method can also include operating the volatile memory
`
`subsystem at a third frequency when the memory system is in the second mode of operation,
`
`the third frequency less than the first frequency.
`
`[0010]
`
`In certain embodiments, a method is provided for controlling a memory
`
`system operatively coupled to a host system. The memory system includes a volatile memory
`
`subsystem and a non-volatile memory subsystem.
`
`In certain embodiments, the method
`
`includes communicating data words between the volatile memory subsystem and the host
`
`system when the memory system is in a first mode of operation. The method can further
`
`include transferring data words from the volatile memory subsystem to the non-volatile
`
`memory subsystem when the memory system is in a second mode of operation. Transferring
`
`each data word can include storing a first portion of the data word in a buffer, storing a
`
`second portion of the data word in the buffer, and writing the entire data word from the buffer
`
`to the non-volatile memory subsystem.
`
`[0011]
`
`A memory system operatively coupled to a host system is provided in
`
`certain embodiments. The memory system can include a volatile memory subsystem and a
`
`non-volatile memory subsystem comprising at least 100 percent more storage capacity than
`
`does the volatile memory subsystem. The memory system includes a controller operatively
`
`coupled to the volatile memory subsystem and operatively coupled to the non-volatile
`
`memory subsystem, the controller configured to allow data to be communicated between the
`
`volatile memory subsystem and the host system when the memory system is operating in a
`
`first state and to allow data to be communicated between the volatile memory subsystem and
`
`the non-volatile memory subsystem when the memory system is operating in a second state.
`
`[0012]
`
`A method of controlling a memory system operatively coupled to a host
`
`system is provided in certain embodiments. The memory system includes a volatile memory
`
`subsystem and a non-volatile memory subsystem. The method can include communicating
`
`data between the volatile memory subsystem and the host system when the memory system is
`
`-3-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 7
`
`

`

`in a first mode of operation. The method of certain embodiments further includes storing a
`first copy of data from the volatile memory subsystem to the non-volatile memory subsystem
`at a first time when the memory system is in a second mode of operation. The method may
`further include restoring the first copy of data from the non-volatile memory subsystem to the
`volatile memory subsystem and erasing the first copy of data from the non-volatile memory
`subsystem. In certain embodiments, the method also includes storing a second copy of data
`from the volatile memory subsystem to the non-volatile memory subsystem at a second time
`when the memory system is in the second mode of operation, wherein storing the second
`copy begins before the first copy is completely erased from the non-volatile memory
`
`subsystem.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0013]
`
`Figure 1 is a block diagram of an example memory system compatible
`
`with certain embodiments described herein.
`
`[0014]
`
`Figure 2 is a block diagram of an example memory module with ECC
`
`(error-correcting code) having a volatile memory subsystem with nine volatile memory
`
`elements and a non-volatile memory subsystem with five non-volatile memory elements in
`
`accordance with certain embodiments described herein.
`
`[0015]
`
`Figure 3 is a block diagram of an example memory module having a
`
`microcontroller unit and logic element integrated into a single device in accordance with
`
`certain embodiments described herein.
`
`[0016]
`
`Figures 4A-4C schematically illustrate example embodiments of memory
`
`systems having volatile memory subsystems comprising registered dual in-line memory
`
`modules in accordance with certain embodiments described herein.
`
`[0017]
`
`Figure 5 schematically illustrates an example power module of a memory
`
`system in accordance with certain embodiments described herein.
`
`[0018]
`
`Figure 6 is a flowchart of an example method of providing a first voltage
`
`and a second voltage to a memory system including volatile and non-volatile memory
`
`subsystems.
`
`-4-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 8
`
`

`

`[0019]
`
`Figure 7 is a flowchart of an example method of controlling a memory
`
`system operatively coupled to a host system and which includes at least 100 percent more
`
`storage capacity in non-volatile memory than in volatile memory.
`
`[0020]
`
`Figure 8 schematically illustrates an example clock distribution topology
`
`of a memory system in accordance with certain embodiments described herein.
`
`[0021]
`
`Figure 9 is a flowchart of an example method of controlling a memory
`
`system operatively coupled to a host system, the method including operating a volatile
`
`memory subsystem at a reduced rate in a back-up mode.
`
`[0022].
`
`Figure 10 schematically illustrates an example topology of a connection to
`
`transfer data slices from two DRAM segments of a volatile memory subsystem of a memory
`
`system to a controller of the memory system.
`
`[0023]
`
`Figure 11 is a flowchart of an example method of controlling a memory
`
`system operatively coupled to a host system, the method including backing up and/or
`
`restoring a volatile memory subsystem in slices.
`
`DETAILED DESCRIPTION
`
`[0024]
`
`Certain embodiments described herein include a memory system which
`
`can communicate with a host system such as a disk controller of a computer system. The
`
`memory system can include volatile and non-volatile memory, and a controller. The
`
`controller backs up the volatile memory using the non-volatile memory in the event of a
`
`trigger condition. Trigger conditions can include, for example, a power failure, power
`
`reduction, request by the host system, etc. In order to power the system in the event of a
`
`power failure or reduction, the memory system can include a secondary power source which
`
`does not comprise a battery and may include, for example, a capacitor or capacitor array.
`
`[0025]
`
`In certain embodiments, the memory system can be configured such that
`
`the operation of the volatile memory is not adversely affected by the non-volatile memory or
`
`by the controller when the volatile memory is interacting with the host system. For example,
`
`one or more isolation devices may isolate the non-volatile memory and the controller from
`
`the volatile memory when the volatile memory is interacting with the host system and may
`
`allow communication between the volatile memory and the non-volatile memory when the
`
`data of the volatile memory is being restored or backed-up. This configuration generally
`
`-5-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 9
`
`

`

`protects the operation of the volatile memory when isolated while providing backup and
`
`restore capability in the event of a trigger condition, such as a power failure.
`
`[0026]
`
`In certain embodiments described herein, the memory system includes a
`
`power module which provides power to the various components of the memory system from
`
`different sources based on a state of the memory system in relation to a trigger condition
`
`(e.g., a power failure). The power module may switch the source of the power to the various
`
`components in order to efficiently provide power in the event of the power failure. For
`
`example, when no power failure is detected, the power module may provide power to certain
`
`components, such as the volatile memory, from system power while charging a secondary
`
`power source (e.g., a capacitor array). In the event of a power failure or other trigger
`
`condition, the power module may power the volatile memory elements using the previously
`
`charged secondary power source.
`
`[0027]
`
`In certain embodiments, the power module transitions relatively smoothly
`
`from powering the volatile memory with system power to powering it with the secondary
`
`power source. For example, the memory system may power volatile memory with a third
`
`power source from the time the memory system detects that power failure is likely to occur
`
`until the time the memory system detects that the power failure has actually occurred.
`
`[0028]
`
`In certain embodiments, the volatile memory system can be operated at a
`
`reduced frequency during backup and/or restore operations which can improve the efficiency
`
`of the system and save power.
`
`In some embodiments, during backup and/or restore
`
`operations, the volatile memory communicates with the non-volatile memory by writing
`
`and/or reading data words in bit-wise slices instead of by writing entire words at once. In
`
`certain embodiments, when each slice is being written to or read from the volatile memory
`
`the unused slice(s) of volatile memory is not active, which can reduce the power consumption
`
`of the system.
`
`[0029]
`
`In yet other embodiments, the non-volatile memory can include at least
`
`100 percent more storage capacity than the volatile memory. This configuration can allow
`
`the memory system to efficiently handle subsequent trigger conditions.
`
`[0030]
`
`Figure 1 is a block diagram of an example memory system 10 compatible
`
`with certain embodiments described herein. The memory system 10 can be coupled to a host
`
`-6-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 10
`
`

`

`computer system and can include a volatile memory subsystem 30, a non-volatile memory
`subsystem 40, and a controller 62 operatively coupled to the non-volatile memory subsystem
`
`40.
`
`In certain embodiments, the memory system 10 includes at least one circuit 52
`
`configured to selectively operatively decouple the controller 62 from the volatile memory
`
`subsystem 30.
`
`[0031]
`
`In certain embodiments, the memory system 10 comprises a memory
`
`module. The memory system 10 may comprise a printed-circuit board (PCB) 20. In certain
`
`embodiments, the memory system 10 has a memory capacity of 512-MB, 1-GB, 2-GB, 4-GB,
`
`or 8-GB. Other volatile memory capacities are also compatible with certain embodiments
`
`described herein. In certain embodiments, the memory system 10 has a non-volatile memory
`
`capacity of 512-MB, 1-GB, 2-GB, 4-GB, 8-GB, 16-GB, or 32-GB. Other non-volatile
`
`memory capacities are also compatible with certain embodiments described herein.
`
`In
`
`addition, memory systems 10 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits,
`
`64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits), are compatible with
`
`embodiments described herein. In certain embodiments, the PCB 20 has an industry-standard
`
`form factor. For example, the PCB 20 can have a low profile (LP) form factor with a height
`
`of 30 millimeters and a width of 133.35 millimeters. In certain other embodiments, the PCB
`
`20 has a very high profile (VHP) form factor with a height of 50 millimeters or more. In
`
`certain other embodiments, the PCB 20 has a very low profile (VLP) form factor with a
`
`height of 18.3 millimeters. Other form factors including, but not limited to, small-outline
`
`(SO-DIMM), unbuffered (UDIMM), registered (RDIMM), fully-buffered (FBDIMM), mini-
`
`DIMM, mini-RDIMM, VLP mini-DIMM, micro-DIMM, and SRAM DIMM are also
`
`compatible with certain embodiments described herein. For example, in other embodiments,
`
`certain non-DIMM form factors are possible such as, for example, single in-line memory
`
`module (SIMM), multi-media card (MMC), and small computer system interface (SCSI).
`
`[0032]
`
`In certain preferred embodiments, the memory system 10 is in electrical
`
`communication with the host system. In other embodiments, the memory system 10 may
`
`communicate with a host system using some other type of communication, such as, for
`
`example, optical communication. Examples of host systems include, but are not limited to,
`
`blade servers, 1U servers, personal computers (PCs), and other applications in which space is
`
`-7-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 11
`
`

`

`constrained or limited. The memory system 10 can be in communication with a disk
`
`controller of a computer system, for example. The PCB 20 can comprise an interface 22 that
`
`is configured to be in electrical communication with the host system (not shown). For
`
`example, the interface 22 can comprise a plurality of edge connections which fit into a
`
`corresponding slot connector of the host system. The interface 22 of certain embodiments
`
`provides a conduit for power voltage as well as data, address, and control signals between the
`
`memory system 10 and the host system. For example, the interface 22 can comprise a
`
`standard 240-pin DDR2 edge connector.
`
`[0033]
`
`The volatile memory subsystem 30 comprises a plurality of volatile
`
`memory elements 32 and the non-volatile memory subsystem 40 comprises a plurality of
`
`non-volatile memory elements 42. Certain embodiments described herein advantageously
`
`provide non-volatile storage via the non-volatile memory subsystem 40 in addition to high-
`
`performance (e.g., high speed) storage via the volatile memory subsystem 30. In certain
`
`embodiments, the first plurality of volatile memory elements 32 comprises two or more
`
`dynamic random-access memory (DRAM) elements. Types of DRAM elements 32
`
`compatible with certain embodiments described herein include, but are not limited to, DDR,
`
`DDR2, DDR3, and synchronous DRAM (SDRAM). For example, in the block diagram of
`
`Figure 1, the first memory bank 30 comprises eight 64Mx8 DDR2 SDRAM elements 32.
`
`The volatile memory elements 32 may comprise other types of memory elements such as
`
`static random-access memory (SRAM). In addition, volatile memory elements 32 having bit
`
`widths of 4, 8, 16, 32, as well as other bit widths, are compatible with certain embodiments
`
`described herein. Volatile memory elements 32 compatible with certain embodiments
`
`described herein have packaging which include, but are not limited to, thin small-outline
`
`package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (µBGA),
`
`mini-BGA (mBGA), and chip-scale packaging (CSP).
`
`[0034]
`
`In certain embodiments, the second plurality of non-volatile memory
`
`elements 42 comprises one or more flash memory elements. Types of flash memory elements
`
`42 compatible with certain embodiments described herein include, but are not limited to,
`
`NOR flash, NAND flash, ONE-NAND flash, and multi-level cell (MLC). For example, in
`
`the block diagram of Figure 1, the second memory bank 40 comprises 512 MB of flash
`
`-8-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 12
`
`

`

`memory organized as four 128Mbx8 NAND flash memory elements 42. In addition, non-
`volatile memory elements 42 having bit widths of 4, 8, 16, 32, as well as other bit widths, are
`compatible with certain embodiments described herein. Non-volatile memory elements 42
`compatible with certain embodiments described herein have packaging which include, but are
`not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA
`(FBGA), micro-BGA (µEGA), mini-BGA (mBGA), and chip-scale packaging (CSP).
`
`[0035]
`(error-correcting code) having a volatile memory subsystem 30 with nine volatile memory
`
`Figure 2 is a block diagram of an example memory module 10 with ECC
`
`elements 32 and a non-volatile memory subsystem 40 with five non-volatile memory
`
`elements 42 in accordance with certain embodiments described herein. The additional
`
`memory element 32 of the first memory bank 30 and the additional memory element 42 of
`
`the second memory bank 40 provide the ECC capability. In certain other embodiments, the
`
`volatile memory subsystem 30 comprises other numbers of volatile memory elements 32
`
`(e.g., 2, 3, 4, 5, 6, 7, more than 9).
`
`In certain embodiments, the non-volatile memory
`
`subsystem 40 comprises other numbers of non-volatile memory elements 42 (e.g., 2, 3, more
`
`than 5).
`
`[0036]
`
`Referring to Figure 1, in certain embodiments, the logic element 70
`
`comprises a field-programmable gate array (FPGA).
`
`In certain embodiments, the logic
`
`element 70 comprises an FPGA available from Lattice Semiconductor Corporation which
`
`includes an internal flash. In certain other embodiments, the logic element 70 comprises an
`
`FPGA available from another vendor. The internal flash can improve the speed of the
`
`memory system 10 and save physical space. Other types of logic elements 70 compatible
`
`with certain embodiments described herein include, but are not limited to, a programmable-
`
`logic device (PLD), an application-specific integrated circuit (ASIC), a custom-designed
`
`semiconductor device, a complex programmable logic device (CPLD).
`
`In certain
`
`embodiments, the logic element 70 is a custom device. In certain embodiments, the logic
`
`element 70 comprises various discrete electrical elements, while in certain other
`
`embodiments, the logic element 70 comprises one or more integrated circuits. Figure 3 is a
`
`block diagram of an example memory module 10 having a microcontroller unit 60 and logic
`
`element 70 integrated into a single controller 62 in accordance with certain embodiments
`
`-9-
`
`Samsung Electronics Co., Ltd.
`Ex. 1007, p. 13
`
`

`

`described herein. In certain embodiments, the controller 62 includes one or more other
`components. For example, in one embodiment, an FPGA without an internal flash is used
`and the controller 62 includes a separate flash mem