UTILITY APPLICATION
`
`Attorney Docket No.: NETL.040A
`First Named Inventor: to be determined
`Title: NON-VOLATILE MEMORY MODULE
`
`Direct all correspondence to Customer No.: 20995
`
`Date: June 2, 2008
`Page 1
`
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`The following enclosures are transmitted herewith to be filed in the patent application of:
`
`Inventor(s):
`to be determined
`1.
`
`APPLICATION:
`
`(X) Specification in 40 pages.
`
`(X) Drawings in 12 sheets.
`
`CONTINUITY INFORMATION:
`
`Application
`This Application
`
`Relationship
`Non-Provisional of
`
`Parent App. No.
`60/941,586
`
`Filing Date
`6/01/2007
`
`Status
`closed
`
`Reference to prior domestic applications is made in the:
`
`(X) Specification.
`
`OTHER APPLICATION PARTS:
`
`FILING FEES:
`
`(X) The total fees will be paid at a later date.
`
`Bruce S. Itchkawitz
`Registration No. 47,677
`Attorney of Record
`Customer No. 20,995
`(949) 760-0404
`
`5458952
`060208
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 1
`
`

`

`NETL.040A
`
`PATENT
`
`NON-VOLATILE MEMORY MODULE
`
`CROSS-REFERENCE TO RELATED APPLICATIONS
`
`[0001]
`
`The present application claims the benefit of priority from U.S.
`
`Provisional Application No. 60/941,586, filed June 1, 2007, which is incorporated in its
`
`entirety by reference herein.
`
`BACKGROUND
`
`[0002]
`
`Certain types of memory modules comprise a plurality of dynamic
`
`random-access memory (DRAM) devices mounted on a printed circuit board (PCB). These
`
`memory modules are typically mounted in a memory slot or socket of a computer system
`
`(e.g., a server system or a personal computer) and are accessed by the computer system to
`
`provide volatile memory to the computer system.
`
`[0003]
`
`Volatile memory generally maintains stored information only when it is
`
`powered. Batteries have been used to provide power to volatile memory during power
`
`failures or interruptions. However, batteries may require maintenance, may need to be
`
`replaced, are not environmentally friendly, and the status of batteries can be difficult to
`
`monitor.
`
`[0004]
`
`Non-volatile memory can generally maintain stored information while
`
`power is not applied to the non-volatile memory. In certain circumstances, it can therefore be
`
`useful to backup volatile memory using non-volatile memory.
`
`SUMMARY
`
`[0005]
`
`In certain embodiments, a memory system coupled to a computer system is
`
`provided which includes a volatile memory subsystem, a non-volatile memory subsystem,
`
`and a controller operatively coupled to the non-volatile memory subsystem. The memory
`
`system can also include at least one circuit configured to selectively operatively decouple the
`
`controller from the volatile memory subsystem.
`
`[0006]
`
`In some embodiments, a power module for providing a plurality of
`
`voltages to a memory system is described. The power module includes non-volatile and
`
`volatile memory, and the plurality of voltages include at least a first voltage and a second
`
`voltage. The power module of certain embodiments includes an input providing a third
`
`-1-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 2
`
`

`

`voltage to the power module and a voltage conversion element configured to provide the
`
`second voltage to the memory system. The power module also includes a first power element
`
`configured to selectively provide a fourth voltage to the conversion element. The power
`
`module further includes a second power element configured to selectively provide a fifth
`
`voltage to the conversion element. The power module can be configured to selectively
`
`provide the first voltage to the memory system either from the conversion element or from
`
`the input.
`
`[0007]
`
`The power module can be configured to be operated in at least three states
`
`in certain embodiments. In a first state, the first voltage is provided to the memory system
`
`from the input and the fourth voltage is provided to the conversion element from the first
`
`power element. In a second, state the fourth voltage is provided to the conversion element
`
`from the first power element and the first voltage is provided to the memory system from the
`
`conversion element. In a third state, the fifth voltage is provided to the conversion element
`
`from the second power element and the first voltage is provided to the memory system from
`
`the conversion element.
`
`[0008]
`
`A method of providing a first voltage and a second voltage to a memory
`
`system including volatile and non-volatile memory subsystems is provided in certain
`
`embodiments. The method includes, during a first condition, providing the first voltage to
`
`the memory system from an input power supply and providing the second voltage to the
`
`memory system from a first power subsystem. The method further includes detecting a
`
`second condition and, during the second condition, providing the first voltage and the second
`
`voltage to the memory system from the first power subsystem. The method also includes
`
`charging a second power subsystem and detecting a third condition. During the third
`
`condition, the method includes providing the first voltage and the second voltage to the
`
`memory system from the second power subsystem.
`
`[0009]
`
`In certain embodiments, a method is provided for controlling a memory
`
`system operatively coupled to a host system and which includes a volatile memory subsystem
`
`and a non-volatile memory subsystem. The method can include operating the volatile
`
`memory subsystem at a first frequency when the memory system is in a first mode of
`
`operation in which data is communicated between the volatile memory subsystem and the
`
`-2-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 3
`
`

`

`host system. In certain embodiments, the method further includes operating the non-volatile
`
`memory subsystem at a second frequency when the memory system is in a second mode of
`
`operation in which data is communicated between the volatile memory subsystem and the
`
`non-volatile memory subsystem. The method can also include operating the volatile memory
`
`subsystem at a third frequency when the memory system is in the second mode of operation,
`
`the third frequency less than the first frequency.
`
`In certain embodiments, a method is provided for controlling a memory
`[0010]
`system operatively coupled to a host system. The memory system includes a volatile memory
`In certain embodiments, the method
`
`subsystem and a non-volatile memory subsystem.
`includes communicating data words between the volatile memory subsystem and the host
`system when the memory system is in a first mode of operation. The method can further
`include transferring data words from the volatile memory subsystem to the non-volatile
`memory subsystem when the memory system is in a second mode of operation. Transferring
`each data word can include storing a first portion of the data word in a buffer, storing a
`second portion of the data word in the buffer, and writing the entire data word from the buffer
`
`to the non-volatile memory subsystem.
`A memory system operatively coupled to a host system is provided in
`[0011]
`certain embodiments. The memory system can include a volatile memory subsystem and a
`non-volatile memory subsystem comprising at least 100 percent more storage capacity than
`does the volatile memory subsystem. The memory system includes a controller operatively
`coupled to the volatile memory subsystem and operatively coupled to the non-volatile
`memory subsystem, the controller configured to allow data to be communicated between the
`volatile memory subsystem and the host system when the memory system is operating in a
`first state and to allow data to be communicated between the volatile memory subsystem and
`the non-volatile memory subsystem when the memory system is operating in a second state.
`A method of controlling a memory system operatively coupled to a host
`
`[0012]
`
`system is provided in certain embodiments. The memory system includes a volatile memory
`
`subsystem and a non-volatile memory subsystem. The method can include communicating
`
`data between the volatile memory subsystem and the host system when the memory system is
`
`in a first mode of operation. The method of certain embodiments further includes storing a
`
`-3-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 4
`
`

`

`first copy of data from the volatile memory subsystem to the non-volatile memory subsystem
`
`at a first time when the memory system is in a second mode of operation. The method may
`
`further include restoring the first copy of data from the non-volatile memory subsystem to the
`
`volatile memory subsystem and erasing the first copy of data from the non-volatile memory
`subsystem. In certain embodiments, the method also includes storing a second copy of data
`
`from the volatile memory subsystem to the non-volatile memory subsystem at a second time
`
`when the memory system is in the second mode of operation, wherein storing the second
`
`copy begins before the first copy is completely erased from the non-volatile memory
`
`subsystem.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0013]
`
`Figure 1 is a block diagram of an example memory system compatible
`
`with certain embodiments described herein.
`Figure 2 is a block diagram of an example memory module with ECC
`[0014]
`(error-correcting code) having a volatile memory subsystem with nine volatile memory
`elements and a non-volatile memory subsystem with five non-volatile memory elements in
`accordance with certain embodiments described herein.
`Figure 3 is a block diagram of an example memory module having a
`[0015]
`microcontroller unit and logic element integrated into a single device in accordance with
`
`certain embodiments described herein.
`Figures 4A-4C schematically illustrate example embodiments of memory
`[0016]
`systems having volatile memory subsystems comprising registered dual in-line memory
`modules in accordance with certain embodiments described herein.
`
`[0017]
`
`Figure 5 schematically illustrates an example power module of a memory
`
`system in accordance with certain embodiments described herein.
`Figure 6 is a flowchart of an example method of providing a first voltage
`[0018]
`and a second voltage to a memory system including volatile and non-volatile memory
`
`subsystems.
`
`[0019]
`system operatively coupled to a host system and which includes at least 100 percent more
`
`Figure 7 is a flowchart of an example method of controlling a memory
`
`storage capacity in non-volatile memory than in volatile memory.
`
`-4-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 5
`
`

`

`[0020]
`
`Figure 8 schematically illustrates an example clock distribution topology
`
`of a memory system in accordance with certain embodiments described herein.
`
`[0021]
`
`Figure 9 is a flowchart of an example method of controlling a memory
`
`system operatively coupled to a host system, the method including operating a volatile
`
`memory subsystem at a reduced rate in a back-up mode.
`
`[0022]
`
`Figure 10 schematically illustrates an example topology of a connection to
`
`transfer data slices from two DRAM segments of a volatile memory subsystem of a memory
`
`system to a controller of the memory system.
`Figure 11 is a flowchart of an example method of controlling a memory
`[0023]
`system operatively coupled to a host system, the method including backing up and/or
`
`restoring a volatile memory subsystem in slices.
`
`DETAILED DESCRIPTION
`
`Certain embodiments described herein include a memory system which
`[0024]
`can communicate with a host system such as a disk controller of a computer system. The
`memory system can include volatile and non-volatile memory, and a controller. The
`controller backs up the volatile memory using the non-volatile memory in the event of a
`trigger condition. Trigger conditions can include, for example, a power failure, power
`reduction, request by the host system, etc. In order to power the system in the event of a
`power failure or reduction, the memory system can include a secondary power source which
`does not comprise a battery and may include, for example, a capacitor or capacitor array.
`In certain embodiments, the memory system can be configured such that
`[0025]
`the operation of the volatile memory is not adversely affected by the non-volatile memory or
`by the controller when the volatile memory is interacting with the host system. For example,
`one or more isolation devices may isolate the non-volatile memory and the controller from
`the volatile memory when the volatile memory is interacting with the host system and may
`allow communication between the volatile memory and the non-volatile memory when the
`data of the volatile memory is being restored or backed-up. This configuration generally
`protects the operation of the volatile memory when isolated while providing backup and
`
`restore capability in the event of a trigger condition, such as a power failure.
`
`-5-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 6
`
`

`

`[0026]
`
`In certain embodiments described herein, the memory system includes a
`
`power module which provides power to the various components of the memory system from
`
`different sources based on a state of the memory system in relation to a trigger condition
`
`(e.g., a power failure). The power module may switch the source of the power to the various
`
`components in order to efficiently provide power in the event of the power failure. For
`
`example, when no power failure is detected, the power module may provide power to certain
`
`components, such as the volatile memory, from system power while charging a secondary
`
`power source (e.g., a capacitor array). In the event of a power failure or other trigger
`
`condition, the power module may power the volatile memory elements using the previously
`
`charged secondary power source.
`
`In certain embodiments, the power module transitions relatively smoothly
`[0027]
`from powering the volatile memory with system power to powering it with the secondary
`power source. For example, the memory system may power volatile memory with a third
`power source from the time the memory system detects that power failure is likely to occur
`until the time the memory system detects that the power failure has actually occurred.
`In certain embodiments, the volatile memory system can be operated at a
`[0028]
`reduced frequency during backup and/or restore operations which can improve the efficiency
`In some embodiments, during backup and/or restore
`
`of the system and save power.
`operations, the volatile memory communicates with the non-volatile memory by writing
`and/or reading data words in bit-wise slices instead of by writing entire words at once. In
`certain embodiments, when each slice is being written to or read from the volatile memory
`the unused slice(s) of volatile memory is not active, which can reduce the power consumption
`
`of the system.
`
`[0029]
`
`In yet other embodiments, the non-volatile memory can include at least
`
`100 percent more storage capacity than the volatile memory. This configuration can allow
`
`the memory system to efficiently handle subsequent trigger conditions.
`
`[0030]
`
`Figure 1 is a block diagram of an example memory system 10 compatible
`
`with certain embodiments described herein. The memory system 10 can be coupled to a host
`
`computer system and can include a volatile memory subsystem 30, a non-volatile memory
`
`subsystem 40, and a controller 62 operatively coupled to the non-volatile memory subsystem
`
`-6-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 7
`
`

`

`40.
`
`In certain embodiments, the memory system 10 includes at least one circuit 52
`
`configured to selectively operatively decouple the controller 62 from the volatile memory
`
`subsystem 30.
`
`[0031]
`
`In certain embodiments, the memory system 10 comprises a memory
`
`module. The memory system 10 may comprise a printed-circuit board (PCB) 20. In certain
`
`embodiments, the memory system 10 has a memory capacity of 512-MB, 1-GB, 2-GB, 4-GB,
`
`or 8-GB. Other volatile memory capacities are also compatible with certain embodiments
`
`described herein. In certain embodiments, the memory system 10 has a non-volatile memory
`
`capacity of 512-MB, 1-GB, 2-GB, 4-GB, 8-GB, 16-GB, or 32-GB. Other non-volatile
`
`memory capacities are also compatible with certain embodiments described herein.
`
`In
`
`addition, memory systems 10 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits,
`
`64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits), are compatible with
`
`embodiments described herein. In certain embodiments, the PCB 20 has an industry-standard
`
`form factor. For example, the PCB 20 can have a low profile (LP) form factor with a height
`
`of 30 millimeters and a width of 133.35 millimeters. In certain other embodiments, the PCB
`
`20 has a very high profile (VHP) form factor with a height of 50 millimeters or more. In
`
`certain other embodiments, the PCB 20 has a very low profile (VLP) form factor with a
`height of 18.3 millimeters. Other form factors including, but not limited to, small-outline
`(SO-DIMM), unbuffered (UDIMM), registered (RDIMM), fully-buffered (FBDIMM), mini-
`
`DIMM, mini-RDIMM, VLP mini-DIMM, micro-DIMM, and SRAM DIMM are also
`
`compatible with certain embodiments described herein. For example, in other embodiments,
`
`certain non-DIMM form factors are possible such as, for example, single in-line memory
`
`module (SIMM), multi-media card (MMC), and small computer system interface (SCSI).
`
`[0032]
`
`In certain preferred embodiments, the memory system 10 is in electrical
`
`communication with the host system. In other embodiments, the memory system 10 may
`
`communicate with a host system using some other type of communication, such as, for
`
`example, optical communication. Examples of host systems include, but are not limited to,
`
`blade servers, 1U servers, personal computers (PCs), and other applications in which space is
`
`constrained or limited. The memory system 10 can be in communication with a disk
`
`controller of a computer system, for example. The PCB 20 can comprise an interface 22 that
`
`-7-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 8
`
`

`

`is configured to be in electrical communication with the host system (not shown). For
`
`example, the interface 22 can comprise a plurality of edge connections which fit into a
`
`corresponding slot connector of the host system. The interface 22 of certain embodiments
`
`provides a conduit for power voltage as well as data, address, and control signals between the
`
`memory system 10 and the host system. For example, the interface 22 can comprise a
`
`standard 240-pin DDR2 edge connector.
`
`[0033]
`
`The volatile memory subsystem 30 comprises a plurality of volatile
`
`memory elements 32 and the non-volatile memory subsystem 40 comprises a plurality of
`
`non-volatile memory elements 42. Certain embodiments described herein advantageously
`
`provide non-volatile storage via the non-volatile memory subsystem 40 in addition to high-
`
`performance (e.g., high speed) storage via the volatile memory subsystem 30. In certain
`
`embodiments, the first plurality of volatile memory elements 32 comprises two or more
`
`dynamic random-access memory (DRAM) elements. Types of DRAM elements 32
`compatible with certain embodiments described herein include, but are not limited to, DDR,
`DDR2, DDR3, and synchronous DRAM (SDRAM). For example, in the block diagram of
`Figure 1, the first memory bank 30 comprises eight 64Mx8 DDR2 SDRAM elements 32.
`The volatile memory elements 32 may comprise other types of memory elements such as
`static random-access memory (SRAM). In addition, volatile memory elements 32 having bit
`widths of 4, 8, 16, 32, as well as other bit widths, are compatible with certain embodiments
`described herein. Volatile memory elements 32 compatible with certain embodiments
`described herein have packaging which include, but are not limited to, thin small-outline
`package (TSOP), ball-grid-array (BGA), fine-pitch BGA (FBGA), micro-BGA (µBGA),
`
`mini-BGA (mBGA), and chip-scale packaging (CSP).
`
`[0034]
`
`In certain embodiments, the second plurality of non-volatile memory
`
`elements 42 comprises one or more flash memory elements. Types of flash memory elements
`
`42 compatible with certain embodiments described herein include, but are not limited to,
`
`NOR flash, NAND flash, ONE-NAND flash, and multi-level cell (MLC). For example, in
`
`the block diagram of Figure 1, the second memory bank 40 comprises 512 MB of flash
`
`memory organized as four 128Mbx8 NAND flash memory elements 42. In addition, non-
`
`volatile memory elements 42 having bit widths of 4, 8, 16, 32, as well as other bit widths, are
`
`-8-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 9
`
`

`

`compatible with certain embodiments described herein. Non-volatile memory elements 42
`
`compatible with certain embodiments described herein have packaging which include, but are
`
`not limited to, thin small-outline package (TSOP), ball-grid-array (BGA), fine-pitch BGA
`
`(FBGA), micro-BGA (µBGA), mini-BGA (mBGA), and chip-scale packaging (CSP).
`
`[0035]
`
`Figure 2 is a block diagram of an example memory module 10 with ECC
`
`(error-correcting code) having a volatile memory subsystem 30 with nine volatile memory
`
`elements 32 and a non-volatile memory subsystem 40 with five non-volatile memory
`
`elements 42 in accordance with certain embodiments described herein. The additional
`
`memory element 32 of the first memory bank 30 and the additional memory element 42 of
`
`the second memory bank 40 provide the ECC capability. In certain other embodiments, the
`
`volatile memory subsystem 30 comprises other numbers of volatile memory elements 32
`
`(e.g., 2, 3, 4, 5, 6, 7, more than 9).
`
`In certain embodiments, the non-volatile memory
`
`subsystem 40 comprises other numbers of non-volatile memory elements 42 (e.g., 2, 3, more
`
`than 5).
`
`[0036]
`
`Referring to Figure 1, in certain embodiments, the logic element 70
`
`comprises a field-programmable gate array (FPGA).
`
`In certain embodiments, the logic
`
`element 70 comprises an FPGA available from Lattice Semiconductor Corporation which
`
`includes an internal flash. In certain other embodiments, the logic element 70 comprises an
`
`FPGA available from another vendor. The internal flash can improve the speed of the
`
`memory system 10 and save physical space. Other types of logic elements 70 compatible
`
`with certain embodiments described herein include, but are not limited to, a programmable-
`
`logic device (PLD), an application-specific integrated circuit (ASIC), a custom-designed
`
`semiconductor device, a complex programmable logic device (CPLD).
`
`In certain
`
`embodiments, the logic element 70 is a custom device. In certain embodiments, the logic
`
`element 70 comprises various discrete electrical elements, while
`
`in certain other
`
`embodiments, the logic element 70 comprises one or more integrated circuits. Figure 3 is a
`
`block diagram of an example memory module 10 having a microcontroller unit 60 and logic
`
`element 70 integrated into a single controller 62 in accordance with certain embodiments
`
`described herein.
`
`In certain embodiments, the controller 62 includes one or more other
`
`components. For example, in one embodiment, an FPGA without an internal flash is used
`
`-9-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 10
`
`

`

`and the controller 62 includes a separate flash memory component which stores configuration
`
`information to program the FPGA.
`
`[0037]
`
`In certain embodiments, the at least one circuit 52 comprises one or more
`
`switches coupled to the volatile memory subsystem 30, to the controller 62, and to the host
`
`computer (e.g., via the interface 22, as schematically illustrated by Figures 1-3). The one or
`
`more switches are responsive to signals (e.g., from the controller 62) to selectively
`
`operatively decouple the controller 62 from the volatile memory subsystem 30 and to
`
`selectively operatively couple the controller 62 to the volatile memory subsystem 30. In
`
`addition, in certain embodiments, the at least one circuit 52 selectively operatively couples
`
`and decouples the volatile memory subsystem 30 and the host system.
`
`[0038]
`
`In certain embodiments, the volatile memory subsystem 30 can comprise a
`
`registered DIMM subsystem comprising one or more registers 160 and a plurality of DRAM
`elements 180, as schematically illustrated by Figure 4A. In certain such embodiments, the at
`least one circuit 52 can comprise one or more switches 172 coupled to the controller 62 (e.g.,
`logic element 70) and to the volatile memory subsystem 30 which can be actuated to couple
`and decouple the controller 62 to and from the volatile memory subsystem 30, respectively.
`The memory system 10 further comprises one or more switches 170 coupled to the one or
`more registers 160 and to the plurality of DRAM elements 180 as schematically illustrated by
`Figure 4A. The one or more switches 170 can be selectively switched, thereby selectively
`operatively coupling the volatile memory subsystem 30 to the host system 150. In certain
`
`other embodiments, as schematically illustrated by Figure 4B, the one or more switches 174
`
`are also coupled to the one or more registers 160 and to a power source 162 for the one or
`more registers 160. The one or more switches 174 can be selectively switched to turn power
`
`on or off to the one or more registers 160, thereby selectively operatively coupling the
`
`volatile memory subsystem 30 to the host system 150. As schematically illustrated by Figure
`
`4C, in certain embodiments the at least one circuit 52 comprises a dynamic on-die
`
`termination (ODT) 176 circuit of the logic element 70. For example, the logic element 70
`
`can comprise a dynamic ODT circuit 176 which selectively operatively couples and
`
`decouples the logic element 70 to and from the volatile memory subsystem 30, respectively.
`
`In addition, and similar to the example embodiment of Figure 4A described above, the one or
`
`-10-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 11
`
`

`

`more switches 170 can be selectively switched, thereby selectively operatively coupling the
`
`volatile memory subsystem 30 to the host system 150.
`
`[0039]
`
`Certain embodiments described herein utilize the non-volatile memory
`
`subsystem 40 as a flash "mirror" to provide backup of the volatile memory subsystem 30 in
`
`the event of certain system conditions. For example, the non-volatile memory subsystem 40
`may backup the volatile memory subsystem 30 in the event of a trigger condition, such as, for
`example, a power failure or power reduction or a request from the host system. In one
`
`embodiment, the non-volatile memory subsystem 30 holds intermediate data results in a
`noisy system environment when the host computer system is engaged in a long computation.
`In certain embodiments, a backup may be performed on a regular basis. For example, in one
`embodiment, the backup may occur every millisecond in response to a trigger condition. In
`certain embodiments, the trigger condition occurs when the memory system 10 detects that
`the system voltage is below a certain threshold voltage. For example, in one embodiment,
`In certain
`the threshold voltage is 10 percent below a specified operating voltage.
`embodiments, a trigger condition occurs when the voltage goes above a certain threshold
`In some
`value, such as, for example, 10 percent above a specified operating voltage.
`embodiments, a trigger condition occurs when the voltage goes below a threshold or above
`another threshold. In various, a backup and/or restore operation may occur in reboot and/or
`
`non-reboot trigger conditions.
`As schematically illustrated by Figures 1 and 2, in certain embodiments,
`[0040]
`the controller 62 may comprise a microcontroller unit (MCU) 60 and a logic element 70. In
`certain embodiments, the MCU 60 provides memory management for the non-volatile
`memory subsystem 40 and controls data transfer between the volatile memory subsystem 30
`and the non-volatile memory subsystem 40. The MCU 60 of certain embodiments comprises
`a 16-bit microcontroller, although other types of microcontrollers are also compatible with
`certain embodiments described herein. As schematically illustrated by Figures 1 and 2, the
`logic element 70 of certain embodiments is in electrical communication with the non-volatile
`
`memory subsystem 40 and the MCU 60. The logic element 70 can provide signal level
`
`translation between the volatile memory elements 32 (e.g., 1.8V SSTL-2 for DDR2 SDRAM
`
`elements) and the non-volatile memory elements 42 (e.g., 3V TTL for NAND flash memory
`
`-11-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 12
`
`

`

`elements). In certain embodiments, the logic element 70 is also programmed to perform
`
`address/address translation between the volatile memory subsystem 30 and the non-volatile
`
`memory subsystem 40. In certain preferred embodiments, 1-NAND type flash are used for
`
`the non-volatile memory elements 42 because of their superior read speed and compact
`
`structure.
`
`[0041]
`
`The memory system 10 of certain embodiments is configured to be
`
`operated in at least two states. The at least two states can comprise a first state in which the
`
`controller 62 and the non-volatile memory subsystem 40 are operatively decoupled (e.g.,
`
`isolated) from the volatile memory subsystem 30 by the at least one circuit 52 and a second
`state in which the volatile memory subsystem 30 is operatively coupled to the controller 62 to
`allow data to be communicated between the volatile memory subsystem 30 and the non-
`volatile memory subsystem 40 via the controller 62. The memory system 10 may transition
`from the first state to the second state in response to a trigger condition, such as when the
`memory system 10 detects that there is a power interruption (e.g., power failure or reduction)
`
`or a system hang-up.
`The memory system 10 may further comprise a voltage monitor 50. The
`[0042]
`voltage monitor circuit 50 monitors the voltage supplied by the host system via the interface
`22. Upon detecting a low voltage condition (e.g., due to a power interruption to the host
`system), the voltage monitor circuit 50 may transmit a signal to the controller 62 indicative of
`the detected condition. The controller 62 of certain embodiments responds to the signal from
`the voltage monitor circuit 50 by transmitting a signal to the at least one circuit 52 to
`operatively couple the controller to the volatile memory system 30, such that the memory
`system 10 enters the second state. For example, the voltage monitor 50 may send a signal to
`the MCU 60 which responds by accessing the data on the volatile memory system 30 and by
`
`executing a write cycle on the non-volatile memory subsystem 40. During this write cycle,
`
`data is read from the volatile memory subsystem 30 and is transferred to the non-volatile
`
`memory subsystem 40 via the MCU 60. In certain embodiments, the voltage monitor circuit
`
`50 is part of the controller 62 (e.g., part of the MCU 60) and the voltage monitor circuit 50
`
`transmits a signal to the other portions of the controller 62 upon detecting a power threshold
`
`condition.
`
`-12-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 13
`
`

`

`[0043]
`
`The isolation or operational decoupling of the volatile memory subsystem
`
`30 from the non-volatile memory subsystem in the first state can preserve the integrity of the
`
`operation of the memory system 10 during periods of operation in which signals (e.g., data)
`are transmitted between the host system and the volatile memory subsystem 30. For
`example, in one embodiment during such periods of operation, the controller 62 and the non-
`volatile memory subsystem 40 do not add a significant capacitive load to the volatile memory
`system 30 when the memory system 10 is in the first state. In certain such embodiments, the
`capacitive load of the controller 62 and the non-volatile memory subsystem 40 do not
`significantly affect the signals propagating between the volatile memory subsystem 30 and
`the host system. This can be particularly advantageous in relatively high-speed memory
`systems where loading effects can be significant. In one preferred embodiment, the at least
`one circuit 52 comprises an FSA1208 Low-Power, Eight-Port, Hi-Speed Isolation Switch
`from Fairchild Semiconductor. In other embodiments, the at least one circuit 52 comprises
`
`other types of isolation devices.
`Power may be supplied to the volatile memory subsystem 30 from a first
`[0044]
`power supply (e.g., a system power supply) when the memory system 10 is in the first state
`and from a second power supply 80 when the memory system 10 is in the second state. In
`certain embodiments, the memory system 10 is in the first