Trials@uspto.gov
`571-272-7822
`
`
` Paper No. 47
`Entered: October 19, 2023
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`__________
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)1
`
`__________
`
`Record of Oral Hearing
`Held: September 11, 2023
`__________
`
`Before: PATRICK M. BOUCHER, JON M. JURGOVAN, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`
`
`
`
`1
`
`
` We exercise our discretion to issue one Order to be filed in each of the
`above-identified cases. The parties, are not authorized to use this style
`heading in any subsequent papers.
`
`
`571-272-7822
`
`
` Paper No. 47
`Entered: October 19, 2023
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`__________
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)1
`
`__________
`
`Record of Oral Hearing
`Held: September 11, 2023
`__________
`
`Before: PATRICK M. BOUCHER, JON M. JURGOVAN, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`
`
`
`
`1
`
`
` We exercise our discretion to issue one Order to be filed in each of the
`above-identified cases. The parties, are not authorized to use this style
`heading in any subsequent papers.
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`THEODORE W. CHANDLER, ESQ.
`Baker Botts LLP
`101 California Street
`Suite 3200
`San Francisco, California 94111-5802
`415-291-6259
`ted.chandler@bakerbotts.com
`
`JUAN C. YAQUIAN, ESQ.
`Winston & Strawn LLP
`800 Capitol Street
`Suite 2400
`Houston, Texas 77002-2925
`713-651-2645
`jyaquian@winston.com
`
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`JASON SHEASBY, ESQ.
`HONG ANNITA ZHONG, ESQ.
`JONATHAN LINDSAY, ESQ.
`Irell & Manella LLP
`1800 Avenue of the Stars
`Suite 900
`Los Angeles, California 90067
`310-203-7096
`jsheasby@irell.com
`hzhong@irell.com
`jlindsay@irell.com
`
`
`
`
`The above-entitled matter came on for hearing Monday,
`
`September 11, 2023, commencing at 1:03 p.m. EDT, via Video-conference.
`
`
`
`
`
`
`
`
`
`
`2
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`P R O C E E D I N G S
`
`1:03 p.m.
`
`
`
`JUDGE JURGOVAN: This is the trial hearing for the following
`
`cases: IPR2022-00996 concerning U.S. Patent No. 11,016,918 B2 and
`
`IPR2022-00999 concerning U.S. Patent No. 11,232,054 B2.
`
`
`
`The date is September 11, 2023. The time is 1:00 p.m. Eastern. On
`
`the panel today are APJ’s Patrick Boucher, Daniel Galligan, and myself, Jon
`
`Jurgovan. Who will be speaking on behalf of the Petitioner in this case?
`
`
`
`MR. CHANDLER: Morning, Your Honor. Ted Chandler from Baker
`
`Botts on behalf of the Petitioner, Samsung Electronics Co. Limited.
`
`
`
`Also on the line is counsel from Micron. They’re in an understudy
`
`position and won’t be arguing.
`
`
`
`
`
`But I believe they would like to introduce themselves this morning.
`
`MR. YAQUIAN: Hi, Your Honors. This is Juan Yaquian here for
`
`Micron.
`
`
`
`JUDGE JURGOVAN: Thank you. Who will be speaking on behalf
`
`of the Patent Owner today?
`
`
`
`MS. ZHONG: My name is Anita Zhong from Irell & Manella. Also
`
`on the line, my colleagues, Mr. Jason Sheasby and Mr. Jonathan Lindsay.
`
`Mr. Sheasby will be doing the presentation today.
`
`
`
`JUDGE JURGOVAN: Thank you. As stated in the hearing order,
`
`each party will have up to ninety minutes to present their arguments for both
`
`cases.
`
`
`
`Since Petitioner bears the burden of proving its case by a
`
`preponderance of the evidence, Petitioner will begin followed by the Patent
`
`Owner.
`
`
`
`
`
`
`3
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Each party may reserve time for rebuttal limited to the opposing
`
`party’s presentation.
`
`
`
`As you address the demonstratives, papers, and exhibits in the record,
`
`please identify them clearly by page number and a paper or exhibit n umber
`
`so that the record will be clear what you’re pointing out in your
`
`presentations.
`
`
`
`Please identify yourselves as you begin speaking so that the court
`
`reporter will know who you are.
`
`
`
`After the hearing, please remain on the line in case the court reporter
`
`has any questions to ask you of terms that may have been used in t he hearing
`
`or other matters that may not have been understood.
`
`
`
`
`
`As this hearing is public, third parties may be listening on the line.
`
`None of the information in this hearing has been designated as
`
`confidential.
`
`
`
`If for some reason you need to discuss confidential information,
`
`please let the judges know in advance so we can address the matter.
`
`
`
`If at any time you experience technical difficulties that impair your
`
`ability to represent your client, please alert us and contact the number given
`
`you to resolve the issue.
`
`
`
`Petitioner has filed motions to exclude in each case. The parties may
`
`devote some of their allotted time to address the motions to exclude.
`
`
`
`However, it is unlikely we will rule on the motions to exclude today.
`
`Do the parties have any questions before we begin?
`
`
`
`MR. SHEASBY: Yes, Your Honors. Jason Sheasby for the Patent
`
`Owner.
`
`
`
`
`
`
`4
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`I did want to discuss the specific page of an exhibit that’s in the
`
`record.
`
`
`
`Do I have Your Honor’s permission to use the share function to
`
`discuss that page?
`
`
`
`
`
`
`
`
`
`(Simultaneous speaking.)
`
`JUDGE JURGOVAN: Yes, you do.
`
`MR. SHEASBY: Thank you.
`
`JUDGE JURGOVAN: Share is fine. So we’ll begin with the
`
`Petitioner’s presentation. How much time would you like to reserve for
`
`rebuttal?
`
`
`
`
`
`MR. CHANDLER: Thirty minutes, please.
`
`JUDGE JURGOVAN: Thirty minutes. Okay. You may proceed
`
`when you are ready.
`
`
`
`MR. CHANDLER: All right. I’m sharing on the screen our
`
`demonstratives marked as Exhibit 1079.
`
`
`
`Are you able to see the demonstratives and are you able to hear me all
`
`right?
`
`
`
`
`
`JUDGE JURGOVAN: Yes, we are.
`
`MR. CHANDLER: Thank you. So starting on slide 5, this provides
`
`an overview of the ’918 patent.
`
`
`
`As highlighted in yellow in the upper left, the ’918 patent claims
`
`priority back to an application filed on June 2nd, 2008.
`
`
`
`Our contention is that the claims of the ’918 and ’054 patents are not
`
`entitled to the earlier provisional filing date of June 1st, 2007.
`
`
`
`Patent Owner has not responded to this issue, and so we believe that
`
`June 2nd, 2008 is the relevant date for these IPRs.
`
`
`
`
`
`
`5
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`On the right side of the slide is claim 1 of the ’918 patent. As
`
`highlighted in red, the claimed invention of the ’918 patent requires four
`
`converters on the memory module providing four regulated voltages.
`
`
`
`Slide 6 provides an overview of the ’054 patent which is a
`
`continuation of the ‘918 patent as shown by the yellow highlighting. And it
`
`requires three buck converters and three regulated voltages.
`
`
`
`Slide 7 provides an overview of the disclosed embodiment of the ’918
`
`and ’054 patents.
`
`
`
`Figure 12 on the left shows a memory module where the yellow is
`
`volatile memory such as DDR2 memory.
`
`
`
`The green is non-volatile memory such as NAND flash memory. The
`
`red is controller 1062, and the blue is the power supply 1080.
`
`
`
`Slide 8 shows Figure 16 of the ’918 and ’054 patents which provides
`
`an example of four converters on a memory module.
`
`
`
`1122 in teal is a converter buck converter outputting 1.8 volts. 1124
`
`in green and yellow is a dual buck converter with outputs of 2.5 volts and
`
`1.2 volts.
`
`
`
`
`
`
`
`And 1126 in red is a buck-boost converter outputting 3.3 volts.
`
`Slide 10 shows the instituted grounds which are similar in those IPRs.
`
`For grounds 1 through 3, the primary reference is Harris with grounds
`
`2 and 3 covering all of the claims.
`
`
`
`And for grounds 4 and 5, the primary reference is Spiers. And these
`
`grounds also cover all of the claims.
`
`
`
`Slide 11 provides an overview of Harris which is the primary
`
`reference for grounds 1 through 3.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`
`
`
`
`
`6
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`As shown by the red box in the middle, Harris teaches putting at least
`
`one onboard voltage regulator module on the memory module just like the
`
`’918 and ’054 patents.
`
`
`
`As shown on the right, paragraph 9 of Harris teaches that the onboard
`
`voltage regulator module can provide voltages from 0.5 volts up to 3.5 volts
`
`or more.
`
`
`
`And as shown on the left, paragraph 12 of Harris specifically
`
`identifies an FBD module which stands for fully buffered DIMM module as
`
`a type of memory module that could benefit from his invention.
`
`
`
`Slide 12 provides an overview of the FBDIMM standards which are
`
`relevant given that Harris specifically identifies FBDIMM as a type of
`
`memory module that could benefit from his invention.
`
`
`
`As shown on the right of this slide, the FBDIMM standards identify a
`
`number of voltages required by an FBDIMM, including 1.5 volts, 1.8 volts,
`
`3.3 volts, and 0.9 volts for VTT which is half of the primary voltage.
`
`
`
`Slide 13 provides an overview of the Amidi reference which discloses
`
`providing battery backup for a memory module in the event that a power
`
`fault is detected.
`
`
`
`Slide 14 provides an overview of the Hajeck reference which teaches
`
`a voltage detection circuit for detecting both undervoltage conditions as well
`
`as overvoltage conditions when the voltage exceeds a certain level.
`
`
`
`Slide 15 provides an overview of the Spiers reference which is very
`
`similar to the ’918 and ’054 patents.
`
`
`
`Figure 5 in the middle shows a memory module where the yellow is
`
`volatile memory, the green is non-volatile memory.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`
`
`
`
`
`7
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`The blue are capacitors that provide backup power, and the red is an
`
`FPGA controller on the memory module.
`
`
`
`As shown on the right side in the event that the memory module
`
`detects a power failure, the memory module can switch power to the
`
`capacitors shown in blue, also referred to as CAPS, C-A-P-S, and can
`
`transfer data from the volatile memory in yellow to the non-volatile memory
`
`in green to avoid losing any data.
`
`
`
`Slide 18 summarizes the ground 1 combination of Harris and the
`
`FBDIMM standards.
`
`
`
`This combination is essentially the same for both IPRs. But as shown
`
`in the bottom right, for each IPR, we provided three different ways that the
`
`voltages disclosed in ground 1 satisfy the claim 1st, 2nd, and 3rd, and 4th
`
`regulated voltages. And we refer to these as voltage mappings A to C in
`
`each IPR.
`
`
`
`Slide 19 shows a quote from the Federal Circuit decision in General
`
`Hospital v. Sienna, which makes the point that, quote, when a prior art
`
`patent discloses a range of values, showing claim value falls within that
`
`range meets the party’s burden of establishing the narrower claim would’ve
`
`been obvious when there is no reason to think the result would be
`
`unpredictable, end quote.
`
`
`
`This precedent is important because ground 1 not only teaches the
`
`specific voltage mappings A to C shown on the bottom right.
`
`
`
`But ground 1 also teaches more generally that any voltages within the
`
`range 0.5 volts to 3.5 volts can be generated on the module using at least one
`
`onboard voltage regulator module.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`
`
`
`
`
`8
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slide 20 summarizes ground 2 which adds the teachings of Amidi
`
`shown in blue to the module of ground 1.
`
`
`
`
`
`Amidi teaches battery backup and logic for detecting power faults.
`
`And Amidi, like Harris, also teaches using buck converters on the
`
`memory module.
`
`
`
`We contend that ground 2 renders obvious all claims of the ’918 and
`
`’054 patents.
`
`
`
`Slide 21 summarizes ground 3 which adds the teachings of the Hajeck
`
`reference shown at the bottom. As shown in red, Hajeck teaches a voltage
`
`detection circuit that monitors for overvoltage conditions such as power
`
`surges and spikes as well as undervoltage conditions including power
`
`outages.
`
`
`
`Slides 22 through 31 address Patent Owner’s primary argument
`
`against grounds 1 to 3 which is that according to the Patent Owner, it would
`
`be non-obvious to supply power to the edge connections at the bottom of the
`
`memory module.
`
`
`
`Slide 23 shows that the Institution Decision correctly rejected this
`
`argument.
`
`
`
`Slide 24 shows that Harris teaches replacing the standard power
`
`supply interface pins which are along the bottom edge of the memory
`
`module with fewer 12-volt pins.
`
`
`
`Paragraph 2 of Harris in the upper left teaches that standard memory
`
`modules in the prior art needed a, quote, relatively large number of pins, end
`
`quote, to supply all the different voltages required by the memory module.
`
`
`
`Now it’s undisputed that it was standard in the prior art for power to
`
`be supplied to the pins along the bottom edge of the memory module.
`
`
`
`
`
`
`9
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Paragraphs 10 and 12 of Harris propose replacing those large number
`
`of pins along the bottom edge with as few as six 12-volt pins.
`
`
`
`Paragraph 14 of Harris emphasizes that his invention works with any
`
`combination of known and heretofore unknown voltage supplies.
`
`
`
`Again, it’s undisputed that it was known that standard memory
`
`modules like an FBDIMM receive power from the pins along the bottom
`
`edge of the memory module.
`
`
`
`And that’s our contention is that it would’ve been completely obvious
`
`from the teachings of ground 1 to continue to use power pins along the
`
`bottom edge of the memory module.
`
`
`
`Slide 25 shows at the top that Netlist expert admits that it was, quote,
`
`standard for a memory module to receive power from the edge connections
`
`along the bottom edge of the memory module.
`
`
`
`For example, as shown in the middle of this slide, it’s undisputed that
`
`FBDIMMs receive power from the edge connections along the bottom of the
`
`memory module.
`
`
`
`And as shown at the bottom of this slide, Harris specifically identifies
`
`FBDIMM as a type of memory module that could benefit from his invention.
`
`
`
`I have a few additional slides in support of our argument that will be
`
`obvious to supply power along the bottom.
`
`
`
`But in the interest of time, I was planning to move on to the next issue
`
`unless the Board has any questions for me on this issue.
`
`
`
`Moving on to slide 32, slides 32 through 37 address the Patent
`
`Owner’s second argument against grounds 1 through 3 which is that
`
`according to the Patent Owner, it would be non-obvious to use data, address,
`
`and control signals between the memory module and the host system.
`
`
`
`
`
`
`10
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slide 33 says that the Institution Decision correctly found that ground
`
`1 renders those signals obvious as shown on the right side of slide 33.
`
`
`
`For example, Harris on the left teaches that the buffer in red on the
`
`memory module receives data, address, and control signals via memory
`
`control or interface 114 highlighted in yellow.
`
`
`
`
`
`
`
`Slide 34 shows on the left the layout of an FBDIMM memory module.
`
`And again, Harris is an example of an FBDIMM memory module.
`
`In the middle of the FBDIMM memory module is a box labeled AMB
`
`which stands for advanced memory buffer.
`
`
`
`As shown at the bottom of the drawing, the memory controller in the
`
`host computer sends address command and clock signals to the AMB as well
`
`as DQ data signals and DQS strobe signals.
`
`
`
`And as explained by Netlist’s expert on the right side of this slide,
`
`these signals sent from the host to the AMB are sent as packetized serial
`
`signals.
`
`
`
`But they are still signals which is all that the claims of the ‘918 and
`
`‘054 patents require.
`
`
`
`Slide 35 provides more detail about how the AMB buffer on an
`
`FBDIMM memory module works.
`
`
`
`As shown in the upper left, the JEDEC standard for the AMB makes
`
`clear that it is the host computer that is in charge of, quote, all memory
`
`control for the DRAM including memory request initiation, end quote.
`
`
`
`In other words, it’s the host that determines what data signals to send,
`
`what address signals to send and what control signals to send.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`
`
`
`
`
`11
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`As underlined in red on the left, the JEDEC standard makes clear that
`
`the host sends those, quote, signals to the AMB, including the signals
`
`labeled PS0 to PS9 which are high speed serial signals.
`
`
`
`As confirmed by Netlist’s expert on the previous slide, the signals
`
`from the host include data, address, and control signals sent as packetized
`
`serial signals.
`
`
`
`The AMB then decodes those signals and sends corresponding data,
`
`address, control signals to the DRAM memory devices as shown on the right
`
`side of this slide.
`
`
`
`Slide 36 responds to one of Netlist’s arguments. Netlist’s argument as
`
`shown on the right is that the claims require dedicated pins for data, address,
`
`and control signals.
`
`
`
`According to Netlist, encoding signals so they can be sent in packets
`
`as is done with the FBDIMM memory module somehow does not satisfy the
`
`claim language.
`
`
`
`But as shown on the left, the claim language just requires signals, not
`
`a dedicated pin for each signal.
`
`
`
`Slide 37 shows that Netlist’s argument would exclude FBDIMM from
`
`the scope of the claims which is contrary to disclosure in the ‘918 and ‘054
`
`patents on the left which explicitly identifies FBDIMM as the preferred
`
`embodiment.
`
`
`
`And as explained by the Federal Circuit on the right the claim
`
`construction that excludes the preferred embodiment is rarely if ever correct
`
`and would require highly persuasive evidentiary support.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`
`
`
`
`
`12
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slides 38 through 62 address Patent Owner’s third argument against
`
`grounds 1 through 3 which is that according to patent owner, it would be
`
`non-obvious to use three or four buck converters on the memory module.
`
`
`
`Slide 39 shows the Institution Decision correctly rejected Netlist’s
`
`argument and found that it would be obvious in light of ground 1 to use four
`
`buck converters on the memory module.
`
`
`
`Slide 40 shows that it was well known to use buck converters to
`
`provide a lower regulated voltage.
`
`
`
`The upper left is paragraph 10 of Harris which teaches the use of a,
`
`quote, switching voltage converter on the memory module which as shown
`
`by the textbook on the right is called a buck converter when you ’re going
`
`from a higher voltage to a lower voltage.
`
`
`
`The lower left figure is Figure 6 of the Amidi which explicitly uses
`
`the label buck for a converter that goes from 3.6 volts down to 1.8 volts.
`
`
`
`Slide 41 shows in the upper left that Netlist expert admits that buck
`
`converters were known in the art.
`
`
`
`And as explained by our expert on the bottom left, the trend in the
`
`industry was to use buck converters in part because they are highly efficient
`
`as we explained on the right in the petition.
`
`
`
`Slide 42 quotes two Federal Circuit decisions which are relevant to
`
`many of the arguments that Netlist makes.
`
`
`
`I will discuss Netlist’s arguments in more detail in the following
`
`slides.
`
`
`
`But first I want to make an overall point. Netlist repeatedly argues
`
`that instead of using a buck converter, you could use something else like an
`
`LDO regulator.
`
`
`
`
`
`
`13
`
`
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`The problem with Netlist’s arguments is that as a legal matter, they
`
`miss the mark.
`
`
`
`The Federal Circuit has repeatedly emphasized that for purposes of
`
`obviousness, it does not matter if a buck converter is considered inferior in
`
`certain situations or if there are better alternatives to a buck converter in
`
`certain situations.
`
`
`
`Rather as shown on the right, the question is whether a buck converter
`
`was a suitable option.
`
`
`
`
`
`
`
`Here, the answer is yes. A buck converter was a suitable option.
`
`Harris and Amidi both specifically taught using buck converters.
`
`Buck converters were taught in textbooks, and they were widely used
`
`and commercially available at the time.
`
`
`
`In short, it was obvious to use buck converters to provide lower
`
`regulated voltages on a memory module.
`
`
`
`Slides 43 to 49 respond to Netlist’s argument that Harris only teaches
`
`using one buck converter and that it would therefore be non-obvious to use
`
`four buck converters for four different voltages.
`
`
`
`Slide 43 on the left quotes from Netlist’s brief which points to a single
`
`sentence in paragraph 10 of Harris that refers to, quote, a high frequency
`
`switching voltage converter, end quote.
`
`
`
`That is shown in the upper right of this slide, paragraph 10 of Harris,
`
`as well as claim 1 of Harris made clear that the invention is not limited to a
`
`single voltage converter and instead also works with multiple voltage
`
`converters which is why Harris repeatedly uses the phrase, quote, at least
`
`one onboard voltage regulator, end quote.
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`
`
`
`
`
`14
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slide 44 points out another problem with Netlist’s argument. As
`
`shown on the left, Netlist argues that Harris’ voltage regulator module
`
`shown in the red box is a single buck converter that outputs two different
`
`regulated voltages, VCC which is 1.5 volts in Harris and VDD which is 1.8
`
`volts.
`
`
`
`But as shown on the right, the problem with Netlist’s argument is that
`
`what Netlist is calling one buck converter is actually two buck converters
`
`according to the ’918 and ’054 patents given that they’re two different
`
`regulated voltage outputs.
`
`
`
`It doesn’t matter that Harris draws one box for the voltage regulator
`
`module.
`
`
`
`What matters is the number of regulated voltage outputs. And we
`
`know from the FBDIMM standards that Harris would need to provide four
`
`different regulated voltage outputs, thus making it obvious to use four buck
`
`converters.
`
`
`
`Slide 45 shows that a single chip such as the one shown on the left can
`
`include multiple buck converters as admitted by Netlist’s expert on the right.
`
`
`
`Again, the point is it does not matter that Harris shows only one box
`
`for the voltage regulator module because that one box can have multiple
`
`buck converters.
`
`
`
`Slide 46 shows that it was common for a single chip to have multiple
`
`buck converters.
`
`
`
`And such chips were commercially available. Slide 47 shows that it
`
`was also common to use multiple buck converters for multiple outputs.
`
`
`
`In this example, the input is 12 volts as highlighted in yellow just like
`
`in Harris.
`
`
`
`
`
`
`15
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`And there are three different buck converters shown in red outputting
`
`three different regulated voltages, 3.3 volts, 2.5 volts, and 0.9 volts.
`
`
`
`Slide 48 responds to an argument by Netlist as supposedly there
`
`would not have been enough space on a memory module to fit four buck
`
`converters.
`
`
`
`But as shown on the left, paragraph 13 of Harris teaches that one
`
`square inch on both sides of the printed circuit board would be enough space
`
`for all the voltage conversion contemplated by his invention.
`
`
`
`And as shown on the right, our expert confirmed that buck converters
`
`can be extremely small.
`
`
`
`Furthermore, nothing in the ’918 or ’054 patents suggest that space
`
`was a concern.
`
`
`
`And there’s nothing in the claims of the ’918 or ’054 patents that limit
`
`the amount of space available for the buck converters.
`
`
`
`So if you need to make the memory module a little bigger to fit four
`
`buck convertors, that would still satisfy the claims of the ’918 and ’054
`
`patents.
`
`
`
`Slide 49 shows that another reason to space for buck converters was
`
`not a concern is because it was known that you could stack DRAM memory
`
`chips to save space on the board.
`
`
`
`As Netlist’s expert admitted in the right, when you stack the DRAM
`
`memory chips, quote, you’ve now doubled the amount of memory stored in
`
`the same amount of physical space, end quote.
`
`
`
`That was a known option at the time to save space on the memory
`
`module.
`
`
`
`
`
`
`16
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slides 50 to 52 respond to Netlist’s argument that it would be non-
`
`obvious to use two different buck converters or two different voltages.
`
`
`
`Slide 50 on the left shows that this argument by Netlist is relevant to
`
`voltage mappings A and B and not voltage mapping C, though, because
`
`voltage mapping C uses four different voltage levels ranking from 0.9 to 3.3
`
`volts.
`
`
`
`With respect to voltage mappings A and B, the Institution Decision on
`
`the right correctly rejected Netlist’s argument and found that it was obvious
`
`to use two different buck converters for the same voltage to provide, quote,
`
`independence for the power supplies with improved stability and flexibility
`
`for power management, end quote.
`
`
`
`Slide 51 shows two excerpts from the JEDEC standard on the left
`
`side.
`
`
`
`As shown by the blue and red highlighting, JEDEC teaches two
`
`different options for VDD, VDDL, and VDDQ.
`
`
`
`One option as shown in blue is to use a, quote, single power converter,
`
`end quote, for those three voltages.
`
`
`
`But another option shown in red is to use multiple converters to
`
`permit independent control and isolation of those voltages. As explained,
`
`our --
`
`
`
`
`
`
`
`JUDGE JURGOVAN: Can I ask a question here?
`
`MR. CHANDLER: Please.
`
`JUDGE JURGOVAN: I believe Patent Owner’s argument with
`
`respect to the red box is that these are just singular sentences.
`
`
`
`And there’s no conjunction that all of these things would be used
`
`together. But how do you respond to that argument?
`
`
`
`
`
`
`17
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`MR. CHANDLER: That’s incorrect, Your Honor. As you see the
`
`bottom there, it says, at least one of these two sets of conditions must be
`
`met.
`
`
`
`And the two sets are the one sets above or which we’ve underlined in
`
`red. And the other set is below the or.
`
`
`
`Also, in the second red box below that, there’s a second indication in
`
`the same JEDEC standard that is recommended to isolate VDDL from VDD
`
`and VDDQ which is consistent with how we are interpreting the two sets,
`
`the two options.
`
`
`
`And then furthermore as explained by our expert at the bottom, it
`
`would be obvious that you would want to treat those voltages independently
`
`so that you could sequence the power so that you could turn the power on
`
`and off independently.
`
`
`
`And also, because it may be more cost effective to use multiple small
`
`regulators rather than one large regulator.
`
`
`
`
`
`JUDGE JURGOVAN: Thank you.
`
`MR. CHANDLER: The second option in red is consistent with
`
`sequencing the power as explained by our expert.
`
`
`
`
`
`And that would be a motivation for having separate buck converters.
`
`The second option requires that the VDD, for example, is turned on
`
`before or at the same time as VDDL.
`
`
`
`And so you would need separate buck converters for that capability to
`
`sequence the order in which you power up these different voltages.
`
`
`
`Slide 52 cites to additional evidence supporting the point that they
`
`were known advantages using multiple buck converters, even if they all
`
`output 1.8 volts.
`
`
`
`
`
`
`18
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`And again, those advantages include sequencing, independent control,
`
`efficiency, and saving power.
`
`
`
`Slides 53 through 57 respond to Netlist’s argument that it would be
`
`non-obvious to use a buck converter on the module for VTT.
`
`
`
`Slide 53 on the left shows that this argument is only relevant to
`
`voltage mapping C which includes a VTT voltage of 0.9 volts.
`
`
`
`As shown on the right side of Slide 53, the Institution Decision
`
`correctly rejected Netlist’s argument and found that it would logically follow
`
`to generate VTT on the module using the same voltage regulatory module
`
`102 as used to generate voltages VCC and VDD.
`
`
`
`Furthermore, the Institution Decision correctly reasoned that, quote,
`
`there are only two options.
`
`
`
`Generate the voltage VTT on the module as Petitioner indicates or
`
`obtain the voltage VTT from the interface pins, end quote. And thus under
`
`KSR, either option would’ve been obvious.
`
`
`
`Slide 54 shows that Harris teaches generating all of the needed
`
`voltages on the module which would include VTT.
`
`
`
`Now Netlist argues that Harris does not explicitly illustrate VTT in
`
`Figure 1A in the upper left of this slide.
`
`
`
`But Harris teaches replacing all the power supply pins on an
`
`FBDIMM memory module with fewer 12-volt pins.
`
`
`
`And then as shown at the bottom in green, a standard FBDIMM needs
`
`power supply pins for VTT.
`
`
`
`It would thus be obvious in light of Harris’ teaching to eliminate the
`
`power supply pins for VTT and instead to use a buck converter to generate
`
`VTT on the memory module.
`
`
`
`
`
`
`19
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`IPR2022-00996 (Patent 11,016,918 B2)
`IPR2022-00999 (Patent 11,232,054 B2)
`
`
`
`
`Slide 55 shows that buck converters were commercially available that
`
`were suitable for generating VTT.
`
`
`
`But not only was it obvious to use a buck converter for VTT, it was
`
`common.
`
`
`
`Slide 56 shows that it was known that buck converters were generally
`
`more efficient than an LDO regulator at converting from 12 volts down to
`
`0.9 volts as would be required for VTT.
`
`
`
`JUDGE JURGOVAN: Counsel, can I interrupt for a second? So are
`
`dual buck or rather are buck converters and LDOs the only options for
`
`converters to use in this context?
`
`
`
`MR. CHANDLER: The only two that the parties have discussed and
`
`they’re the two that I recall seeing in the record.
`
`
`
`In the provisional, there is reference to a third type, something like a
`
`transformer. But all the discussions been around buck convertors and LDOs.
`
`
`
`JUDGE JURGOVAN: And then the high-speed switching voltage
`
`converter, I think that’s how Harris describes what its converter is.
`
`
`
`
`
`MR. CHANDLER: Yes.
`
`JUDGE JURGOVAN: How would one know with certainty that
`
`that’s a buck convertor and not some other kind of converter? Are buck
`
`converters the only converters that use switched --
`
`
`
`
`
`
`
`MR. CHANDLER: Yes.
`
`JUDGE JURGOVAN: -- voltages that they’re input?
`
`MR. CHANDLER: Yes, that’s the description. So we have this here
`
`on slide 40.
`
`
`
`S
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
