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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
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`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`
`
`
`
`___________________
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`PATENT OWNER PRELIMINARY RESPONSE
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`TABLE OF CONTENTS
`
`2.
`
`3.
`
`4.
`
`Page
`INTRODUCTION ........................................................................................ 1
`I.
`THE ’918 PATENT ...................................................................................... 2
`II.
`SKILL LEVEL OF A POSITA .................................................................... 6
`III.
`IV. THE PRIOR ART ......................................................................................... 6
`A. Harris (EX1023) ................................................................................. 6
`B.
`Spiers (EX1025) ................................................................................. 9
`THE PETITION DOES NOT ESTABLISH A REASONABLE
`LIKELIHOD OF SUCCESS ON GROUNDS 1-3 ..................................... 14
`A.
`Petitioner Has Failed to Present Prima Facie Evidence that
`Harris Discloses a Memory Module Having a PCB Interface
`that Receives Voltage/Power from a Host System .......................... 14
`Petitioner Has Failed to Provide Competent Evidence that a
`POSITA Would Have Modified Harris’ Memory Module to
`Have Four Converters ...................................................................... 20
`1.
`Harris Requires At Most Three Converters to Provide
`the Four Claimed Voltages .................................................... 22
`Petitioner Fails to Present a Prima Facie Case for
`Using Multiple Converters to Provide Voltages of the
`Same Level ............................................................................. 25
`Petitioner Fails to Present a Prima Facie Case for
`Using a Third Buck Converter to Provide VTT ...................... 29
`Petitioner Fails to Present a Prima Facie Case for
`Using a Fourth Buck Converter to Provide VDDSPD ............... 33
`Petitioner has Failed to Provide Competent Evidence that a
`POSITA Would Have Modified Harris’ Memory Module
`With Amidi’s Power Management Block (Grounds 2 and 3) .......... 35
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`V.
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`B.
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`C.
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`Page
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`D.
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`2.
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`B.
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`Petitioner Has Presented No Competent Evidence on “Pre-
`Regulated Input Voltage” (Claims 16-22, 30) ................................. 39
`VI. PETITIONER FAILED TO ESTABLISH A REASONABLE
`LIKELIHOD OF SUCCESS ON GROUNDS 4-5 ..................................... 40
`A.
`Petitioner Has Not Presented Any Competent Evidence that
`Spiers, Alone or in Combination, Renders Obvious the
`Requirement for Four Regulated Voltages ...................................... 42
`1.
`Spiers’ Volatile Memory Devices in the Backup
`Device are SDR SDRAMs ..................................................... 42
`Petitioner Has Presented No Reason Why a POSITA
`Would Have Replaced Spiers’ SDRAMs with DDR2
`or DDR3 ................................................................................. 47
`Petitioner Has Presented No Competent Evidence that a
`POSITA Would Have Modified Spiers Using Four Buck
`Converters ........................................................................................ 53
`1.
`No reasons were given for using a buck converter for
`VTT (Mappings A-B) .............................................................. 53
`(a)
`There is no evidence why Spiers’ PCI Board
`would need to provide a VTT to DDR2 or DDR3
`memory ........................................................................ 53
`There is no competent evidence that a POSITA
`would have generated VTT using a buck
`converter ...................................................................... 56
`No reason is provided for equipping Spiers with
`multiple 1.8V regulators (Mappings B-C) ............................. 59
`No reason is provided for equipping Spiers with a
`buck converter for generating 1.5V output (mapping
`A) ............................................................................................ 60
`
`(b)
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`2.
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`3.
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`No reasons were provided for why Spiers’ 5V-to-3.3V
`regulator 184 is a buck converter (all mappings) .................. 62
`Petitioner Has Presented No Competent Evidence on “Pre-
`Regulated Input Voltage” (Claims 16-22, 30) ................................. 70
`Petitioner Has Presented No Competent Evidence for Claim
`23 ...................................................................................................... 71
`VII. PETITIONER IMPROPERLY INCORPORATES BY
`REFERENCE ............................................................................................. 72
`VIII. CONCLUSION ........................................................................................... 72
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`C.
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`D.
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Cisco Systems, Inc. v. C-Cation Techs., LLC,
`IPR2014-00454 (PTAB Aug. 29, 2014) ............................................................. 72
`In re Enhanced Security Research, LLC,
`739 F.3d 1347 (Fed. Cir. 2014) ........................................................ 24, 25, 26, 27
`In re Lee,
`277 F.3d 1338 (Fed. Cir. 2002) .......................................................................... 30
`Ex parte Pinon,
`Appeal 2017/005566 (PTAB, March 9, 2018) ................................................... 25
`South-Tek Sys., LLC v. Engineered Corrosion Sols., LLC,
`748 F. App’x. 1003 (Fed. Cir. 2018) .................................................................. 37
`TQ Delta, LLC v. Cisco Sys., Inc.,
`942 F.3d 1352 (Fed. Cir. 2019) ........................................................ 31, 32, 47, 69
`Other Authorities
`37 C.F.R. § 42.6(a)(3) .............................................................................................. 72
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`EXHIBIT LIST
`
`Document
`Declaration of Dr. Sunil P. Khatri
`U.S. 8,301,833
`Belloni, M. et al., A 4-Output Single-Inductor DC-DC Buck
`Converter with Self-Boosted Switch Drivers and 1.2A Total
`Output Current, ISSCC 2008, Session 24.6
`Ma, Dongsheng et al., Single-Inductor Multiple-Output
`Switching Converters With Time-Multiplexing Control in
`Discontinuous Conduction Mode, IEEE J. of Solid-State
`Circuits, 38(1) (Jan. 2003)
`U.S. 6,067,2451
`Micron Technical Note, TN-47-05 DDR2 Power Solutions for
`Notebooks Overview (2004)
`Texas Instruments, LP29996-N, LP2296A DDR Termination
`Regulator (Nov. 2002-Revised Dec. 2016)
`National Semiconductor, LP2996 DDR Termination Regulator
`(June 2006), downloaded from
`https://datasheet.octopart.com/LP2996MR-NOPB-Texas-
`Instruments-datasheet-7837571.pdf (last visited 09/08/2022)
`National Semiconductor, LP2997 DDR-II Termination Regulator
`(June 2006), downloaded from
`https://www.jameco.com/Jameco/Products/ProdDS/843930.pdf
`(last visited 09/08/2022)
`National Semiconductor, LP2998 DDR-II and DDR-I
`Termination Regulator (Dec. 12, 2007), downloaded from
`https://www.semiee.com/file/backup/INTERSIL-LP2998.pdf
`(last visited 09/08/2022)
`Bergveld, H. J., Battery Management Systems Design by
`Modeling, Royal Philips Electronics N.V. (2001)
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`Exhibit No.
`EX2001
`EX2002
`EX2003
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`EX2004
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`EX2005
`EX2006
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`EX2007
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`EX2008
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`EX2009
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`EX2010
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`EX2011
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`Document
`Romo, Joaquin, DDR Memories: Comparison and overview,
`NXP technical note, downloaded from
`https://www.nxp.com/docs/en/supporting-
`information/BeyondBits2article17.pdf (last access 09/08/2022).
`As downloaded the file shows the following meta data:
`
`
`JEDEC Standard No. 21-C, PC133 SDRAM Unbuffered SO-
`DIMM Reference Design Specification Rev. 1.02 (2001)
`Qimonda HYB39SC256[80/16]0FE, HYI39SC256[80/16]OFF
`datasheet (June 2007), downloaded from
`https://pdf.dzsc.com/200810211/200809251204372352.pdf (last
`visited 09/08/2022)
`Siemens HYS64/72V2200GU-8/-10, HYS64/72V4220GU-8/-10
`datasheet (June 1998), downloaded from
`https://cdn.datasheetspdf.com/pdf-down/P/C/6/PC66-222-
`920_SiemensSemiconductorGroup.pdf (last visited 09/08/2022)
`EURESYS, PCI Bus Variation Technical Note (2006),
`downloaded from PCI Bus Variation - Technology Note
`(euresys.com) (last accessed 09/08/2022)
`Qimonda HY[B/I]39S256[40/80/16]0FT(L) etc. datasheet
`(September 2007), downloaded from
`https://cms.nacsemi.com/content/AuthDatasheets/QMDAS00628
`-1.pdf (last visited 09/08/2022)
`Transcend, What is the difference between SDRAM, DDR1,
`DDR2, DDR3 and DDR4? Downloaded from
`https://www.transcend-info.com/support/faq-296#:~:text=DDR3
`(last visited 09/08/2022)
`Transcend company profile, https://us.transcend-
`info.com/about/company (last visited 09/08/2022)
`Brown, M., Power Supply Cookbook, Newnes (2d.) (2001)
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`Exhibit No.
`EX2012
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`EX2013
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`EX2014
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`EX2015
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`EX2016
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`EX2017
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`EX2018
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`EX2019
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`EX2020
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`EX2022
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`EX2023
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`EX2024
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`EX2025
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`EX2026
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`Exhibit No.
`EX2021
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`
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`Document
`Texas Instruments, Low Dropout Operation in a Buck Converter
`(SLUA928A, December 2018 — revised March. 2019),
`downloaded from Low Dropout Operation in a Buck Converter
`(Rev. A) (last visited 09/08/2022)
`Electronic Design, Simple Soft-Start Circuitry Provides Long
`Startup Times (June 22, 1998), downloaded from
`https://www.electronicdesign.com/power-
`management/article/21801244/simple-softstart-circuitry-
`provides-long-startup-times (last visited 09/08/2022)
`Micron Technical Note, TN-04-30, Various Methods of DRAM
`Refresh (1999), downloaded from DT30 (reactivemicro.com)
`(last visited 09/08/2022)
`Schmid, Patrick, Understanding Hard Drive Performance
`(March 5, 2007), downloaded from
`https://www.tomshardware.com/reviews/understanding-hard-
`drive-performance,1557-5.html (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded
`from https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/256mb_sdr.pdf (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded
`from https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/64mb_x4x8x16_sdram.pdf (last visited 09/08/2022)
`Transcend, DDR2 SO-DIMM datasheet
`EX2027
`EX2028 Micron Technical Note TN-41-13, DDR3 Point-to-Point Design
`Support Introduction (2013), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/technical-
`note/dram/tn4113_ddr3_point_to_point_design.pdf (last visited
`09/08/2022)
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`Document
`PCI Technology Overview (Feb. 2003)
`downloaded from
`https://web.archive.org/web/20040721012143/http://www.cs.unc
`.edu/Research/stc/FAQs/pci-overview.pdf (Wayback Machine
`(archive.org)) (last visited 09/08/2022)
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`
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`Exhibit No.
`EX2029
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`STATEMENT OF MATERIAL FACTS IN DISPUTE
`Petitioner did not submit a statement of material facts in this Petition.
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`Accordingly, no response is due pursuant to 37 C.F.R. § 42.23(a), and no facts are
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`admitted.
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`INTRODUCTION1
`The petition is a textbook example of hindsight. Each of the challenged
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`I.
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`claims requires four voltage converters, each configured to provide a regulated
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`voltage. See EX1001, cls. 1.c-1.f, 16.c-16.d and 23.d-23.e. Harris, however,
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`discloses a “Voltage Regulator Module” 102, preferably implemented as “a high-
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`frequency voltage converter” that generates two voltages (Vcc and Vdd). See
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`Section V.B.1. As such, a POSITA would need at most two additional regulators
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`for no more than three regulators in total to generate the four voltages identified in
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`Petitioner’s voltage mappings. Ignoring Harris’ disclosures, Petitioner instead uses
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`the claims as a roadmap to argue that a POSITA would have used four converters
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`for the four voltages. That is hindsight.
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`Similarly, for the Spiers-based grounds, Petitioner argues that Spiers did not
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`disclose the specific types of SDRAMs it used, and a POSITA would therefore
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`look to Amidi for such details and use DDR2 (or DDR3) in Spiers. That simply
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`ignores Spier’s disclosures as a whole, which makes clear that Spiers used single
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`data rate (“SDR”) SDRAM as its volatile memory. See Section VI.A.1. Petitioner
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`arbitrarily selects DDR2/DDR3 in order to come up with the required number of
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`voltages and converters. That is again hindsight. Indeed, Petitioner does not even
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`1 All emphasis added unless otherwise noted.
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`consider the fact that DDR2/DDR3 is for use in applications with high high read-
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`to-write ratios, while Spiers’ application has a low read-to-write ratio. See VI.A.2
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`Petitioner ignores the references’ express disclosures in other respects. For
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`example, the claims require the memory module to have edge connections
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`“configured to couple power … between the memory module and the host system.”
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`See elements 1.b, 16.b and 23.b. Petitioner’s own citations disclose instead that
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`Harris eliminated the system power supply to the memory module, and replaced it
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`with an external power source. E.g., EX1023, Fig. 1A, [0019], [0012], [0010]
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`(cited on Pet. 21).
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`To be clear, Netlist is not arguing bodily incorporation or weight of
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`evidence. It is pointing out the absence of pertinent analysis in the Petition and the
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`facial inconsistency between Petitioner’s evidence and the claim requirements.
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`The petition should be denied for these and further reasons stated below.
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`II. THE ’918 PATENT
`The inventions of the ’918 patent originated from Netlist’s development work
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`on a memory module/system 1010 having both volatile and non-volatile memories.
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`In one preferred embodiment, the memory module 1010 comprises a PCB 1020
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`having DRAM (volatile) and NAND (nonvolatile) memory, both of which may be
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`operatively coupled to a controller unit 1062. See, e.g., EX1001, Fig. 12 (annotated
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`image on Pet. 6 reproduced below).
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`In the figure above, the controller 1062 includes both a microcontroller unit
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`1060 and an FPGA logic 1070. See EX1001, 24:35-37. In other embodiments, the
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`FPGA may be integrated with the microcontroller. See id., 23:19-22, Fig. 14. Data
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`may be transferred between the volatile and non-volatile memories via and under the
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`management of the microcontroller. See id., 24:35-41. The logic element 1070
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`provides signal level translation and address translation between the volatile memory
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`and non-volatile memory. See id., 24:45-56.
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`A switch 1052 can selectively couple or decouple the volatile memory from
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`the controller in response to control signals from the controller. See id., 21:20-23,
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`23:28-37, 23:44-50, 24:60-25:3. The switch 1052 may also “selectively operatively
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`couple[] and decouple[] the volatile memory subsystem 1030 and the host system.”
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`Id., 23:37-40. For example, in response to a power interruption (e.g., a second state),
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`switch 1052 may operatively couple the volatile memory with the controller and the
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`non-volatile memory so that data in the volatile memory may be transferred to the
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`non-volatile memory. See id., 24:60-25:7. When the system is operating normally
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`(e.g., a first state), switch 1052 operatively decouples the volatile memory from the
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`controller and the non-volatile memory. See id.
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`In the figure above, the PCB includes a DIMM interface (colored in orange),
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`via which “power voltage as well as data, address and control signals between the
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`memory system 1010 and [a] host system” is exchanged. Id., 21:65-22:6. The power
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`from the host system powers the memory system in the first state. Id., 25:54-58.
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`To effect the transition from the first state to the second state, the invention
`
`includes a voltage monitor 1050 on the PCB that “monitors the voltage supplied by
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`the host system via the [DIMM] interface[.]” See id., Fig. 12, 25:8-10. Upon
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`detecting an abnormal condition, the voltage monitor circuit 1050 may transmit a
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`signal to the controller, which may in turn transmit a signal to switch 1052 for it to
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`operatively couple the volatile memory and the non-volatile memory. See id., 25:8-
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`20. The voltage monitor circuit can be part of, or separate from, the controller.
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`EX1001, 25:27-31.
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`In preferred embodiments, the system power (a first power supply) supplies
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`power for the first state, and a second power supply 1080 is provided for the second
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`state. See id., 25:54-58, 26:4-13, Fig. 12. The power supply includes a capacitor
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`bank 86/1086 as well as voltage regulators. See id. The second power supply may
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`be selectively coupled or decoupled to the controller and the memory via a switch
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`1090. See id., 26:43-54. The memory subsystem may also include a third state in
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`which power is supplied from a third power supply. See id., 25:62-26:3.
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`Figure 16 of the ’918 patent illustrates a power module comprising the three
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`power supplies:
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`(1) power from system (color orange to match Samsung’s color for DIMM
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`interface) for a first state;
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`(2) “second power element” 1140 (colored blue to match Samsung’s color
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`scheme for power supply 1080) for the second state (e.g., when there is a power
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`interruption); and
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`(3) “first power element” 1130 (colored purple) for the third state (e.g., when
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`detecting a power failure is likely to occur).2 See id., 28:3-25, 28:39-47, 28:53-58.
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`2 Note, in connection with Figures 16-17 of the ’918 patent, the specification refers
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`to the condition in which a trigger event is likely to occur as the “second”
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`condition/state and the condition in which the trigger event has occurred as the
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`“third” state. See id., 28:39-47.
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`The power module also includes a conversion element 1120 (colored dark
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`blue on the right) that outputs regulated voltages 1102-1107. See EX1001, Fig. 16.
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`III. SKILL LEVEL OF A POSITA
`For the purposes of this POPR, Patent Owner is applying the level of ordinary
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`skill in the art proposed by Petitioner. See Pet. 8-9.
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`IV. THE PRIOR ART
`A. Harris (EX1023)
`Harris discloses a “memory assembly module including an on-board voltage
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`regulator for converting an externally supplied voltage into appropriate voltage
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`levels for powering memory devices of the memory assembly module.” See e.g.,
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`EX1023, Abstract, FIG. 1A.
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`
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`As Harris explains, conventional memory modules, such as industry standard
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`Dual In-line Memory Modules (DIMM) “are provided with power supply rails (on
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`a relatively large number of pins) that are powered from system board or main board
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`voltage sources, and are specific to the memory technology.” EX1023, [0002].
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`Harris, on the other hand, aims to “provide[] a technology-independent voltage
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`distribution scheme for memory devices wherein system board power supply and
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`associated voltage plane(s) are eliminated.” Id., [0019]. Using a fully-buffered
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`DIMM as an example, Harris explains that its goal can be achieved by “replacing
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`the[] power supply interface pins with … +12V pins (from an external power
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`source), with local conversion to Vdd (to DRAM) and Vcc (to buffer/logic) being
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`added.” Id., [0012].
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`In other words, instead of obtaining power from the host via power supply
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`interface pins, Harris’s design derives its power from an external power source that
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`is subsequently converted to the appropriate voltage levels depending on the designs.
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`Id., [0012]; [0016] (“voltage is supplied to a memory board assembly from an
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`external source, e.g., an unregulated source generating fairly high voltages
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`(illustratively, at +12V) with a wide tolerance. The voltage distribution method then
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`involves locally converting the supply voltage using an on-board VRM to generate
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`appropriate levels of voltage for powering on-board memory devices. … [T]he local
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`voltage levels preferably depend on the application….”).
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`In an alternative embodiment, more than one voltage source may be provided
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`“wherein each VRM is operable with an independent voltage supply path for locally
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`converting an external supply voltage into appropriate local voltage levels.”
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`EX1023, [0014]. In this embodiment, a “logic module 124 is provided for selecting
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`among the plurality of like voltage outputs from the VRMs 122-K in order to
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`energize the Vdd and Vcc paths 108, 106, respectively.” Id., [0015].
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`B.
`Spiers (EX1025)
`U.S. 2006/0080515 to Spiers et al. relates to “Non-Volatile Memory Backup
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`for Network Storage System.” EX1025, p. 1 (title). Spiers aims reduce the amount
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`of time it takes to report data that is written into a storage media while minimizing
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`the risk of data loss. See id., [0003].
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`To achieve this objective, Spiers provides a backup storage system to the main
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`storage device (such as a hard disk drive). See id., [0007]-[0008], Fig. 3. In
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`particular, Spiers describes its implementation with reference to network attached
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`storage (NAS) devices. See id., [0029], Fig. 1. The NAS devices “receive data from
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`applications 104 and acknowledge back to the application 104 that the data is
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`securely stored at the NAS device 108, before the data is actually stored on storage
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`media located within the NAS 108.” Id., [0030]. This allegedly improves NAS’s
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`performance as the NAS device can report that the data has been stored without
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`waiting for the data to be actually stored at the storage media. See id. Spiers
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`achieves this by sending a command to the backup device to store the data and
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`reports the data as having been stored if the backup device reports that that data is
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`store. Id., [0040], Fig. 6.
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`In addition to components necessary to interface with the network, Spiers’
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`NAS devices each include a main storage device 140 with write-back cache and a
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`backup device 144. See id., [0031]-[0032].
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`Spiers’ backup storage device includes a volatile memory (such as SDRAM),
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`a non-volatile memory (such as a NAND flash), and a processor. See id., [0007],
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`[0010], [0032], Fig. 3. The processor is “for causing a copy of data provided to the
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`[main] storage device to be provided to the [backup] storage device volatile memory,
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`and in the event of a power interruption, moving the data from the [backup] data
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`storage device volatile memory to the [backup] data storage device non-volatile
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`memory.” Id., [0007], [0010], [0032], Fig. 3. In this manner, the data written to the
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`main storage’s write-back cache would be retained even in the event of a power
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`interruption, which in turn reduces the risk of data loss. Id., [0007], [0034]. A high-
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`level block diagram for the backup device is shown in Figure 4.
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`Spiers explains that in the exemplary backup device 144, there exists an
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`interface 152 “utilized to communicate with [a] storage controller 132” shown in
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`Figure 3. EX1025, [0036]. The interface 152 is connected to a processor 156 in the
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`backup device 144, and the processor “controls operations within the backup device
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`144.” Id. Connected to the processor 156 are volatile memory 160 (e.g., SDRAM)
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`and non-volatile memory 164 (e.g., flash). Id. The backup device also includes a
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`power supply 168, which is used “upon [processor] detecting a power failure” to
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`move data from the volatile memory 160 to the non-volatile memory 164. Id. “After
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`the data from the volatile memory 160 is stored in the non-volatile memory 164, the
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`processor 156 shuts down the backup device 144.” Id.
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`One example of a backup power supply uses a capacitor array, which “are
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`charged when the backup device 144 is powered up.” Id. In the event of a power
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`interruption, “the backup device 144 receives power from the capacitor(s) when
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`moving the data. After the data is securely stored in the non-volatile memory 164,
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`the power is switched off from the capacitor(s).” Id.
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`Spiers’ Figure 5 illustrates an example of such an implementation. The
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`components in the red box correspond to the backup power supply 168 in Figure 4.
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`NAND Flash 194, SDRAM 190, processor 198 and 64-bit PCI interface 172
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`correspond respectively to the non-volatile memory 164, volatile memory 160,
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`processor 156 and interface 152 of Figure 4. See EX1025, [0037].
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`Spiers references only two voltage regulators: (1) the 5V-to-3.3V regulator
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`184, and (2) regulator 206 that outputs 1.8V “required for the [processor] core.” Id.,
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`[0037], Fig. 5.
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`In Figure 5, the power supply includes two 50F super capacitors connected in
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`a parallel. EX1025, [0037]. “The capacitors 176 are connected to a diode 180[,] a
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`voltage regulator 184, and a charger 186.” Id. The charger 186 draws power from
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`the PCI interface and “charge[s] the capacitor(s).” Id. “[I]n the event of a power
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`failure[,] the capacitors are used as the power source to power the backup device 144
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`when moving data from the volatile memory to the non-volatile memory.” Id.; see
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`also Fig. 5 (showing “+5V_PCI Detector” block).
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`V. THE PETITION DOES NOT ESTABLISH A REASONABLE
`LIKELIHOD OF SUCCESS ON GROUNDS 1-3
`A.
`Petitioner Has Failed to Present Prima Facie Evidence that Harris
`Discloses a Memory Module Having a PCB Interface that
`Receives Voltage/Power from a Host System
`All asserted claims require a memory module that includes “a printed circuit
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`Board (PCB) having an interface … including a plurality of edge connections
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`configured to couple power … between the memory module and the host system.”
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`Pet. xi (1.b), xiii (16.b), xv (23.b); see also Pet. xiv (16.f) (reciting “a voltage monitor
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`circuit configured to monitor an input voltage received via a first portion of the
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`plurality of edge connections”). Thus, all challenged claims require that the memory
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`module includes a PCB interface that receives voltage/power from the host system.
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`Grounds 1-3 rely exclusively on Harris for allegedly disclosing this feature. Pet. 21-
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`22, 50-51, 71, 75-77. For the reasons below, however, Petitioner has not made a
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`prima facie case that Harris discloses such a memory module.
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`Specifically, Petitioner relies on Harris’ Figure 1A and paragraphs 12, 10 and
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`19 to argue that Harris discloses a plurality of edge connections “configured to
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`couple power … between the memory module and the host system.” Pet. 21. These
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`citations instead consistently disclose that Harris derives its power from an “external
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`voltage source.” See EX1023, Fig. 1A.
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`Paragraph 10 of Harris describes an on-board voltage regulator module “for
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`converting an externally supplied voltage level available on external source path
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`104 into appropriate local voltage levels ….” EX1023, [0010]. Paragraph 12 notes
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`that “a standard FBD module requires 28 Vdd pins … and 8 Vcc pins” but suggests
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`“replacing the[] power supply interface pins with as few as six +12V pins (from an
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`external power source).” Id., [0012]. Paragraph 19 is even more explicit, describing
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`how Harris’s method “eliminated” “system board power supply and associated
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`voltage plane(s).” Id., [0019]; see also id. (“Cost savings may include, for example,
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`elimination of system-board-specific power supply or regulator output ….”).
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`Simply put, Petitioner argues that Harris discloses a PCB with edge
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`connections that are configured to couple power between the memory module and
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`host system. Pet. 21. Its own citations indicate instead that Harris modifies the
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`standard FBD module by replacing the module’s “power supply interface pins” (i.e.,
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`pins from which power is supplied from the host’s DIMM slot) with pins connected
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`to an external power source so as to eliminate system board power supply. See
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`EX1023, [0010], [0012], [0019], Fig. 1A (cited on Pet. 21-22).
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`Harris’ approach accords with its stated problem and solution. According to
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`Harris, “[a]s the performance of the DRAM technology goes up, and timing margins
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`shrink, it is becoming increasingly more difficult for the system board sources to
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`provide tightly regulated power for the DRAM cores as well as input/output (I/O)
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`interface buffers.” EX1023, [0002].
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`Harris overcomes this by eliminating “system board power supply and
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`associated voltage plane(s)” typically used to provide power to the memory board,
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`and instead providing power to the memory board “from an external voltage source,”
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`particularly an unregulated source generating fairly high voltages. See id., [0019],
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`[0012], [0015]. Specifically, Harris achieves this by replacing the module’s “power
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`supply interface pins” that couple power between the memory module and the host
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`system with fewer +12V pins connected instead to “an external voltage source.”
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`Id., [0012]; see also id., [0016] (“voltage is supplied to a memory board assembly
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`from an external source, e.g., an unregulated source generating fairly high voltages
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`(illustratively, at +12V) with a wide tolerance”). In this way, Harris effectively
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`decouples the host system’s voltage supply from the memory module. EX2001, ¶60.
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`The absence of power from the PCB is not an optional feature of Harris; it is
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`the entire purpose of Harris, which expressly states that its method “provides a
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`technology-independent voltage distribution scheme for memory devices wherein
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`system board power supply and associated voltage plane(s) are eliminated.”
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`EX1023, [0019]; see also id. (“Cost savings may include, for example, elimination
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`of system-board-specific power supply or regulator output, associated bypass
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`capacitor arrangements, heavy etch or power planes.”). The claims, however,
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`require interface pins (i.e., edge connections) “to couple power … between the
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`memory module and the host system.” See EX1001, 38:21-24, 39:56-59, 40:53-54.
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`Petitioner does not engage at all on how its own citations, which disclose
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`providing power from an external voltage source to the memory board (EX1023,
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`[0010], [0012], Fig. 1A) and “elimination of system-board-specific power supply”
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`([0019]), satisfy the requirement that the claimed memory module receive power
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`from a host system via the module interface configured to fit into a slot connector to
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`the host system. See EX1001, 38:19-24, 39:54-59, 40:51-54 (a PCB “having an
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`interface configured to fit into a corresponding slot connector of a host system, the
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`interface including a plurality of edge connections configured to couple power …
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`between the memory module and the host system”). To be clear, this is not a dispute
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`Case No. IPR2022-00996
`Patent No. 1
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