LP2998 DDR-II and DDR-I Termination Regulator
`
`December 12, 2007
`
`LP2998
`DDR-II and DDR-I Termination Regulator
`Features
`General Description
`■ Source and sink current
`The LP2998 linear regulator is designed to meet JEDEC
`■ Low output voltage offset
`SSTL-2 and JEDEC SSTL-18 specifications for termination of
`DDR-SDRAM and DDR-II memory. The device contains a
`■ No external resistors required
`high-speed operational amplifier to provide excellent re-
`■ Linear topology
`sponse to load transients. The output stage prevents shoot
`■ Suspend to Ram (STR) functionality
`through while delivering 1.5A continuous current as required
`■ Low external component count
`for DDR-SDRAM termination. The LP2998 also incorporates
`a VSENSE pin to provide superior load regulation and a VREF
`■ Thermal Shutdown
`output as a reference for the chipset and DIMMs.
`■ Available in SO-8, PSOP-8 packages
`An additional feature found on the LP2998 is an active low
`shutdown (SD) pin that provides Suspend To RAM (STR)
`functionality. When SD is pulled low the VTT output will tri-
`state providing a high impedance output; while, VREF remains
`active. A power savings advantage can be obtained in this
`mode through lower quiescent current.
`
`Applications
`■ DDR-I and DDR-II Termination Voltage
`■ SSTL-18 Termination
`■ SSTL-2 and SSTL-3 Termination
`■ HSTL Termination
`
`Typical Application Circuit
`
`30026918
`
`© 2007 National Semiconductor Corporation
`
`300269
`
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`
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`

`Connection Diagrams
`
`LP2998
`
`PSOP-8 Layout
`
`30026903
`
`SO-8 Layout
`
`30026904
`
`Pin Descriptions
`
`SO-8 Pin or PSOP-8 Pin
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`
`
`Name
`
`GND
`
`SD
`
`VSENSE
`
`VREF
`
`VDDQ
`
`AVIN
`
`PVIN
`
`VTT
`
`EP
`
`Function
`
`Ground.
`
`Shutdown.
`Feedback pin for regulating VTT.
`Buffered internal reference voltage of VDDQ /2.
`Input for internal reference equal to VDDQ/2.
`Analog input pin.
`
`Power input pin.
`
`Output voltage for connection to termination resistors.
`
`Exposed pad thermal connection. Connect to soft Ground.
`
`Ordering Information
`
`Order Number
`
`Package Type
`
`NSC Package Drawing
`
`Supplied As
`
`LP2998MA
`
`LP2998MAX
`
`LP2998MR
`
`LP2998MRX
`
`SO-8
`
`SO-8
`
`PSOP-8
`
`PSOP-8
`
`M08A
`
`M08A
`
`MRA08A
`
`MRA08A
`
`95 Units per Rail
`
`2500 Units Tape and Reel
`
`95 Units Tape and Reel
`
`2500 Units Tape and Reel
`
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`LP2998
`
`151°C/W
`
`43°C/W
`1kV
`
`-40°C to +125°C
`2.2V to 5.5V
`
`SO-8 Thermal Resistance (θJA)
`PSOP-8 Thermal Resistance (θJA)
`Minimum ESD Rating (Note 2)
`
`Operating Range
`Junction Temp. Range (Note 3)
`AVIN to GND
`
`Absolute Maximum Ratings (Note 1)
`If Military/Aerospace specified devices are required,
`please contact the National Semiconductor Sales Office/
`Distributors for availability and specifications.
`
`PVIN, AVIN, VDDQ to GND
`No pin should exceed AVIN
`Storage Temp. Range
`Junction Temperature
`Lead Temperature (Soldering, 10 sec)
`
`−0.3V to +6V
`−65°C to +150°C
`150°C
`260°C
`
`Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type
`apply over the full Operating Temperature Range (TJ = -40°C to +125°C) (Note 4). Unless otherwise specified,
`VIN = AVIN = PVIN = 2.5V.
`
`Symbol
`
`Parameter
`
`Conditions
`
`Min
`
`Typ Max Units
`
`VIN = VDDQ = 2.3V
`VIN = VDDQ = 2.5V
`VIN = VDDQ = 2.7V
`
`VREF Voltage (DDR I)
`
`VREF
`
`VREF Voltage (DDR II)
`
`ZVREF VREF Output Impedance
`
`VTT Output Voltage (DDR I) (Note 7)
`
`VTT
`
`VOSVtt
`
`VTT Output Voltage (DDR II) (Note 7)
`
`VTT Output Voltage Offset (VREF – VTT) for DDR I (Note 7)
`
`1.135 1.150 1.185
`1.235 1.250 1.285
`1.335 1.350 1.385
`
`0.837 0.850 0.887
`0.887 0.910 0.937
`0.936 0.950 0.986
`
`
`
`
`
`2.5
`
`
`
`
`
`
`
`1.120 1.150 1.190
`1.210 1.250 1.290
`1.320 1.350 1.390
`
`
`
`
`1.125 1.150 1.190
`1.225 1.250 1.290
`1.325 1.350 1.390
`
`
`
`
`
`
`
`0.822 0.850 0.887
`0.874 0.900 0.939
`0.923 0.950 0.988
`
`
`
`
`0.820 0.850 0.890
`0.870 0.900 0.940
`0.920 0.950 0.990
`
`V
`V
`V
`
`V
`V
`V
`kΩ
`
`
`V
`V
`V
`
`
`V
`V
`V
`
`
`
`V
`V
`V
`
`
`V
`V
`V
`
`-30
`
`-30
`
`-30
`
`0
`
`0
`
`0
`
`30
`
`30
`
`30
`
`mV
`
`mV
`
`mV
`
`PVIN = VDDQ = 1.7V
`PVIN = VDDQ = 1.8V
`PVIN = VDDQ = 1.9V
`IREF = -30 to +30 µA
`IOUT = 0A
` VIN = VDDQ = 2.3V
` VIN = VDDQ = 2.5V
` VIN = VDDQ = 2.7V
`IOUT = +/- 1.5A
` VIN = VDDQ = 2.3V
` VIN = VDDQ = 2.5V
` VIN = VDDQ = 2.7V
`IOUT = 0A, AVIN = 2.5V
` PVIN = VDDQ = 1.7V
` PVIN = VDDQ = 1.8V
` PVIN = VDDQ = 1.9V
`IOUT = +/- 0.5A, AVIN = 2.5V
` PVIN = VDDQ = 1.7V
` PVIN = VDDQ = 1.8V
` PVIN = VDDQ = 1.9V
`IOUT = 0A
`IOUT = -1.5A
`IOUT = +1.5A
`
`IOUT = 0A
`IOUT = -0.5A
`IOUT = +0.5A
`IOUT = 0A
`
`
`SD = 0V
`
`SD = 0V
`
`
`
`
`
`SD = 0V
`VTT = 1.25V
`
`
`
`-30
`
`-30
`
`-30
`
`
`
`
`
`
`
`
`
`1.9
`
`
`
`
`
`
`
`
`0
`
`0
`
`0
`
`320
`
`100
`
`115
`
`2
`
`
`
`
`
`1
`
`
`30
`
`30
`
`30
`
`500
`
`
`
`150
`
`5
`
`
`
`0.8
`
`10
`
`13
`
`
`
`
`mV
`
`mV
`
`mV
`
`µA
`kΩ
`µA
`
`µA
`
`V
`
`V
`
`µA
`
`nA
`
`3
`
`www.national.com
`
`VTT Output Voltage Offset (VREF – VTT) for DDR II (Note 7)
`
`Quiescent Current (Note 5)
`
`IQ
`ZVDDQ VDDQ Input Impedance
`Quiescent current in shutdown (Note 6)
`ISD
`IQ_SD
`VIH
`VIL
`Iv
`
`Shutdown leakage current
`
`Minimum Shutdown High Level
`
`Maximum Shutdown Low Level
`
`VTT leakage current in shutdown
`
`ISENSE VSENSE Input current
`
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`Conditions
`
`Min
`
`Typ Max Units
`
`
`
`
`
`
`
`
`
`165
`
`10
`
`
`
`
`
`°C
`
`°C
`
`Symbol
`TSD
`TSD_HYS Thermal Shutdown Hysteresis
`
`Thermal Shutdown (Note 6)
`
`Parameter
`
`LP2998
`
`Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
`intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics.
`The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
`the listed test conditions.
`Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
`Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2° C/W
`junction to ambient with no heat sink.
`
`Note 4: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
`Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
`
`Note 5: Quiescent current defined as the current flow into AVIN.
`Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA,
`and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
`shutdown.
`Note 7: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.
`
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`LP2998
`
`Typical Performance Characteristics
`
`Iq vs AVIN in SD
`
`Iq vs AVIN
`
`30026920
`
`30026921
`
`VIH and VIL
`
`VREF vs VDDQ
`
`30026922
`
`30026924
`
`VTT vs VDDQ
`
`Iq vs AVIN in SD Temperature
`
`30026926
`
`30026927
`
`5
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`Iq vs AVIN Temperature
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 1.8V, PVIN = 1.8V)
`
`LP2998
`
`30026928
`
`30026935
`
`Maximum Sinking Current vs AVIN
`(VDDQ = 1.8V)
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 2.5V, PVIN = 1.8V)
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 2.5V, PVIN = 2.5V)
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 2.5V, PVIN = 3.3V)
`
`30026936
`
`30026931
`
`30026932
`
`30026933
`
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`LP2998
`
`Maximum Sinking Current vs AVIN
`(VDDQ = 2.5V)
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 1.8V, PVIN = 3.3V)
`
`30026934
`
`30026937
`
`7
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`Block Diagram
`
`LP2998
`
`Description
`The LP2998 is a linear bus termination regulator designed to
`meet the JEDEC requirements of SSTL-2 and SSTL-18. The
`output, VTT is capable of sinking and sourcing current while
`regulating the output voltage equal to VDDQ / 2. The output
`stage has been designed to maintain excellent load regulation
`while preventing shoot through. The LP2998 also incorpo-
`rates two distinct power rails that separates the analog cir-
`cuitry from the power output stage. This allows a split rail
`approach to be utilized to decrease internal power dissipation.
`It also permits the LP2998 to provide a termination solution
`for the next generation of DDR-SDRAM memory (DDRII). The
`LP2998 can also be used to provide a termination voltage for
`other logic schemes such as SSTL-3 or HSTL.
`Series Stub Termination Logic (SSTL) was created to im-
`prove signal integrity of the data transmission across the
`memory bus. This termination scheme is essential to prevent
`data error from signal reflections while transmitting at high
`frequencies encountered with DDR-SDRAM. The most com-
`mon form of termination is Class II single parallel termination.
`This involves one RS series resistor from the chipset to the
`memory and one RT termination resistor. Typical values for
`RS and RT are 25 Ohms, although these can be changed to
`scale the current requirements from the LP2998. This imple-
`mentation can be seen below in .
`
`FIGURE 1. SSTL-Termination Scheme
`
`30026906
`
`Pin Descriptions
`
`AVIN AND PVIN
`AVIN and PVIN are the input supply pins for the LP2998. AVIN
`is used to supply all the internal control circuitry. PVIN, how-
`
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`
`8
`
`30026905
`
`ever, is used exclusively to provide the rail voltage for the
`output stage used to create VTT. These pins have the capa-
`bility to work off separate supplies, under the condition that
`AVIN is always greater than or equal to PVIN. For SSTL-18
`applications, it is recommended to connect PVIN to the 1.8V
`rail used for the memory core and AVIN to a rail within its
`operating range of 2.2V to 5.5V (typically a 2.5V supply). PVIN
`should always be used with either a 1.8V or 2.5V rail. This
`prevents the thermal limit from tripping because of excessive
`internal power dissipation. If the junction temperature ex-
`ceeds the thermal shutdown than the part will enter a shut-
`down state identical to the manual shutdown where VTT is tri-
`stated and VREF remains active. A lower rail such as 1.5V can
`be used but it will reduce the maximum output current, there-
`fore it is not recommended for most termination schemes.
`
`VDDQ
`VDDQ is the input used to create the internal reference volt-
`age for regulating VTT. The reference voltage is generated
`from a resistor divider of two internal 50kΩ resistors. This
`guarantees that VTT will track VDDQ / 2 precisely. The optimal
`implementation of VDDQ is as a remote sense. This can be
`achieved by connecting VDDQ directly to the 1.8V rail at the
`DIMM instead of PVIN. This ensures that the reference volt-
`age tracks the DDR memory rails precisely without a large
`voltage drop from the power lines. For SSTL-18 applications
`VDDQ will be a 1.8V signal, which will create a 0.9V termina-
`tion voltage at VTT (See Electrical Characteristics Table for
`exact values of VTT over temperature).
`
`VSENSE
`The purpose of the sense pin is to provide improved remote
`load regulation. In most motherboard applications the termi-
`nation resistors will connect to VTT in a long plane. If the output
`voltage was regulated only at the output of the LP2998 then
`the long trace will cause a significant IR drop resulting in a
`termination voltage lower at one end of the bus than the other.
`The VSENSE pin can be used to improve this performance, by
`connecting it to the middle of the bus. This will provide a better
`distribution across the entire termination bus. If remote load
`regulation is not used then the VSENSE pin must still be con-
`nected to VTT. Care should be taken when a long VSENSE trace
`is implemented in close proximity to the memory. Noise pick-
`up in the VSENSE trace can cause problems with precise
`regulation of VTT. A small 0.1uF ceramic capacitor placed next
`to the VSENSE pin can help filter any high frequency signals
`and preventing errors.
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`LP2998
`
`tion and the requirements for load transient response of VTT.
`As a general recommendation the output capacitor should be
`sized above 100 µF with a low ESR for SSTL applications with
`DDR-SDRAM. The value of ESR should be determined by the
`maximum current spikes expected and the extent at which the
`output voltage is allowed to droop. Several capacitor options
`are available on the market and a few of these are highlighted
`below:
`AL - It should be noted that many aluminum electrolytics only
`specify impedance at a frequency of 120 Hz, which indicates
`they have poor high frequency performance. Only aluminum
`electrolytics that have an impedance specified at a higher fre-
`quency (100 kHz) should be used for the LP2998. To improve
`the ESR several AL electrolytics can be combined in parallel
`for an overall reduction. An important note to be aware of is
`the extent at which the ESR will change over temperature.
`Aluminum electrolytic capacitors can have their ESR rapidly
`increase at cold temperatures.
`Ceramic - Ceramic capacitors typically have a low capaci-
`tance, in the range of 10 to 100 µF range, but they have
`excellent AC performance for bypassing noise because of
`very low ESR (typically less than 10 mΩ). However, some
`dielectric types do not have good capacitance characteristics
`as a function of voltage and temperature. Because of the typ-
`ically low value of capacitance it is recommended to use
`ceramic capacitors in parallel with another capacitor such as
`an aluminum electrolytic. A dielectric of X5R or better is rec-
`ommended for all ceramic capacitors.
`Hybrid - Several hybrid capacitors such as OS-CON and SP
`are available from several manufacturers. These offer a large
`capacitance while maintaining a low ESR. These are the best
`solution when size and performance are critical, although
`their cost is typically higher than any other capacitors.
`
`Thermal Dissipation
`Since the LP2998 is a linear regulator any current flow from
`VTT will result in internal power dissipation generating heat.
`To prevent damaging the part by exceeding the maximum al-
`lowable junction temperature, care should be taken to derate
`the part dependent on the maximum expected ambient tem-
`perature and power dissipation. The maximum allowable in-
`ternal temperature rise (TRmax) can be calculated given the
`maximum ambient temperature (TAmax) of the application and
`the maximum allowable junction temperature (TJmax).
`TRmax = TJmax − TAmax
`From this equation, the maximum power dissipation (PDmax)
`of the part can be calculated:
`PDmax = TRmax / θJA
`The θJA of the LP2998 will be dependent on several variables:
`the package used; the thickness of copper; the number of vias
`and the airflow. For instance, the θJA of the SO-8 is 163°C/W
`with the package mounted to a standard 8x4 2-layer board
`with 1oz. copper, no airflow, and 0.5W dissipation at room
`temperature. This value can be reduced to 151.2°C/W by
`changing to a 3x4 board with 2 oz. copper that is the JEDEC
`standard. Figure 2 shows how the θJA varies with airflow for
`the two boards mentioned.
`
`9
`
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`
`SHUTDOWN
`The LP2998 contains an active low shutdown pin that can be
`used for suspend to RAM functionality. In this condition the
`VTT output will tri-state while the VREF output remains active
`providing a constant reference signal for the memory and
`chipset. During shutdown VTT should not be exposed to volt-
`ages that exceed PVIN. With the shutdown pin asserted low
`the quiescent current of the LP2998 will drop, however, VD-
`DQ will always maintain its constant impedance of 100kΩ for
`generating the internal reference. Therefore, to calculate the
`total power loss in shutdown both currents need to be con-
`sidered. For more information refer to the Thermal Dissipation
`section. The shutdown pin also has an internal pull-up current;
`therefore, to turn the part on the shutdown pin can either be
`connected to AVIN or left open
`
`VREF
`VREF provides the buffered output of the internal reference
`voltage VDDQ / 2. This output should be used to provide the
`reference voltage for the Northbridge chipset and memory.
`Since these inputs are typically an extremely high impedance,
`there should be little current drawn from VREF. For improved
`performance, an output bypass capacitor can be used, locat-
`ed close to the pin, to help with noise. A ceramic capacitor in
`the range of 0.1 µF to 0.01 µF is recommended. This output
`remains active during the shutdown state and thermal shut-
`down events for the suspend to RAM functionality.
`
`VTT
`VTT is the regulated output that is used to terminate the bus
`resistors. It is capable of sinking and sourcing current while
`regulating the output precisely to VDDQ / 2. The LP2998 is
`designed to handle continuous currents of up to +/- 1.5A with
`excellent load regulation. If a transient is expected to last
`above the maximum continuous current rating for a significant
`amount of time, then the bulk output capacitor should be sized
`large enough to prevent an excessive voltage drop. If the
`LP2998 is to operate in elevated temperatures for long dura-
`tions care should be taken to ensure that the maximum junc-
`tion temperature is not exceeded. Proper thermal de-rating
`should always be used. (Please refer to the Thermal Dissi-
`pation section) If the junction temperature exceeds the ther-
`mal shutdown point than VTT will tri-state until the part returns
`below the temperature hysteresis trip-point
`
`Component Selections
`
`INPUT CAPACITOR
`The LP2998 does not require a capacitor for input stability,
`but it is recommended for improved performance during large
`load transients to prevent the input rail from dropping. The
`input capacitor should be located as close as possible to the
`PVIN pin. Several recommendations exist dependent on the
`application required. A typical value recommended for AL
`electrolytic capacitors is 22 µF. Ceramic capacitors can also
`be used. A value in the range of 10 µF with X5R or better
`would be an ideal choice. The input capacitance can be re-
`duced if the LP2998 is placed close to the bulk capacitance
`from the output of the 1.8V DC-DC converter. For the AVIN
`pin, a small 0.1uF ceramic capacitor is sufficient to prevent
`excessive noise from coupling into the device.
`
`OUTPUT CAPACITOR
`The LP2998 has been designed to be insensitive of output
`capacitor size or ESR (Equivalent Series Resistance). This
`allows the flexibility to use any capacitor desired. The choice
`for output capacitor will be determined solely on the applica-
`
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`sources of loss: output current at VTT, either sinking or sourc-
`ing, and quiescent current at AVIN and VDDQ. During the
`active state (when shutdown is not held low) the total internal
`power dissipation can be calculated from the following equa-
`tions:
`
`Where,
`
`PD = PAVIN + PVDDQ + PVTT
`
`PAVIN = IAVIN * VAVIN
`
`PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
`To calculate the maximum power dissipation at VTT both con-
`ditions at VTT need to be examined, sinking and sourcing
`current. Although only one equation will add into the total,
`VTT cannot source and sink current simultaneously.
`PVTT = VVTT x ILOAD (Sinking) or
`
`PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)
`The power dissipation of the LP2998 can also be calculated
`during the shutdown state. During this condition the output
`VTT will tri-state, therefore that term in the power equation will
`disappear as it cannot sink or source any current (leakage is
`negligible). The only losses during shutdown will be the re-
`duced quiescent current at AVIN and the constant impedance
`that is seen at the VDDQ pin.
`
`PD = PAVIN + PVDDQ
`
`PAVIN = IAVIN x VAVIN
`
`PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
`
`FIGURE 2. θJA vs Airflow (SO-8)
`
`30026907
`
`Additional improvements can be made by the judicious use of
`vias to connect the part and dissipate heat to an internal
`ground plane. Using larger traces and more copper on the top
`side of the board can also help. With careful layout it is pos-
`sible to reduce the θJA further than the nominal values shown
`in Figure 2
`Optimizing the θJA and placing the LP2998 in a section of a
`board exposed to lower ambient temperature allows the part
`to operate with higher power dissipation. The internal power
`dissipation can be calculated by summing the three main
`
`LP2998
`
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`LP2998
`
`Typical Application Circuits
`Several different application circuits have been shown in Fig-
`ure 5 through Figure 12 to illustrate some of the options that
`are possible in configuring the LP2998. Graphs of the indi-
`vidual circuit performance can be found in the Typical Perfor-
`mance Characteristics section in the beginning of the
`datasheet. These curves illustrate how the maximum output
`current is affected by changes in AVIN and PVIN.
`
`SSTL-2 APPLICATIONS
`For the majority of applications that implement the SSTL-2
`termination scheme it is recommended to connect all the input
`rails to the 2.5V rail. This provides an optimal trade-off be-
`tween power dissipation and component count and selection.
`An example of this circuit can be seen in Figure 5.
`
`FIGURE 3. Recommended SSTL-2 Implementation
`
`30026910
`
`If power dissipation or efficiency is a major concern then the
`LP2998 has the ability to operate on split power rails. The
`output stage (PVIN) can be operated on a lower rail such as
`1.8V and the analog circuitry (AVIN) can be connected to a
`higher rail such as 2.5V, 3.3V or 5V. This allows the internal
`power dissipation to be lowered when sourcing current from
`
`VTT. The disadvantage of this circuit is that the maximum
`continuous current is reduced because of the lower rail volt-
`age, although it is adequate for all motherboard SSTL-2 ap-
`plications. Increasing the output capacitance can also help if
`periods of large load transients will be encountered.
`
`FIGURE 4. Lower Power Dissipation SSTL-2 Implementation
`
`30026911
`
`The third option for SSTL-2 applications in the situation that
`a 1.8V rail is not available and it is not desirable to use 2.5V,
`is to connect the LP2998 power rail to 3.3V. In this situation
`AVIN will be limited to operation on the 3.3V or 5V rail as PVIN
`can never exceed AVIN. This configuration has the ability to
`provide the maximum continuous output current at the down-
`
`side of higher thermal dissipation. Care should be taken to
`prevent the LP2998 from experiencing large current levels
`which cause the junction temperature to exceed the maxi-
`mum. Because of this risk it is not recommended to supply
`the output stage with a voltage higher than a nominal 3.3V
`rail.
`
`11
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`

`FIGURE 5. SSTL-2 Implementation with higher voltage rails
`
`30026912
`
`DDR-II APPLICATIONS
`With the separate VDDQ pin and an internal resistor divider
`it is possible to use the LP2998 in applications utilizing DDR-
`II memory. Figure 6 and Figure 7 show several implementa-
`tions of recommended circuits with output curves displayed
`
`in the Typical Performance Characteristics. Figure 6 shows
`the recommended circuit configuration for DDR-II applica-
`tions. The output stage is connected to the 1.8V rail and the
`AVIN pin can be connected to either a 3.3V or 5V rail.
`
`FIGURE 6. Recommended DDR-II Termination
`
`30026913
`
`If it is not desirable to use the 1.8V rail it is possible to connect
`the output stage to a 3.3V rail. Care should be taken to not
`exceed the maximum junction temperature as the thermal
`dissipation increases with lower VTT output voltages. For this
`
`reason it is not recommended to power PVIN off a rail higher
`than the nominal 3.3V. The advantage of this configuration is
`that it has the ability to source and sink a higher maximum
`continuous current.
`
`FIGURE 7. DDR-II Termination with higher voltage rails
`
`30026914
`
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`
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`

`LP2998
`
`LEVEL SHIFTING
`If standards other than SSTL-2 are required, such as SSTL-3,
`it may be necessary to use a different scaling factor than 0.5
`times VDDQ for regulating the output voltage. Several options
`are available to scale the output to any voltage required. One
`method is to level shift the output by using feedback resistors
`
`from VTT to the VSENSE pin. This has been illustrated in Figures
`10 and 11. Figure 10 shows how to use two resistors to level
`shift VTT above the internal reference voltage of VDDQ/2. To
`calculate the exact voltage at VTT the following equation can
`be used.
`
`VTT = VDDQ/2 ( 1 + R1/R2)
`
`FIGURE 8. Increasing VTT by Level Shifting
`
`30026915
`
`Conversely, the R2 resistor can be placed between VSENSE
`and VDDQ to shift the VTT output lower than the internal refer-
`ence voltage of VDDQ/2. The equations relating VTT and the
`resistors can be seen below:
`
`VTT = VDDQ/2 (1 - R1/R2)
`
`FIGURE 9. Decreasing VTT by Level Shifting
`
`30026916
`
`HSTL APPLICATIONS
`The LP2998 can be easily adapted for HSTL applications by
`connecting VDDQ to the 1.5V rail. This will produce a VTT and
`
`VREF voltage of approximately 0.75V for the termination re-
`sistors. AVIN and PVIN should be connected to a 2.5V rail for
`optimal performance.
`
`FIGURE 10. HSTL Application
`
`30026917
`
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`

`tor divider or one of the LP2998 signals. Because VREF and
`VTT are expected to track and the part to part variations are
`minor, there should be little difference between the reference
`signals of each LP2998.
`
`OUTPUT CAPACITOR SELECTION
`For applications utilizing the LP2998 to terminate SSTL-2 I/O
`signals the typical application circuit shown in Figure 9 can be
`implemented.
`
`QDR APPLICATIONS
`Quad data rate (QDR) applications utilize multiple channels
`for improved memory performance. However, this increase in
`bus lines has the effect of increasing the current levels re-
`quired for termination. The recommended approach in termi-
`nating multiple channels is to use a dedicated LP2998 for
`each channel. This simplifies layout and reduces the internal
`power dissipation for each regulator. Separate VREF signals
`can be used for each DIMM bank from the corresponding
`regulator with the chipset reference provided by a local resis-
`
`LP2998
`
`FIGURE 11. Typical SSTL-2 Application Circuit
`
`30026918
`
`This circuit permits termination in a minimum amount of board
`space and component count. Capacitor selection can be var-
`ied depending on the number of lines terminated and the
`maximum load transient. However, with motherboards and
`other applications where VTT is distributed across a long plane
`it is advisable to use multiple bulk capacitors and addition to
`
`high frequency decoupling. Figure 10 shown below depicts
`an example circuit where 2 bulk output capacitors could be
`situated at both ends of the VTT plane for optimal placement.
`Large aluminum electrolytic capacitors are used for their low
`ESR and low cost.
`
`FIGURE 12. Typical SSTL-2 Application Circuit for Motherboards
`
`30026919
`
`In most PC applications an extensive amount of decoupling
`is required because of the long interconnects encountered
`with the DDR-SDRAM DIMMs mounted on modules. As a re-
`
`sult bulk aluminum electrolytic capacitors in the range of
`1000uF are typically used.
`
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`
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`

`LP2998
`
`PCB Layout Considerations
`1. The input capacitor for the power rail should be placed
`as close as possible to the PVIN pin.
`2. VSENSE should be connected to the VTT termination bus
`at the point where regulation is required. For
`motherboard applications an ideal location would be at
`the center of the termination bus.
`3. VDDQ can be connected remotely to the VDDQ rail input at
`either the DIMM or the Chipset. This provides the most
`accurate point for creating the reference voltage.
`4. For improved thermal performance excessive top side
`copper should be used to dissipate heat from the
`
`package. Numerous vias from the ground connection to
`the internal ground plane will help. Additionally these can
`be located underneath the package if manufacturing
`standards permit.
`5. Care should be taken when routing the VSENSE trace to
`avoid noise pickup from switching I/O signals. A 0.1uF
`ceramic capacitor located close to the SENSE can also be
`used to filter any unwanted high frequency signal. This
`can be an issue especially if long SENSE traces are used.
`6. VREF should be bypassed with a 0.01 µF or 0.1 µF
`ceramic capacitor for improved performance. This
`capacitor should be located as close as possible to the
`VREF pin.
`
`15
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`

`Physical Dimensions inches (millimeters) unless otherwise noted
`
`LP2998
`
`8-Lead Small Outline Package (M8)
`NS Package Number M08A
`
`8-Lead PSOP Package (PSOP-8)
`NS Package Number MRA08A
`
`www.national.com
`
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`

`LP2998
`
`Notes
`
`17
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`

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