LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002 –REVISED DECEMBER 2016
`
`LP2996-N, LP2996A DDR Termination Regulator
`An additional
`feature found on the LP2996-N and
`LP2996A is an active-low shutdown (SD) pin that
`provides Suspend To RAM (STR) functionality. When
`SD is pulled low the VTT output will tri-state providing
`a high impedance output, but VREF remains active. A
`power savings advantage can be obtained in this
`mode through lower quiescent current.
`TI recommends the LP2998 and LP2998-Q1 devices
`for automotive applications and DDR applications that
`require operating at temperatures below zero.
`WEBENCH® design tools can be used by application
`designers to generate, optimize, and simlulate
`applications using the LP2998 and LP2998-Q1.
`
`1 Features
`1• Minimum VDDQ:
`– 1.8 V (LP2996-N)
`– 1.35 V (LP2996A)
`• Source and Sink Current
`•
`Low Output Voltage Offset
`• No External Resistors Required for Setting Output
`Voltage
`Linear Topology
`•
`• Suspend to Ram (STR) Functionality
`• Stable With Ceramic Capacitors With Appropriate
`ESR
`Low External Component Count
`•
`• Thermal Shutdown
`2 Applications
`•
`LP2996-N: DDR1 and DDR2 Termination Voltage
`•
`LP2996A: DDR1, DDR2, DDR3, and DDR3L
`Termination Voltage
`• FPGA
`•
`Industrial and Medical PC
`• SSTL-2 and SSTL-3 Termination
`• HSTL Termination
`3 Description
`The LP2996-N and LP2996A linear regulators are
`designed to meet the JEDEC SSTL-2 specifications
`for
`termination of DDR-SDRAM. The device also
`supports DDR2, while LP2996A supports DDR3 and
`DDR3L VTT bus termination with VDDQ minimum of
`1.35 V. The device contains a high-speed operational
`amplifier
`to provide excellent
`response to load
`transients. The output stage prevents shoot through
`while delivering 1.5-A continuous
`current and
`transient peaks up to 3 A in the application as
`required for DDR-SDRAM termination. The LP2996-N
`and LP2996A also incorporate a VSENSE pin to
`provide superior load regulation and a VREF output
`as a reference for the chipset and DIMMs.
`
`Device Information(1)
`PACKAGE
`BODY SIZE (NOM)
`PART NUMBER
`SOIC (8)
`4.90 mm x 3.90 mm
`LP2996-N
`LP2996-N, LP2996A WSON (8)
`4.90 mm x 3.90 mm
`LP2996-N
`WQFN (16)
`4.00 mm x 4.00 mm
`(1) For all available packages, see the orderable addendum at
`the end of the data sheet.
`
`Simplified Schematic
`
`1
`
`An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
`intellectual property matters and other important disclaimers. PRODUCTION DATA.
`
`SD
`
`VDDQ = 1.5 V
`
`VDD = 2.5 V
`
`LP2996A
`
`SD
`
`VDDQ
`
`AVIN
`
`PVIN
`
`VREF
`
`VSENSE
`
`VTT
`
`+
`
`47 PF
`
`GND
`
`VREF = 0.75 V
`
`+
`
`0.01PF
`
`VTT = 0.75 V
`
`36 (cid:13)
`
`220 PF
`
`Copyright © 2016, Texas Instruments Incorporated
`
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`

`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`www.ti.com
`
`Table of Contents
`Features .................................................................. 1
`1
`8 Applications and Implementation ...................... 12
`2 Applications ........................................................... 1
`8.1 Application Information............................................ 12
`8.2 Typical Applications ................................................ 12
`3 Description ............................................................. 1
`9 Power Supply Recommendations...................... 18
`4 Revision History..................................................... 2
`10 Layout................................................................... 19
`5 Pin Configuration and Functions ......................... 3
`10.1 Layout Guidelines ................................................. 19
`6 Specifications......................................................... 5
`10.2 Layout Examples................................................... 19
`6.1 Absolute Maximum Ratings ...................................... 5
`10.3 Thermal Considerations........................................ 20
`6.2 ESD Ratings.............................................................. 5
`11 Device and Documentation Support ................. 23
`6.3 Recommended Operating Conditions....................... 5
`11.1 Documentation Support ........................................ 23
`6.4 Thermal Information.................................................. 5
`11.2 Related Links ........................................................ 23
`6.5 Electrical Characteristics........................................... 6
`11.3 Receiving Notification of Documentation Updates 23
`6.6 Typical Characteristics.............................................. 7
`11.4 Community Resources.......................................... 23
`7 Detailed Description ............................................ 10
`11.5 Trademarks ........................................................... 23
`7.1 Overview ................................................................. 10
`11.6 Electrostatic Discharge Caution............................ 23
`7.2 Functional Block Diagram ...................................... 10
`11.7 Glossary ................................................................ 23
`7.3 Feature Description................................................. 11
`12 Mechanical, Packaging, and Orderable
`7.4 Device Functional Modes........................................ 11
`Information ........................................................... 23
`
`4 Revision History
`NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
`
`Changes from Revision J (March 2013) to Revision K
`
`Page
`
`• Added Device Information table, Specifications section, ESD Ratings table, Thermal Information table, Feature
`Description section, Device Functional Modes section, Application and Implementation section, Power Supply
`Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
`Packaging, and Orderable Information section ...................................................................................................................... 1
`• Added LP2996A throughout data sheet ................................................................................................................................. 1
`• Added DDR3 support throughout data sheet ......................................................................................................................... 1
`• Deleted Lead temperature (260°C maximum) from Absolute Maximum Ratings .................................................................. 5
`• Changed Thermal Resistance, RθJA, values in Thermal Information From: 151°C/W To: 119.5°C/W (SOIC), From:
`151°C/W To: 56.5°C/W (SO), and From: 151°C/W To: 52.7°C/W (WQFN)........................................................................... 5
`
`Changes from Revision I (March 2013) to Revision J
`
`Page
`
`• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
`• Added VDDQ Range................................................................................................................................................................. 1
`
`2
`
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`5 Pin Configuration and Functions
`
`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`D Package
`8-Pin SOIC
`Top View
`
`DDA Package
`8-Pin SO With PowerPAD
`Top View
`
`NHP Package
`16-Pin WQFN
`Top View
`
`Pin Functions
`
`DESCRIPTION
`
`Analog input pin. AVIN is used to supply all the internal control circuitry. This pin has the capability
`to work from a supply separate from PVIN depending on the application. For SSTL-2 applications, a
`good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
`eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
`voltage selection is that PVIN must be equal to or lower than AVIN.
`Ground
`Power input pin. PVIN is used exclusively to provide the rail voltage for the output stage used to
`create VTT. This pin has the capability to work from a supply separate from PVIN depending on the
`application. Higher voltages on PVIN increases the maximum continuous output current because of
`output RDS(ON) limitations at voltages close to VTT. The disadvantage of high values of PVIN is that
`the internal power loss also increases, thermally limiting the design. For SSTL-2 applications, a
`good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This
`eliminates the requirement for bypassing the two supply pins separately. The only limitation on input
`voltage selection is that PVIN must be equal to or lower than AVIN. TI recommends connecting PVIN
`to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of
`excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown then
`the part enters a shutdown state identical to the manual shutdown where VTT is tri-stated and
`VREF remains active.
`
`PIN
`
`SO
`PowerPAD
`
`SOIC
`
`WQFN
`
`NAME
`
`AVIN
`
`GND
`
`PVIN
`
`6
`
`1
`
`7
`
`6
`
`1
`
`7
`
`I/O
`
`I
`
`—
`
`10
`
`2
`
`11, 12
`
`I
`
`Copyright © 2002–2016, Texas Instruments Incorporated
`Product Folder Links: LP2996-N LP2996A
`
`Submit Documentation Feedback
`
`3
`
`12
`
`11
`
`10
`
`9
`
`PVIN
`
`PVIN
`
`AVIN
`
`NC
`
`NC
`
`VTT
`
`VTT
`
`NC
`
`13
`
`14
`
`15
`
`16
`
`Thermal Pad
`
`5
`
`6
`
`7
`
`8
`
`Not to scale
`
`VDDQ
`
`VREF
`
`NC
`
`VSENSE
`
`NC
`
`GND
`
`NC
`
`SD
`
`1
`
`2
`
`3
`
`4
`
`GND
`
`SD
`
`VSENSE
`
`VREF
`
`1
`
`2
`
`3
`
`4
`
`PowerPAD
`
`8
`
`7
`
`6
`
`5
`
`VTT
`
`PVIN
`
`AVIN
`
`VDDQ
`
`Not to scale
`
`GND
`
`SD
`
`VSENSE
`
`VREF
`
`1
`
`2
`
`3
`
`4
`
`8
`
`7
`
`6
`
`5
`
`VTT
`
`PVIN
`
`AVIN
`
`VDDQ
`
`Not to scale
`
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`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`www.ti.com
`
`PIN
`
`SO
`PowerPAD
`
`SOIC
`
`WQFN
`
`I/O
`
`Pin Functions (continued)
`
`DESCRIPTION
`
`Shutdown. The LP2996-N and LP2996A contain an active low shutdown pin that can be used to tri-
`state VTT. During shutdown VTT must not be exposed to voltages that exceed AVIN. With the
`shutdown pin asserted low the quiescent current of the LP2996-N and LP2996A drops, however,
`VDDQ always maintains its constant impedance of 100 kΩ for generating the internal reference.
`Therefore, to calculate the total power loss in shutdown, both currents must be considered. See
`Thermal Considerations for more information. The shutdown pin also has an internal pullup current,
`therefore to turn the part on, the shutdown pin can either be connected to AVIN or left open.
`Input for internal reference equal to VDDQ / 2. VDDQ is the input used to create the internal
`reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of
`two internal 50-kΩ resistors. This ensures that VTT tracks VDDQ / 2 precisely. The optimal
`implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly
`to the 2.5-V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage
`tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-
`2 applications VDDQ is a 2.5-V signal, which creates a 1.25-V termination voltage at VTT. See
`Electrical Characteristics for exact values of VTT over temperature.
`Buffered internal reference voltage of VDDQ / 2. VREF provides the buffered output of the internal
`reference voltage VDDQ / 2. This output must be used to provide the reference voltage for the
`Northbridge chipset and memory. Because these inputs are typically an extremely high impedance,
`there must be little current drawn from VREF. For improved performance, an output bypass
`capacitor can be placed close to the pin to help reduce noise. TI recommends a ceramic capacitor
`from 0.1 µF to 0.01 µF. This output remains active during the shutdown state and thermal shutdown
`events for the suspend to RAM functionality.
`Feedback pin for regulating VTT. The purpose of the sense pin is to provide improved remote load
`regulation. In most motherboard applications the termination resistors connect to VTT in a long
`plane. If the output voltage was regulated only at the output of the device then the long trace
`causes a significant IR drop resulting in a termination voltage lower at one end of the bus than the
`other. The VSENSE pin can be used to improve this performance by connecting it to the middle of
`the bus. This provides a better distribution across the entire termination bus. If remote load
`regulation is not used then the VSENSE pin must still be connected to VTT. Take care when a long
`VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace
`can cause problems with precise regulation of VTT. A small 0.1-µF ceramic capacitor placed next to
`the VSENSE pin can help filter any high frequency signals and preventing errors.
`Output voltage for connection to termination resistors. VTT is the regulated output that is used to
`terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output
`precisely to VDDQ / 2. The LP2996-N and LP2996A are designed to handle peak transient currents
`of up to ±3 A with a fast transient response. The maximum continuous current is a function of VDD
`and can be seen in Typical Characteristics. If a transient above the maximum continuous current
`rating is expected to last for a significant amount of time then the output capacitor must be large
`enough to prevent an excessive voltage drop. Despite the fact that the device is designed to handle
`large transient output currents it is not capable of handling these for long durations under all
`conditions. The reason for this is the standard packages are not able to thermally dissipate the heat
`as a result of the internal power loss. If large currents are required for longer durations, then ensure
`that the maximum junction temperature is not exceeded. Proper thermal derating must always be
`used (see Thermal Considerations). If the junction temperature exceeds the thermal shutdown point
`then VTT tri-states until the part returns below the hysteretic trip-point.
`
`NAME
`
`SD
`
`VDDQ
`
`VREF
`
`VSENSE
`
`2
`
`5
`
`4
`
`3
`
`2
`
`5
`
`4
`
`3
`
`4
`
`8
`
`7
`
`5
`
`I
`
`I
`
`O
`
`I
`
`VTT
`
`8
`
`8
`
`14, 15
`
`O
`
`NC
`
`Thermal
`Pad
`
`—
`
`PowerPAD
`
`—
`
`—
`
`1, 3, 6,
`9, 13, 16
`Thermal
`Pad
`
`—
`
`—
`
`No internal connection
`
`Exposed pad thermal connection. Connect to Ground.
`
`4
`
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`6 Specifications
`6.1 Absolute Maximum Ratings
`over operating free-air temperature range (unless otherwise noted)(1)(2)
`
`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`MIN
`−0.3
`–0.3
`−0.3
`
`–65
`
`MAX
`6
`AVIN
`6
`150
`150
`
`UNIT
`V
`V
`V
`°C
`°C
`
`AVIN to GND
`PVIN to GND
`Input voltage (VDDQ)(3)
`Junction temperature, TJ
`Storage temperature, Tstg
`(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
`only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
`Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
`If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
`specifications.
`(3) VDDQ voltage must be less than 2 × (AVIN – 1) or 6 V, whichever is smaller.
`
`(2)
`
`6.2 ESD Ratings
`
`Electrostatic discharge
`
`V(ESD)
`(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
`
`Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
`
`6.3 Recommended Operating Conditions
`over operating free-air temperature range (unless otherwise noted)
`
`AVIN to GND
`PVIN supply voltage
`SD input voltage
`Junction temperature(1)
`
`TJ
`(1) At elevated temperatures, devices must be derated based on thermal resistance.
`
`VALUE
`±1000
`
`UNIT
`V
`
`MIN
`2.2
`0
`0
`0
`
`MAX
`5.5
`AVIN
`AVIN
`125
`
`UNIT
`V
`V
`V
`°C
`
`6.4 Thermal Information
`
`THERMAL METRIC
`
`RθJA
`RθJC(top)
`RθJB
`ψJT
`ψJB
`RθJC(bot)
`
`Junction-to-ambient thermal resistance
`Junction-to-case (top) thermal resistance
`Junction-to-board thermal resistance
`Junction-to-top characterization parameter
`Junction-to-board characterization parameter
`Junction-to-case (bottom) thermal resistance
`
`D (SOIC)
`8 PINS
`119.5
`65.3
`59.8
`16.7
`59.3
`—
`
`LP2996-N, LP2996A
`DDA (SO)
`8 PINS
`56.5
`65.1
`36.5
`15.9
`36.5
`8.4
`
`NHP (WQFN)
`16 PINS
`52.7
`50.1
`30.1
`0.7
`30.2
`9.8
`
`UNIT
`
`°C/W
`°C/W
`°C/W
`°C/W
`°C/W
`°C/W
`
`Copyright © 2002–2016, Texas Instruments Incorporated
`Product Folder Links: LP2996-N LP2996A
`
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`
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`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`www.ti.com
`
`6.5 Electrical Characteristics
`Minimum and maximum limits apply over the full operating temperature range (TJ = 0°C to 125°C) and are specified through
`test, design, or statistical correlation. Typical values represent the most likely parametric norm (TJ = 25°C), and are provided
`for reference purposes only. Unless otherwise specified, AVIN = PVIN = 2.5 V and VDDQ = 2.5 V.(1)
`PARAMETER
`TEST CONDITIONS
`MIN
`VDD = VDDQ = 2.3 V
`1.135
`VDD = VDDQ = 2.5 V
`1.235
`VDD = VDDQ = 2.7 V
`1.335
`PVIN = VDDQ = 1.7 V
`0.837
`PVIN = VDDQ = 1.8 V
`0.887
`PVIN = VDDQ = 1.9 V
`0.936
`PVIN = VDDQ = 1.35 V
`0.669
`PVIN = VDDQ = 1.5 V
`0.743
`PVIN = VDDQ = 1.6 V
`0.793
`IREF = –30 to 30 µA
`
`VREF voltage (DDR I)
`
`VREF
`
`VREF voltage (DDR II)
`
`VREF voltage (DDR III)
`
`ZVREF
`
`VREF output impedance
`
`VTT
`
`VTT output voltage (DDR I)(2)
`
`VTT output voltage (DDR II)(2)
`
`VTT output voltage (DDR III)(2)
`
`VTT output voltage offset
`(VREF – VTT) for DDR I(2)
`
`VOSVtt
`
`VTT output voltage offset
`(VREF – VTT) for DDR II(2)
`
`VTT output voltage offset
`(VREF – VTT) for DDR III(2)
`
`IQ
`
`Quiescent current(3)
`
`IOUT = 0 A
`
`IOUT = ±1.5 A
`
`IOUT = 0 A, AVIN = 2.5 V
`
`IOUT = ±0.5 A, AVIN = 2.5 V
`
`IOUT = 0 A, AVIN = 2.5 V
`
`VDD = VDDQ = 2.3 V
`VDD = VDDQ = 2.5 V
`VDD = VDDQ = 2.7 V
`VDD = VDDQ = 2.3 V
`VDD = VDDQ = 2.5 V
`VDD = VDDQ = 2.7 V
`PVIN = VDDQ = 1.7 V
`PVIN = VDDQ = 1.8 V
`PVIN = VDDQ = 1.9 V
`PVIN = VDDQ = 1.7 V
`PVIN = VDDQ = 1.8 V
`PVIN = VDDQ = 1.9 V
`PVIN = VDDQ = 1.35 V
`PVIN = VDDQ = 1.5 V
`PVIN = VDDQ = 1.6 V
`IOUT = 0.2 A, AVIN = 2.5 V, PVIN = VDDQ = 1.35 V
`IOUT = –0.2 A, AVIN = 2.5 V, PVIN = VDDQ = 1.35 V
`IOUT = 0.4 A, AVIN = 2.5 V, PVIN = VDDQ = 1.5 V
`IOUT = –0.4 A, AVIN = 2.5 V, PVIN = VDDQ = 1.5 V
`IOUT = 0.5 A, AVIN = 2.5 V, PVIN = VDDQ = 1.6 V
`IOUT = –0.5 A, AVIN = 2.5 V, PVIN = VDDQ = 1.6 V
`IOUT = 0 A
`IOUT = –1.5 A
`IOUT = 1.5 A
`IOUT = 0 A
`IOUT = –0.5 A
`IOUT = 0.5 A
`IOUT = 0 A
`IOUT = ±0.2 A
`IOUT = ±0.4 A
`IOUT = ±0.5 A
`IOUT = 0 A
`
`1.12
`1.21
`1.32
`1.125
`1.225
`1.325
`0.822
`0.874
`0.923
`0.82
`0.87
`0.92
`0.656
`0.731
`0.781
`0.667
`0.641
`0.74
`0.731
`0.79
`0.781
`–30
`–30
`–30
`–30
`–30
`–30
`–30
`–30
`–30
`–30
`
`TYP
`1.158
`1.258
`1.358
`0.86
`0.91
`0.959
`0.684
`0.758
`0.808
`2.5
`1.159
`1.259
`1.359
`1.159
`1.259
`1.359
`0.856
`0.908
`0.957
`0.856
`0.908
`0.957
`0.677
`0.752
`0.802
`0.688
`0.673
`0.763
`0.752
`0.813
`0.802
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`320
`
`V
`
`V
`
`MAX UNIT
`1.185
`1.285
`1.385
`0.887
`0.937
`0.986
`0.699
`0.773
`0.823
`
`V
`
`kΩ
`
`1.19
`1.29
`1.39
`1.19
`1.29
`1.39
`0.887
`0.939
`0.988
`0.89
`0.94
`0.99
`0.698
`0.773
`0.823
`0.71
`0.694
`0.786
`0.773
`0.836
`0.823
`30
`30
`30
`30
`30
`30
`30
`30
`30
`30
`500
`
`V
`
`V
`
`V
`
`mV
`
`mV
`
`mV
`
`µA
`
`(1) VDD is defined as VDD = AVIN = PVIN.
`(2) VTT load regulation is tested by using a 10-ms current pulse and measuring VTT.
`(3) Quiescent current defined as the current flow into AVIN.
`6
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`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`Electrical Characteristics (continued)
`Minimum and maximum limits apply over the full operating temperature range (TJ = 0°C to 125°C) and are specified through
`test, design, or statistical correlation. Typical values represent the most likely parametric norm (TJ = 25°C), and are provided
`for reference purposes only. Unless otherwise specified, AVIN = PVIN = 2.5 V and VDDQ = 2.5 V.(1)
`PARAMETER
`TEST CONDITIONS
`MIN
`VDDQ input impedance
`Quiescent current in shutdown(3) SD is low
`Shutdown leakage current
`SD is low
`Minimum shutdown, high level
`Maximum shutdown, low level
`VTT leakage current in shutdown SD is low, VTT = 1.25 V
`VSENSE input current
`Thermal shutdown
`Thermal shutdown hysteresis
`
`ZVDDQ
`ISD
`IQ_SD
`VIH
`VIL
`IV
`ISENSE
`TSD
`TSD_HYS
`
`1.9
`
`TYP
`100
`115
`2
`
`1
`13
`165
`10
`
`150
`5
`
`MAX UNIT
`kΩ
`µA
`µA
`V
`V
`µA
`nA
`°C
`°C
`
`0.8
`10
`
`6.6 Typical Characteristics
`Unless otherwise specified, AVIN = PVIN = 2.5 V.
`
`Figure 1. IQ vs AVIN In Shutdown
`
`Figure 2. IQ vs AVIN
`
`Figure 3. VIH and VIL
`
`Figure 4. VREF vs IREF
`
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`7
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`4
`
`3.5
`
`3
`
`2.5
`
`2
`
`1.5
`
`1
`
`0.5
`
`VSD (V)
`
`1.40
`
`1.35
`
`1.30
`
`1.25
`
`1.20
`
`1.15
`
`1.10
`
`VREF (V)
`
`-30
`
`-20
`
`-10
`
`0
`
`10
`
`20
`
`30
`
`IREF (uA)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`400
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`50
`
`IQ (uA)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`1050
`
`900
`
`750
`
`600
`
`450
`
`300
`
`150
`
`0
`
`IQ (uA)
`
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`
`Typical Characteristics (continued)
`Unless otherwise specified, AVIN = PVIN = 2.5 V.
`
`www.ti.com
`
`Figure 5. VREF vs VDDQ
`
`Figure 6. VTT vs IOUT
`
`Figure 7. VTT vs VDDQ
`
`Figure 8. IQ vs AVIN in Shutdown Temperature
`
`Figure 9. IQ vs AVIN Temperature
`
`PVIN = 1.8 V
`VDDQ = 2.5 V
`Figure 10. Maximum Sourcing Current vs AVIN
`
`8
`
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`
`85oC
`
`25oC
`
`0oC
`
`1050
`
`900
`
`750
`
`600
`
`450
`
`300
`
`150
`
`0
`
`IQ (uA)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0
`
`OUTPUT CURRENT (A)
`
`0
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`VDDQ (V)
`
`3
`
`2.5
`
`2
`
`1.5
`
`1
`
`0.5
`
`0
`
`VTT (V)
`
`0oC
`
`125oC
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AV IN (V)
`
`400
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`50
`
`IQ(uA)
`
`0
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`VDDQ (V)
`
`3
`
`2.5
`
`2
`
`1.5
`
`1
`
`0.5
`
`0
`
`VREF (V)
`
`1.275
`
`1.270
`
`1.265
`
`1.260
`
`1.255
`
`1.250
`
`1.245
`
`VTT (V)
`
`-100 -75
`
`-50
`
`-25
`
`0
`
`25
`
`50
`
`75
`
`100
`
`IOUT (mA)
`
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`Typical Characteristics (continued)
`Unless otherwise specified, AVIN = PVIN = 2.5 V.
`
`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`PVIN = 2.5 V
`VDDQ = 2.5 V
`Figure 11. Maximum Sourcing Current vs AVIN
`
`PVIN = 3.3 V
`VDDQ = 2.5 V
`Figure 12. Maximum Sourcing Current vs AVIN
`
`VDDQ = 2.5 V
`Figure 13. Maximum Sinking Current vs AVIN
`
`PVIN = 1.8 V
`VDDQ = 1.8 V
`Figure 14. Maximum Sourcing Current vs AVIN
`
`VDDQ = 1.8 V
`Figure 15. Maximum Sinking Current vs AVIN
`
`PVIN = 3.3 V
`VDDQ = 1.8 V
`Figure 16. Maximum Sourcing Current vs AVIN
`
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`
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`9
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`2.4
`
`2.2
`
`2
`
`1.8
`
`1.6
`
`1.4
`
`1.2
`
`1
`
`OUTPUT CURRENT (A)
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`3
`
`2.8
`
`2.6
`
`2.4
`
`2.2
`
`2
`
`3
`
`OUTPUT CURRENT (A)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`3.0
`
`2.8
`
`2.6
`
`2.4
`
`2.2
`
`2.0
`
`1.8
`
`1.6
`
`OUTPUT CURRENT (A)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`1.4
`
`1.2
`
`1
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0
`
`OUTPUT CURRENT (A)
`
`2
`
`2.5
`
`3
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`1.8
`
`1.7
`
`1.6
`
`1.5
`
`1.4
`
`1.3
`
`1.2
`
`1.1
`
`OUTPUT CURRENT (A)
`
`3.5
`
`4
`
`4.5
`
`5
`
`5.5
`
`AVIN (V)
`
`3
`
`2.8
`
`2.6
`
`2.4
`
`2.2
`
`2
`
`3
`
`OUTPUT CURRENT (A)
`
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`LP2996-N, LP2996A
`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`7 Detailed Description
`
`www.ti.com
`
`7.1 Overview
`The LP2996-N and LP2996A devices can be used to provide a termination voltage for additional logic schemes
`such as SSTL-3 or HSTL.
`Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
`memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
`at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
`parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination
`resistor. Typical values for RS and RT are 25 Ω, although these can be changed to scale the current
`requirements from the LP2996-N or LP2996A. This implementation is shown in Figure 17.
`
`Figure 17. SSTL-Termination Scheme
`
`7.2 Functional Block Diagram
`
`10
`
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`
`VTT
`
`VSENSE
`
`SD
`
`VDDQ
`
`AVIN
`
`PVIN
`
`- +
`
`50k
`
`50k
`
`+ -
`
`VREF
`
`GND
`
`Copyright © 2016, Texas Instruments Incorporated
`
`VDD
`
`VTT
`
`RT
`
`MEMORY
`
`RS
`
`CHIPSET
`
`VREF
`
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`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`
`7.3 Feature Description
`The LP2996-N and LP2996A are linear bus termination regulators designed to meet the JEDEC requirements of
`SSTL-2. The output (VTT) is capable of sinking and sourcing current while regulating the output voltage equal to
`VDDQ / 2. The output stage is designed to maintain excellent load regulation while preventing shoot through. The
`LP2996-N and LP2996A also incorporate two distinct power rails that separates the analog circuitry from the
`power output stage. This allows a split rail approach to be used to decrease internal power dissipation. It also
`permits the LP2996-N to provide a termination solution for DDR2-SDRAM, while the LP2996A supports DDR3-
`SDRAM and DDR3L-SDRAM memory. TI recommends the LP2998 and LP2998-Q1 for all DDR applications that
`require operation at below-zero temperatures.
`
`7.4 Device Functional Modes
`
`7.4.1 Start-Up
`During start up when VDDQ is enabled, the error amplifier senses the output voltage is low and drives the pass
`element hard causing a large inrush current. If this inrush current is too large, the device shuts down and restarts
`due to the internal current limit. Two solutions to prevent large inrush current during start up:
`1. Slow down the slew rate of VDDQ. When the slew rate of VDDQ is fast (approximately 60 µs), the input
`current can reach over 5 A which exceeds the device’s current limit thus causing a restart. If VDDQ start-up
`slew rate is ≥300 µs, the inrush current can be reduced by 90% limiting the input rush current to less than
`500mA.
`In some cases the system designers have very little to no control over the VDDQ voltage supply slew rate,
`whether using linear or switching regulators. Some step down voltage regulators do not have soft-start
`feature. VDDQ voltage source requires only 18 µA current
`to enable the DDRII
`termination voltage.
`Therefore placing an RC filter at VDDQ pin can conveniently increase the output voltage slew rate, allowing
`a slow rise in capacitor charge current. To keep the VDDQ voltage losses minimum, the resistor value must
`be chosen carefully. Using a 100-Ω resistor keeps the VDDQ supply voltage losses down to 1.8 mV,
`because the current through VDDQ is only 18 µA for DDRIII configuration.
`See Limiting DDR Termination Regulators’ Inrush Current (SNVA758) for more information relating to the inrush
`current during start up.
`
`2.
`
`7.4.2 Normal Operation
`The device contains a high-speed operational amplifier to provide excellent response to load transients. The
`output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in
`the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a
`VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
`See Electrical Characteristics and Application Information.
`
`7.4.3 Shutdown
`The LP2996-N and LP2996A feature an active-low shutdown (SD) pin that provides Suspend To RAM (STR)
`functionality. When SD is pulled low, the VTT output tri-states providing a high impedance output, but VREF
`remains active. A power savings advantage can be obtained in this mode through lower quiescent current.
`During shutdown, VTT must not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low
`the quiescent current of the LP2996-N and LP2996A drops, however, VDDQ always maintains its constant
`impedance of 100 kΩ for generating the internal reference. Therefore, to calculate the total power loss in
`shutdown, both currents must be considered. The shutdown pin also has an internal pullup current, therefore to
`turn the part on, the shutdown pin can either be connected to AVIN or left open.
`
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`
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`SNOSA40K –NOVEMBER 2002–REVISED DECEMBER 2016
`8 Applications and Implementation
`
`www.ti.com
`
`NOTE
`the TI component
`Information in the following applications sections is not part of
`specification, and TI does not warrant its accuracy or completeness. TI’s customers are
`responsible for determining suitability of components for their purposes. Customers should
`validate and test their design implementation to confirm system functionality.
`
`8.1 Application Information
`The LP2996 has split rails to allow flexibility in powering the device. It has a control circuitry rail (AVIN) and an
`output power stage rail (PVIN), both separate from the reference voltage input (VDDQ). This allows for different
`setups which cater to specific requirements such as high current capabilities, lower thermal dissipation, or
`minimum component count. Because the output is always VDDQ / 2 due to two internal 50-kΩ resistors, the only
`necessary external components are bypass capacitors.
`
`8.2 Typical Applications
`
`8.2.1 Typical SSTL-2 Application Circuit
`This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
`can be varied depending on the number of lines terminated and the maximum load transient. However, with
`motherboards and other applications where VTT is distributed across a long plane, it is advisable to use multiple
`bulk capacitors and addition to high frequency decoupling.
`
`Figure 18. Typical SSTL-2 Application Circuit Diagram
`
`8.2.1.1 Design Requirements
`For this design example, use the parameters listed in Table 1 as the input parameters.
`
`Table 1. Design Parameters
`
`PARAMETER
`VDDQ
`Input to AVIN and PVIN, VDD
`VREF
`VTT
`Input bypass capacitor, CIN
`Output bypass capacitor, COUT
`
`VALUE
`1.5 V
`2.5 V
`0.75 V
`0.75 V
`47 µF
`220 µF
`
`12
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`SD
`
`VDDQ = 1.5 V
`
`VDD = 2.5 V
`
`LP2996A
`
`SD
`
`VDDQ
`
`AVIN
`
`PVIN
`
`VREF
`
`VSENSE
`
`VTT
`
`+
`
`47 PF
`
`GND
`
`VREF = 0.75 V
`
`+
`
`0.01PF
`
`VTT = 0.75 V
`
`36 (cid:13)
`
`220 PF
`
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`
`8.2.1.2 Detailed Design Procedure
`The LP2996 requires voltage be applied to three pins for proper operation: VDDQ, AVIN, and PVIN. VDDQ sets
`the internal reference voltage and is divided across two 50-kΩ resistors. Therefore, VDDQ must be set at exactly
`twice the appropriate DDR termination. AVIN powers the internal control circuitry and must be from 2.2 V to
`5.5 V. PVIN is the supply for the power output stage and must be larger than or equal to VDDQ while smaller
`than or equal to AVIN. When picking PVIN, note that smaller values reduce internal power dissipation but reduce
`the maximum continuous current as well. It is acceptable to tie PVIN to either VDDQ or AVIN to minimize the
`number of supplies and bypass capacitors required.
`To prevent voltage dips on the output, a bypass capacitor must be placed on the VTT line. The size of this
`capacitor does not affect stability, but larger values improve the transient response and must be sized according
`to the design requirements. When using ceramic capacitors on the output, large load steps can cause ringing on
`VTT. Table 2 shows the range of acceptable equivalent series resistance (ESR) that can be added to dampen
`and improve the response.
`
`Table 2. Approximate ESR Values for VTT Capacitors
`VTT CAPACIT