(12) United States Patent
`Chen et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,301.833 B1
`Oct. 30, 2012
`
`USOO83 01833B1
`
`(54)
`(75)
`
`(73)
`(*)
`
`(21)
`(22)
`
`(63)
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`(56)
`
`NON-VOLATILE MEMORY MODULE
`
`Inventors: Chi-She Chen, Walnut, CA (US);
`Jeffrey C. Solomon, Irvine, CA (US);
`Scott Milton, Irvine, CA (US); Jayesh
`Bhakta, Cerritos, CA (US)
`Assignee: Netlist, Inc., Irvine, CA (US)
`Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 638 days.
`Appl. No.: 12/240,916
`Filed:
`Sep. 29, 2008
`
`Related U.S. Application Data
`Continuation of application No. 12/131,873, filed on
`Jun. 2, 2008, now abandoned.
`Provisional application No. 60/941,586, filed on Jun.
`1, 2007.
`
`Int. C.
`(2006.01)
`G06F 12/00
`U.S. C. ........ 711/104; 711/160; 711/161: 711/162:
`710/10
`Field of Classification Search .................. 711/160,
`711/161, 162, 104; 710/10
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`12/1983 Hoffman
`4.420,821 A
`5, 1984 Hoffman
`4,449,205 A
`
`5/1996 Harper, Jr. et al.
`5,519,663 A
`6,158,015 A 12/2000 Klein
`6,336,174 B1
`1/2002 Li et al.
`6,336,176 B1
`1/2002 Leyda et al.
`6,487.623 B1
`1 1/2002 Emerson et al.
`6,658,507 B1 12/2003 Chan
`6,799,244 B2
`9/2004 Tanaka et al.
`7,409,590 B2
`8/2008 Moshayedi et al.
`2002, 0083368 A1
`6/2002 Abe et al.
`2004/O190210 A1
`9, 2004 Leete
`2007,0192627 A1* 8, 2007 Oshikiri ........................ T13, 191
`2008/01958.06 A1* 8/2008 Cope ............................. T11 111
`* cited by examiner
`
`Primary Examiner — Midys Rojas
`(74) Attorney, Agent, or Firm — Nixon Peabody LLP:
`Khaled Shami
`
`(57)
`ABSTRACT
`Certain embodiments described herein include a memory
`system which can communicate with a host system such as a
`disk controller of a computer system. The memory system
`can include Volatile and non-volatile memory and a controller
`which are configured such that the controller backs up the
`Volatile memory using the non-volatile memory in the event
`of a trigger condition. In order to power the system in the
`event of a power failure or reduction, the memory system can
`include a secondary power source which is not a battery and
`may include, for example, a capacitor or capacitor array. The
`memory system can be configured such that the operation of
`the volatile memory is not adversely affected by the non
`volatile memory or the controller when the volatile memory is
`interacting with the host system.
`
`30 Claims, 12 Drawing Sheets
`
`322
`
`,
`
`57
`
`
`
`Operate volatile memory at first frequency
`in first mode
`
`Operate non-volatile memory at
`second frequency in second
`mode
`
`Operate volatile memory at
`third frequency in second
`mode
`
`Netlist Ex 2002-p. 1
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 1 of 12
`
`US 8,301.833 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INOONGOV;
`
`---??-
`----}-- -|- — — —
`—-- - - - - - - - - -
`
`Zºzº
`----
`
`Netlist Ex 2002-p. 2
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`US 8,301.833 B1
`
`
`
`
`Netlist Ex 2002-p. 3
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`US 8,301.833 B1
`
`| ||
`
`
`
`
`
`
`
`Netlist Ex 2002-p. 4
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 4 of 12
`
`US 8,301.833 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`6247/(79/
`
`(247/
`
`Netlist Ex 2002-p. 5
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`US 8,301.833 B1
`
`
`
`
`
`
`
`
`
`
`ppA
`
`Netlist Ex 2002-p. 6
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 6 of 12
`
`US 8,301.833 B1
`
`?Z9/ - | |-------------J
`
`|
`
`| ~
`
`
`
`
`
`
`
`
`
`
`
`
`
`ppA
`
`pu6
`
`Netlist Ex 2002-p. 7
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 7 of 12
`
`US 8,301.833 B1
`
`272 /
`
`
`
`Provide first voltage from input power supply
`and second Voltage from first power subsystem
`
`SeCOnd COndition detected?
`
`Provide first voltage and second voltage from
`first power subsystem
`
`Charge Second power Subsystem
`
`Third Condition detected?
`
`Provide first voltage and second voltage from
`Second power Subsystem
`
`FIG. 6
`
`Netlist Ex 2002-p. 8
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 8 of 12
`
`US 8,301.833 B1
`
`367/7
`
`Communicate data between Volatile
`memory and host system in a first mode
`
`37/7
`
`
`
`Store a first copy of data from the volatile
`memory to the non-volatile memory when
`in a second mode
`
`32/7
`
`Restore the first copy of data from the non-
`Volatile memory to the volatile memory
`
`3.377
`
`
`
`
`
`
`
`Erase the first copy of data from
`the non-volatile memory
`
`Copy Second copy of data from
`Volatile memory to non-volatile
`memory in a second mode
`
`
`
`
`
`
`
`
`
`Restore the second Copy of data from the
`non-volatile memory to the Volatile memory
`
`56(7
`
`Netlist Ex 2002-p. 9
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`US 8,301.833 B1
`
`
`
`
`
`
`
`
`
`Netlist Ex 2002-p. 10
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 10 of 12
`
`US 8,301.833 B1
`
`527
`
`5/47
`
`Operate volatile memory at first frequency
`in first mode
`
`Operate non-volatile memory at
`second frequency in second
`mode
`
`Operate Volatile memory at
`third frequency in second
`mode
`
`
`
`
`
`
`
`
`
`Netlist Ex 2002-p. 11
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 11 of 12
`
`US 8,301.833 B1
`
`re-
`E
`CD
`E
`CS)
`CD
`CO
`d
`a.
`Y
`?
`
`CN
`
`CD
`S
`O
`GD
`(/)
`2
`CC
`Y
`?
`
`
`
`Netlist Ex 2002-p. 12
`Samsung v Netlist
`IPR2022-00996
`
`

`

`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 12 of 12
`
`US 8,301.833 B1
`
`/
`
`
`
`
`
`Communicate data Words between Volatile
`memory and host system in first mode
`
`4/2
`
`transfor alaware rom nail maman - “
`Transfer data words from volatile memory
`system to non-volatile memory system
`
`
`
`Store first slice of data word in
`buffer
`
`Store Second slice of data Word in
`buffer
`
`Write entire data WOrd from buffer
`to non-volatile memory
`
`Netlist Ex 2002-p. 13
`Samsung v Netlist
`IPR2022-00996
`
`

`

`1.
`NON-VOLATILE MEMORY MODULE
`
`US 8,301,833 B1
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of U.S. patent applica
`tion Ser. No. 12/131,873, filed Jun. 2, 2008, which claims the
`benefit of U.S. Provisional Application No. 60/941,586, filed
`Jun. 1, 2007. Each of these applications is incorporated in its
`entirety by reference herein.
`
`10
`
`BACKGROUND
`
`15
`
`Certain types of memory modules comprise a plurality of
`dynamic random-access memory (DRAM) devices mounted
`on a printed circuit board (PCB). These memory modules are
`typically mounted in a memory slot or socket of a computer
`system (e.g., a server System or a personal computer) and are
`accessed by the computer system to provide volatile memory o
`to the computer system.
`Volatile memory generally maintains stored information
`only when it is powered. Batteries have been used to provide
`power to Volatile memory during power failures or interrup
`tions. However, batteries may require maintenance, may need 25
`to be replaced, are not environmentally friendly, and the sta
`tus of batteries can be difficult to monitor.
`Non-volatile memory can generally maintain stored infor
`mation while power is not applied to the non-volatile
`memory. In certain circumstances, it can therefore be useful 30
`to backup volatile memory using non-volatile memory.
`
`SUMMARY
`
`In certain embodiments, a memory system coupled to a 35
`computer system is provided which includes a volatile
`memory Subsystem, a non-volatile memory Subsystem, and a
`controller operatively coupled to the non-volatile memory
`Subsystem. The memory system can also include at least one
`circuit configured to selectively operatively decouple the con- 40
`troller from the volatile memory subsystem.
`In some embodiments, a power module for providing a
`plurality of Voltages to a memory system is described. The
`power module includes non-volatile and Volatile memory,
`and the plurality of voltages include at least a first Voltage and 45
`a second Voltage. The power module of certain embodiments
`includes an input providing a third Voltage to the power mod
`ule and a Voltage conversion element configured to provide
`the second Voltage to the memory system. The power module
`also includes a first power element configured to selectively 50
`provide a fourth voltage to the conversion element. The power
`module further includes a second power element configured
`to selectively provide a fifth voltage to the conversion ele
`ment. The power module can be configured to selectively
`provide the first voltage to the memory system either from the 55
`conversion element or from the input.
`The power module can be configured to be operated in at
`least three states in certain embodiments. In a first state, the
`first Voltage is provided to the memory system from the input
`and the fourth voltage is provided to the conversion element 60
`from the first power element. In a second, state the fourth
`voltage is provided to the conversion element from the first
`power element and the first voltage is provided to the memory
`system from the conversion element. In a third state, the fifth
`voltage is provided to the conversion element from the second 65
`power element and the first voltage is provided to the memory
`system from the conversion element.
`
`2
`A method of providing a first Voltage and a second Voltage
`to a memory system including Volatile and non-volatile
`memory Subsystems is provided in certain embodiments. The
`method includes, during a first condition, providing the first
`Voltage to the memory system from an input power Supply
`and providing the second Voltage to the memory system from
`a first power subsystem. The method further includes detect
`ing a second condition and, during the second condition,
`providing the first voltage and the second Voltage to the
`memory system from the first power subsystem. The method
`also includes charging a second power Subsystem and detect
`ing a third condition. During the third condition, the method
`includes providing the first Voltage and the second Voltage to
`the memory system from the second power Subsystem.
`In certain embodiments, a method is provided for control
`ling a memory system operatively coupled to a host system
`and which includes a volatile memory Subsystem and a non
`Volatile memory Subsystem. The method can include operat
`ing the volatile memory Subsystem at a first frequency when
`the memory system is in a first mode of operation in which
`data is communicated between the Volatile memory Sub
`system and the host system. In certain embodiments, the
`method further includes operating the non-volatile memory
`Subsystem at a second frequency when the memory system is
`in a second mode of operation in which data is communicated
`between the volatile memory subsystem and the non-volatile
`memory Subsystem. The method can also include operating
`the volatile memory subsystem at a third frequency when the
`memory system is in the second mode of operation, the third
`frequency less than the first frequency.
`In certain embodiments, a method is provided for control
`ling a memory system operatively coupled to a host system.
`The memory system includes a volatile memory Subsystem
`and a non-volatile memory Subsystem. In certain embodi
`ments, the method includes communicating data words
`between the volatile memory subsystem and the host system
`when the memory system is in a first mode of operation. The
`method can further include transferring data words from the
`Volatile memory Subsystem to the non-volatile memory Sub
`system when the memory system is in a second mode of
`operation. Transferring each data word can include storing a
`first portion of the data word in a buffer, storing a second
`portion of the data word in the buffer, and writing the entire
`data word from the buffer to the non-volatile memory sub
`system.
`A memory system operatively coupled to a host system is
`provided in certain embodiments. The memory system can
`include a volatile memory Subsystem and a non-volatile
`memory Subsystem comprising at least 100 percent more
`storage capacity than does the Volatile memory Subsystem.
`The memory system includes a controller operatively coupled
`to the Volatile memory Subsystem and operatively coupled to
`the non-volatile memory Subsystem, the controller config
`ured to allow data to be communicated between the volatile
`memory Subsystem and the host system when the memory
`system is operating in a first state and to allow data to be
`communicated between the Volatile memory Subsystem and
`the non-volatile memory Subsystem when the memory sys
`tem is operating in a second state.
`A method of controlling a memory system operatively
`coupled to a host system is provided in certain embodiments.
`The memory system includes a volatile memory Subsystem
`and a non-volatile memory Subsystem. The method can
`include communicating data between the Volatile memory
`Subsystem and the host system when the memory system is in
`a first mode of operation. The method of certain embodiments
`further includes storing a first copy of data from the volatile
`
`Netlist Ex 2002-p. 14
`Samsung v Netlist
`IPR2022-00996
`
`

`

`US 8,301,833 B1
`
`10
`
`15
`
`25
`
`30
`
`35
`
`3
`memory Subsystem to the non-volatile memory Subsystem at
`a first time when the memory system is in a second mode of
`operation. The method may further include restoring the first
`copy of data from the non-volatile memory Subsystem to the
`Volatile memory Subsystem and erasing the first copy of data
`from the non-volatile memory Subsystem. In certain embodi
`ments, the method also includes storing a second copy of data
`from the volatile memory subsystem to the non-volatile
`memory Subsystem at a second time when the memory sys
`tem is in the second mode of operation, wherein storing the
`second copy begins before the first copy is completely erased
`from the non-volatile memory Subsystem.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of an example memory system
`compatible with certain embodiments described herein.
`FIG. 2 is a block diagram of an example memory module
`with ECC (error-correcting code) having a volatile memory
`Subsystem with nine Volatile memory elements and a non
`volatile memory subsystem with five non-volatile memory
`elements in accordance with certain embodiments described
`herein.
`FIG. 3 is a block diagram of an example memory module
`having a microcontroller unit and logic element integrated
`into a single device in accordance with certain embodiments
`described herein.
`FIGS. 4A-4C schematically illustrate example embodi
`ments of memory systems having Volatile memory Sub
`systems comprising registered dual in-line memory modules
`in accordance with certain embodiments described herein.
`FIG. 5 schematically illustrates an example power module
`of a memory system in accordance with certain embodiments
`described herein.
`FIG. 6 is a flowchart of an example method of providing a
`first Voltage and a second Voltage to a memory system includ
`ing volatile and non-volatile memory Subsystems.
`FIG. 7 is a flowchart of an example method of controlling
`a memory system operatively coupled to a host system and
`which includes at least 100 percent more storage capacity in
`non-volatile memory than in Volatile memory.
`FIG. 8 schematically illustrates an example clock distribu
`tion topology of a memory system in accordance with certain
`embodiments described herein.
`FIG. 9 is a flowchart of an example method of controlling
`a memory system operatively coupled to a host system, the
`method including operating a volatile memory Subsystemata
`reduced rate in a back-up mode.
`FIG. 10 schematically illustrates an example topology of a
`connection to transfer data slices from two DRAM segments
`of a Volatile memory Subsystem of a memory system to a
`controller of the memory system.
`FIG. 11 is a flowchart of an example method of controlling
`a memory system operatively coupled to a host system, the
`method including backing up and/or restoring a volatile
`memory Subsystem in slices.
`
`4
`power the system in the event of a power failure or reduction,
`the memory system can include a secondary power source
`which does not comprise a battery and may include, for
`example, a capacitor or capacitor array.
`In certain embodiments, the memory system can be con
`figured such that the operation of the volatile memory is not
`adversely affected by the non-volatile memory or by the
`controller when the volatile memory is interacting with the
`host system. For example, one or more isolation devices may
`isolate the non-volatile memory and the controller from the
`volatile memory when the volatile memory is interacting with
`the host system and may allow communication between the
`volatile memory and the non-volatile memory when the data
`of the volatile memory is being restored or backed-up. This
`configuration generally protects the operation of the Volatile
`memory when isolated while providing backup and restore
`capability in the event of a trigger condition, Such as a power
`failure.
`In certain embodiments described herein, the memory sys
`tem includes a power module which provides power to the
`various components of the memory system from different
`Sources based on a state of the memory system in relation to
`a trigger condition (e.g., a power failure). The power module
`may switch the source of the power to the various components
`in order to efficiently provide power in the event of the power
`failure. For example, when no power failure is detected, the
`power module may provide power to certain components,
`Such as the volatile memory, from system power while charg
`ing a secondary power source (e.g., a capacitor array). In the
`event of a power failure or other trigger condition, the power
`module may power the Volatile memory elements using the
`previously charged secondary power source.
`In certain embodiments, the power module transitions rela
`tively smoothly from powering the volatile memory with
`system power to powering it with the secondary power
`Source. For example, the memory system may power volatile
`memory with a third power source from the time the memory
`system detects that power failure is likely to occur until the
`time the memory system detects that the power failure has
`actually occurred.
`In certain embodiments, the volatile memory system can
`be operated at a reduced frequency during backup and/or
`restore operations which can improve the efficiency of the
`system and save power. In some embodiments, during backup
`and/or restore operations, the Volatile memory communicates
`with the non-volatile memory by writing and/or reading data
`words in bit-wise slices instead of by writing entire words at
`once. In certain embodiments, when each slice is being writ
`ten to or read from the volatile memory the unused slice(s) of
`Volatile memory is not active, which can reduce the power
`consumption of the system.
`In yet other embodiments, the non-volatile memory can
`include at least 100 percent more storage capacity than the
`Volatile memory. This configuration can allow the memory
`system to efficiently handle Subsequent trigger conditions.
`FIG. 1 is a block diagram of an example memory system 10
`compatible with certain embodiments described herein. The
`memory system 10 can be coupled to a host computer system
`and can include a volatile memory Subsystem 30, a non
`volatile memory subsystem 40, and a controller 62 opera
`tively coupled to the non-volatile memory subsystem 40. In
`certain embodiments, the memory system 10 includes at least
`one circuit 52 configured to selectively operatively decouple
`the controller 62 from the volatile memory subsystem 30.
`In certain embodiments, the memory system 10 comprises
`a memory module. The memory system 10 may comprise a
`printed-circuit board (PCB) 20. In certain embodiments, the
`
`40
`
`45
`
`50
`
`55
`
`DETAILED DESCRIPTION
`
`Certain embodiments described herein include a memory
`system which can communicate with a host system such as a
`disk controller of a computer system. The memory system
`can include Volatile and non-volatile memory, and a control
`ler. The controller backs up the volatile memory using the
`non-volatile memory in the event of a trigger condition. Trig
`ger conditions can include, for example, a power failure,
`power reduction, request by the host system, etc. In order to
`
`60
`
`65
`
`Netlist Ex 2002-p. 15
`Samsung v Netlist
`IPR2022-00996
`
`

`

`US 8,301,833 B1
`
`10
`
`15
`
`5
`memory system 10 has a memory capacity of 512-MB, 1-GB,
`2-GB, 4-GB, or 8-GE. Other volatile memory capacities are
`also compatible with certain embodiments described herein.
`In certain embodiments, the memory system 10 has a non
`volatile memory capacity of 512-MB, 1-GB, 2-GB, 4-GB,
`8-GE, 16-GB, or 32-GB. Other non-volatile memory capaci
`ties are also compatible with certain embodiments described
`herein. In addition, memory systems 10 having widths of 4
`bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits,
`256 bits, as well as other widths (in bytes or in bits), are
`compatible with embodiments described herein. In certain
`embodiments, the PCB 20 has an industry-standard form
`factor. For example, the PCB 20 can have a low profile (LP)
`form factor with a height of 30 millimeters and a width of
`133.35 millimeters. In certain other embodiments, the PCB
`20 has a very high profile (VHP) form factor with a height of
`50 millimeters or more. In certain other embodiments, the
`PCB 20 has a very low profile (VLP) form factor with a height
`of 18.3 millimeters. Other form factors including, but not
`limited
`to,
`small-outline (SO-DIMM), unbuffered
`(UDIMM), registered (RDIMM), fully-buffered (FBDIMM),
`mini-DIMM, mini-RDIMM, VLP mini-DIMM, micro
`DIMM, and SRAM DIMM are also compatible with certain
`embodiments described herein. For example, in other
`embodiments, certain non-DIMM form factors are possible
`Such as, for example, single in-line memory module (SIMM),
`multi-media card (MMC), and small computer system inter
`face (SCSI).
`In certain preferred embodiments, the memory system 10
`is in electrical communication with the host system. In other
`embodiments, the memory system 10 may communicate with
`a host system using some other type of communication, such
`as, for example, optical communication. Examples of host
`systems include, but are not limited to, blade servers, 1U
`servers, personal computers (PCs), and other applications in
`which space is constrained or limited. The memory system 10
`can be in communication with a disk controller of a computer
`system, for example. The PCB 20 can comprise an interface
`22 that is configured to be in electrical communication with
`the host system (not shown). For example, the interface 22
`can comprise a plurality of edge connections which fit into a
`corresponding slot connector of the host system. The inter
`face 22 of certain embodiments provides a conduit for power
`Voltage as well as data, address, and control signals between
`the memory system 10 and the host system. For example, the
`interface 22 can comprise a standard 240-pin DDR2 edge
`COnnectOr.
`The volatile memory subsystem 30 comprises a plurality of
`volatile memory elements 32 and the non-volatile memory
`Subsystem 40 comprises a plurality of non-volatile memory
`elements 42. Certain embodiments described herein advan
`tageously provide non-volatile storage via the non-volatile
`memory Subsystem 40 in addition to high-performance (e.g.,
`high speed) storage via the volatile memory subsystem30. In
`certain embodiments, the first plurality of volatile memory
`elements 32 comprises two or more dynamic random-access
`memory (DRAM) elements. Types of DRAM elements 32
`compatible with certain embodiments described herein
`include, but are not limited to, DDR, DDR2, DDR3, and
`synchronous DRAM (SDRAM). For example, in the block
`diagram of FIG. 1, the first memory bank 30 comprises eight
`64Mx8 DDR2 SDRAM elements 32. The volatile memory
`elements 32 may comprise other types of memory elements
`Such as static random-access memory (SRAM). In addition,
`volatile memory elements 32 having bit widths of 4, 8, 16, 32.
`as well as other bit widths, are compatible with certain
`embodiments described herein. Volatile memory elements 32
`
`6
`compatible with certain embodiments described herein have
`packaging which include, but are not limited to, thin Small
`outline package (TSOP), ball-grid-array (BGA), fine-pitch
`BGA (FBGA), micro-BGA (uBGA), mini-BGA (mEGA),
`and chip-scale packaging (CSP).
`In certain embodiments, the second plurality of non-vola
`tile memory elements 42 comprises one or more flash
`memory elements. Types of flash memory elements 42 com
`patible with certain embodiments described herein include,
`but are not limited to, NOR flash, NAND flash, ONE-NAND
`flash, and multi-level cell (MLC). For example, in the block
`diagram of FIG. 1, the second memory bank 40 comprises
`512MB offlash memory organized as four 128Mbx8 NAND
`flash memory elements 42. In addition, non-volatile memory
`elements 42 having bit widths of 4, 8, 16, 32, as well as other
`bit widths, are compatible with certain embodiments
`described herein. Non-volatile memory elements 42 compat
`ible with certain embodiments described herein have pack
`aging which include, but are not limited to, thin Small-outline
`package (TSOP), ball-grid-array (BGA), fine-pitch BGA
`(FBGA), micro-BGA (LBGA), mini-BGA (mEGA), and
`chip-scale packaging (CSP).
`FIG. 2 is a block diagram of an example memory module
`10 with ECC (error-correcting code) having a volatile
`memory subsystem 30 with nine volatile memory elements
`32 and a non-volatile memory subsystem 40 with five non
`Volatile memory elements 42 in accordance with certain
`embodiments described herein. The additional memory ele
`ment 32 of the first memory bank 30 and the additional
`memory element 42 of the second memory bank 40 provide
`the ECC capability. In certain other embodiments, the volatile
`memory subsystem 30 comprises other numbers of volatile
`memory elements 32 (e.g., 2, 3, 4, 5, 6, 7, more than 9). In
`certain embodiments, the non-volatile memory subsystem 40
`comprises other numbers of non-volatile memory elements
`42 (e.g. 2, 3, more than 5).
`Referring to FIG. 1, in certain embodiments, the logic
`element 70 comprises a field-programmable gate array
`(FPGA). In certain embodiments, the logic element 70 com
`prises an FPGA available from Lattice Semiconductor Cor
`poration which includes an internal flash. In certain other
`embodiments, the logic element 70 comprises an FPGA
`available from another vendor. The internal flash can improve
`the speed of the memory system 10 and save physical space.
`Other types of logic elements 70 compatible with certain
`embodiments described herein include, but are not limited to,
`a programmable-logic device (PLD), an application-specific
`integrated circuit (ASIC), a custom-designed semiconductor
`device, a complex programmable logic device (CPLD). In
`certain embodiments, the logic element 70 is a custom device.
`In certain embodiments, the logic element 70 comprises vari
`ous discrete electrical elements, while in certain other
`embodiments, the logic element 70 comprises one or more
`integrated circuits. FIG. 3 is a block diagram of an example
`memory module 10 having a microcontroller unit 60 and
`logic element 70 integrated into a single controller 62 in
`accordance with certain embodiments described herein. In
`certain embodiments, the controller 62 includes one or more
`other components. For example, in one embodiment, an
`FPGA without an internal flash is used and the controller 62
`includes a separate flash memory component which stores
`configuration information to program the FPGA.
`In certain embodiments, the at least one circuit 52 com
`prises one or more Switches coupled to the Volatile memory
`subsystem 30, to the controller 62, and to the host computer
`(e.g., via the interface 22, as Schematically illustrated by
`FIGS. 1-3). The one or more switches are responsive to sig
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Netlist Ex 2002-p. 16
`Samsung v Netlist
`IPR2022-00996
`
`

`

`7
`nals (e.g., from the controller 62) to selectively operatively
`decouple the controller 62 from the volatile memory sub
`system 30 and to selectively operatively couple the controller
`62 to the volatile memory subsystem 30. In addition, in cer
`tain embodiments, the at least one circuit 52 selectively 5
`operatively couples and decouples the Volatile memory Sub
`system 30 and the host system.
`In certain embodiments, the volatile memory subsystem 30
`can comprise a registered DIMM Subsystem comprising one
`or more registers 160 and a plurality of DRAM elements 180, 10
`as schematically illustrated by FIG. 4A. In certain such
`embodiments, the at least one circuit 52 can comprise one or
`more switches 172 coupled to the controller 62 (e.g., logic
`element 70) and to the volatile memory subsystem 30 which
`can be actuated to couple and decouple the controller 62 to 15
`and from the volatile memory subsystem 30, respectively.
`The memory system 10 further comprises one or more
`switches 170 coupled to the one or more registers 160 and to
`the plurality of DRAM elements 180 as schematically illus
`trated by FIG. 4A. The one or more switches 170 can be 20
`selectively switched, thereby selectively operatively coupling
`the volatile memory subsystem 30 to the host system 150. In
`certain other embodiments, as schematically illustrated by
`FIG. 4B, the one or more switches 174 are also coupled to the
`one or more registers 160 and to a power source 162 for the 25
`one or more registers 160. The one or more switches 174 can
`be selectively switched to turn power on or off to the one or
`more registers 160, thereby selectively operatively coupling
`the volatile memory subsystem 30 to the host system 150. As
`schematically illustrated by FIG. 4C, in certain embodiments 30
`the at least one circuit 52 comprises a dynamic on-die termi
`nation (ODT) 176 circuit of the logic element 70. For
`example, the logic element 70 can comprise a dynamic ODT
`circuit 176 which selectively operatively couples and
`decouples the logic element 70 to and from the volatile 35
`memory Subsystem 30, respectively. In addition, and similar
`to the example embodiment of FIG. 4A described above, the
`one or more switches 170 can be selectively switched, thereby
`selectively operatively coupling the Volatile memory Sub
`40
`system 30 to the host system 150.
`Certain embodiments described herein utilize the non
`volatile memory subsystem 40 as a flash “mirror” to provide
`backup of the volatile memory subsystem 30 in the event of
`certain system conditions. For example, the non-volatile
`memory subsystem 40 may backup the volatile memory sub- 45
`system 30 in the event of a trigger condition, such as, for
`example, a power failure or power reduction or a request from
`the host system. In one embodiment, the non-volatile
`memory subsystem 40 holds intermediate data results in a
`noisy System environment when the host computer system is 50
`engaged in a long computation. In certain embodiments, a
`backup may be performed on a regular basis. For example, in
`one embodiment, the backup may occur every millisecond in
`response to a trigger condition. In certain embodiments, the
`trigger condition occurs when the memory system 10 detects 55
`that the system Voltage is below a certain threshold Voltage.
`For example, in one embodiment, the threshold voltage is 10
`percent below a specified operating Voltage. In certain
`embodiments, a trigger condition occurs when the Voltage
`goes above a certain threshold value. Such as, for example, 10 60
`percent above a specified operating Voltage. In some embodi
`ments, a trigger condition occurs when the Voltage goes
`below a threshold or above another threshold. In various
`embodiments, a backup and/orrestore operation may occur in
`reboot and/or non-reboot trigger conditions.
`As schematically illustrated by FIGS. 1 and 2, in certain
`embodiments, the controller 62 may comprise a microcon
`
`65
`
`US 8,301,833 B1
`
`8
`troller unit (MCU) 60 and a logic element 70. In certain
`embodiments, the MCU 60 provides memory management
`for the non-volatile memory subsystem 40 and controls data
`transfer between the volatile memory subsystem 30 and the
`non-volatile memory subsystem 40. The MCU 60 of certain
`embod