UNITED STATES PATENT AND TRADEMARK OFFICE
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`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`___________________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`___________________
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`DECLARATION OF DR. SUNIL P. KHATRI
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`___________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`___________________
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`DECLARATION OF DR. SUNIL P. KHATRI
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`DECLARATION OF SUNIL P. KHATRI, PH. D
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`I, Sunil P. Khatri, do hereby declare as follows:
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`INTRODUCTION
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`I have been retained on behalf of Netlist, Inc. (“Patent Owner”) as an
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`expert to evaluate certain technical aspects of U.S. Patent No. 11,016,918 (“the ’918
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`patent”), and to provide certain options relating thereto. I am personally
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`knowledgeable about the matters stated herein and am competent to make this
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`declaration.
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`I understand
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`that Patent Owner will submit
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`this declaration
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`(“Declaration”) in connection with IPR2022-00996 (“Proceeding”), which I have
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`been informed is an inter partes review (IPR) proceeding before the Patent Trial and
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`Appeal Board challenging the patentability of claims 1-30 of the ’918 patent.
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`I receive compensation at my normal consulting rate for my time
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`working on this matter, plus expenses. I have no financial interest in Patent Owner
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`or in the patents involved in this litigation, and my compensation is not dependent
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`on the outcome of this litigation. The opinions I present are due to my own judgment.
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`All “EX10XX” cites herein are to exhibits I understand are being
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`submitted by the Patent Owner in this Proceeding. All “Appendix _” cites followed
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`by a letter are to appendices to this Declaration. All citations to “Section XX” are
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`internal citations to the sections of this Declaration. All citations to “Paragraph XX”
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`are internal citations to the paragraphs of this Declaration.
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`BACKGROUND AND QUALIFICATIONS
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`I have over thirty-five years of experience with electronics, electrical
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`engineering, and computer engineering. A copy of my latest curriculum vitae (CV),
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`which I understand is being submitted with this Declaration as Appendix A, provides
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`further details regarding my background and qualifications. During my career, I have
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`acquired extensive knowledge and experience with VLSI circuits, computer
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`architecture, testing, computer-aided design (CAD) algorithms and algorithm
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`acceleration, logic synthesis, semiconductor memory, redundancy, synchronous and
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`asynchronous circuits, and related software and hardware topics. Most relevant to
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`the ’054 patent, my technical expertise includes extensive work with semiconductor
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`memory devices such as dynamic random access memory (DRAM), static random
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`access memory (SRAM), and flash memory. My work with semiconductor memory
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`devices has included work on 3D integration and novel ring-based DRAM memory
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`DIMM architectures, power and speed tradeoffs using selective body bias,
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`architectures and circuit approaches for processing-in-memory within DIMM-based
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`DRAM architectures, stability modeling of RAM memory, power reduction in
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`memory designs, and clocking and source-synchronous design. My graduate as well
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`as undergraduate coursework covers memory circuit design extensively, including
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`DRAM memory circuits as well as DIMMs and their system-level design and latency
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`properties. Additionally, I have served as an expert witness in several cases
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`involving semiconductor memory, including DRAM and flash memory. My MS
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`thesis involved designing a memory interface for a multi-threaded Reduced
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`Instruction Set Computing (RISC) microprocessor.
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`
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`The following describes some of my relevant experience. I earned my
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`Bachelor of Science in Electrical Engineering in 1987 from the Indian Institute of
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`Technology, Kanpur, India. After graduating with my B.S. degree, I was a candidate
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`for a Master of Science degree in Electrical and Computer Engineering at the
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`University of Texas from 1987–89. At the University of Texas, I held the
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`Microelectronics and Computer Development (MCD) Fellowship from 1987–89. I
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`also conducted my M.S. research and wrote my thesis on the design of the METRIC
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`memory interface and memory system. METRIC was one of the first super-scalar
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`processors that was developed in the world. I earned an M.S. degree in 1989 from
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`the University of Texas, Austin.
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`
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`After leaving the University of Texas, I worked at Motorola Inc. from
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`1989–93 as a design engineer for the MC88110 RISC microprocessor team,
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`followed by the PowerPC 603 RISC microprocessor design team. My duties
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`included the design of digital and analog circuitry, test logic circuits, layout, JTAG
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`boundary scan design, input/output driver design, and clock phase-locked loop
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`(PLL) logic and clock distribution. During my time at Motorola, I was independently
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`responsible for the design of the factory test controller of the MC88110
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`microprocessor. I performed all attendant tasks in a “vertical” VLSI design
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`methodology, which included high-level modeling, circuit and layout design and
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`verification, as well as global and detailed routing. I also helped in the design of the
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`Translation Lookaside Buffer (TLB) unit, which included a static random-access
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`memory (SRAM) block.
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`
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`In 1999, I earned a Doctor of Philosophy degree in Electrical
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`Engineering and Computer Sciences from the University of California, Berkeley.
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`While at Berkeley, I held the California Microelectronics (MICRO) Fellowship in
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`1993.
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`
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`I joined the faculty at the University of Colorado, Boulder, in 2000 as
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`an Assistant Professor of Electrical and Computer Engineering. At the University of
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`Colorado my research focused on VLSI logic design automation, VLSI layout design
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`automation, and VLSI design methodologies to address Deep Submicron (DSM)
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`issues such as crosstalk and power.
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`
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`I joined the faculty at Texas A&M University in 2004 as an Assistant
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`Professor in Electrical and Computer Engineering. In 2010, I was promoted to
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`Associate Professor in Electrical and Computer Engineering. In 2015, I was
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`promoted to full Professor in Electrical and Computer Engineering. My research
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`focuses on three primary areas: the first is computer systems, including computer
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`architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs
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`and custom ICs. The second is logic and its applications, while the third area consists
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`of interdisciplinary extensions of the first two. One of my newer focus areas is
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`researching tamper-proof memory techniques including flash and DRAM-based
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`tamper-proof memories, as well as multi-row read architectures for computer
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`memory systems, including DRAM memory systems.
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` At Texas A&M I teach classes that cover memories extensively,
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`featuring thorough discussion of sense amplifiers, row and column decoders, and
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`different types of memory circuits including DRAM and flash. For example, in
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`Electrical and Computer Engineering (ECEN) 752 “Advances in VLSI Circuit
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`Design,” a graduate level course, I cover all aspects of VLSI design, including
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`memory design. In ECEN 449/749 “Microprocessor System Design,” and in ECEN
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`752, I cover memories, including DRAM and flash memories, the design of DRAM
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`and flash memory cells, the organization of DRAM memories into multiple banks,
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`and the division of data across multiple banks of memory, as well as other design
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`techniques that can be used to optimize and manage such memories at the circuit and
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`system level. This course is attended by both undergraduate (ECEN 449) and
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`graduate (ECEN 749) students. In ECEN 454 “Digital Circuit Design,” a senior
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`undergraduate course, I cover circuit design techniques for memory in detail. The
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`Ph.D. thesis of one of my recent doctoral students dealt with the use of flash
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`transistors to design logic circuits, and two current Ph.D. students are expanding on
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`this work. The research of a recent M.S. student entailed a new ring-based source
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`synchronous architecture for 3D DRAM-based DIMM technologies, which has been
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`published at a conference and in a journal and is being submitted for dissemination
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`as a research monograph. Currently, one of the Ph.D. students that I advise is
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`conducting research in secure tamper-proof memory, including DRAM. In the past,
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`I have conducted research into new topologies for efficient memory redundancy as
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`part of a course project for my graduate course.
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` Since 2000, I have earned 24 research contracts from funders including
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`Intel, the National Science Foundation, the National Security Agency, Altera
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`Corporation,
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`the National Center
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`for Atmospheric Research, National
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`Semiconductor Corporation, and several private sources. The total amount for these
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`research grants is $17.53 million, of which my portion is $2.85 million.
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`
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`I have a total of over 275 peer-reviewed publications. Among these
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`papers, five received a best paper award, while seven others received best paper
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`nominations (including one journal best paper nomination). An additional six journal
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`papers and six conference papers are currently undergoing peer review. I have co-
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`authored nine research monographs, one edited research monograph, and three book
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`chapters. Additionally, I have six awarded U.S. Patents (one of which was filed
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`during my tenure at Texas A&M), two filed provisional U.S. Patents, and another
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`U.S. Patent which is currently under review and was also submitted during my tenure
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`at Texas A&M. I have co-authored one invited journal paper and 13 invited
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`conference or workshop papers (including one from Design Automation Conference
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`(DAC) and one from Allerton). Moreover, I was invited to serve as a panelist at a
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`conference seven times and have presented two conference tutorials. I received the
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`“Outstanding Professor Award” in the ECE Department at Texas A&M University
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`in 2007 and also in 2020. My H-index is 33 (per Google Scholar).
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` Since 2003, I have published numerous research monographs, journal
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`papers, and conference papers on memory systems, as detailed in my CV. A few
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`papers on relevant subject areas authored or co-authored by me include:
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`•
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`"CIDAN-XE: Computing in DRAM with Artificial Neurons", Singh,
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`Wagle, Khatri, Vrudhula. Frontiers in Electronics, section Integrated
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`Circuits and VLSI. Vol. 3, Feb 2022;
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`•
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`"A Flash-based Current-mode IC to Realize Quantized Neural
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`Networks", Scott, Lee, Khatri, Vrudhula. Design Automation and Test
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`in Europe (DATE) Conference, Mar 2022, virtual conference;
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`•
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`"CIDAN: Computing in DRAM with Artificial Neurons", Singh,
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`Wagle, Vrudhula, Khatri. 39th IEEE International Conference on
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`Computer Design (ICCD) 2021, pp. 349-356, Oct 2021, virtual
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`conference;
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`•
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`Fast, Ring-based Design of 3D Stacked DRAM, IEEE Transactions on
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`Very Large Scale Integrated Circuits (VLSI) Systems (TVLSI), Vol 27
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`number 8, Aug 2019. pp. 1731-1741;
`
`•
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`•
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`Fast, Ring-Based Design of 3D Stacked DRAM, IEEE International
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`Conference on Computer Design 2017: pp. 665-672;
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`Selective Forward Body Bias for High Speed and Low Power SRAMs,
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`Journal of Low Power Electronics, Vol. 5, No. 2, Aug. 2009, pp. 185-
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`95;
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`•
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`Low Power and High Performance SRAM Design using Bank-based
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`Selective Forward Body Bias, IEEE/ACM Great Lakes Symposium on
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`VLSI, May 10-12, 2009, Boston, MA, pp. 441-44;
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`•
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`Modeling Dynamic Stability of SRAMs in the Presence of Single Event
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`Upsets (SEUs), IEEE International Symposium on Circuits and
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`Systems, May 18-21, 2008, Seattle, WA, pp. 1788-91;
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`•
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`“Design of a Flash-based Circuit for Multi-valued Logic”, Proceedings
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`of the Great Lakes Symposium on VLSI (GLSVLSI) 2017, pp. 41-46,
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`May 10-12, 2017. Banff, Canada.
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`•
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`"SAT-Based Optimization
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`for Flash-Based Digital Designs",
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`IEEE/ACM Design Automation Conference (DAC), Jun 18-22 2017,
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`Austin, TX.
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`•
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`"A Flash-based Digital Circuit Design Flow", IEEE/ACM International
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`Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX,
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`Nov 2016.
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`•
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`"Implementing low power digital circuits using flash devices", 2016
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`IEEE 34th International Conference on Computer Design (ICCD), pp.
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`109-116, Oct 3-5, 2016, Phoenix, AZ.
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`•
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`•
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`•
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`"Exploring Flash Devices to Implement Digital Circuits", IEEE/ACM
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`Design Automation Conference (DAC), June 2016, Austin, TX.
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`FTCAM: An Area-efficient Flash-based Ternary CAM Design, IEEE
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`Transactions on Computers, Vol. 65, No. 8, Aug. 2016, pp. 2652-58;
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`An Area-efficient Ternary CAM Design Using Floating Gate
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`Transistors, IEEE International Conference on Computer Design, Oct.
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`19-22, 2014, Seoul, S. Kor., pp. 55-60; and
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`•
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`A Fast Ternary CAM Design for IP Networking Applications,
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`International Conference on Computer Communications and Networks,
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`October 22, 2003, Dallas, TX, pp. 434-39 (candidate for best paper
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`award).
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`In addition to my work on the papers listed above, I have also served as an editor
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`for IEEE Transactions on Computers, ACM Transactions on Design Automation of
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`Electronic Systems, and MDPI Journal of Electronics.
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`
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`I have served as EDA Track Co-Chair for ICECS 2014, Panel Chair for
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`TexasWISE 2014, Track Co-Chair (VLSI Systems, Applications and Computer
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`Aided Design track) for ICECS 2013, Poster Session Chair for TexasWISE 2013,
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`Advisory Committee for HotPI 2013, Panel Session Chair for SLiP 2013, Track
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`Chair (Logic track) for ICCAD 2009-10, 2015-17, Track Chair (logic track) for DAC
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`2016-17, General Chair for IWLS 2009, Technical Program Chair for IWLS 2008,
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`Track Co-Chair, Computer Aided Network DEsign (CANDE) Track, for ISCAS
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`2008-10, Track Co-chair for the DSP track for ISCAS 2022, Track Co-Chair, Test
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`and Methodologies Track, for ICCD 2007, Panel Chair for ITSW 2009, Publicity
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`Co-Chair for GLS-VLSI 2009, and as a member of the TPC for several conferences.
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`
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`I am generally familiar with the analysis of patents. I am a named
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`inventor on the following U.S. Patents:
`
`•
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`Data Processing System Having Serial Self Address Decoding and
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`Method of Operation, United States Patent No. 5,347,523, issued
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`September 13, 1994;
`
`•
`
`•
`
`•
`
`•
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`•
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`Circuit Identifier for Use with Focused Ion Beam Equipment, United
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`States Patent No. 5,408,131, issued April 18, 1995;
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`Driver Circuit with Self-Adjusting Impedance Matching, United States
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`Patent No. 5,448,182, issued September 5, 1995;
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`Circuit Identifier for Use with Focused Ion Beam Equipment, United
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`States Patent No. 6,156,579, issued December 5, 2000;
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`Datapath Design Methodology and Routing Apparatus, United States
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`Patent No. 6,598,215, issued July 22, 2003;
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`Low Power Reconfigurable Circuits with Delay Compensation, United
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`States Patent No. 7,880,505, issued February 1, 2011.
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` MATERIALS CONSIDERED
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`
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`I have considered information from various sources in forming my
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`opinions. Besides drawing from my decades of experience in the computer industry,
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`I have reviewed the Petition and supporting declaration, the ’918 patent and its file
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`history, the prior art discussed below, and the other documents and references cited
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`herein.
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` LEGAL STANDARDS
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`
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`I have relied on instructions from counsel as to the applicable legal
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`standards to use in arriving at my opinions in this Declaration. I am relying only on
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`instructions from Netlist’s attorneys for these legal standards.
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`I understand that a patent claim is unpatentable and invalid if the subject
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`matter of the claim as a whole would have been obvious to a person of ordinary skill
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`in the art of the claimed subject matter, as of the time of the invention at issue.
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`I have been informed and understand that a patent claim can be
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`considered to have been obvious to a person of ordinary skill in the art at the time of
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`the alleged invention. This means that, even if all the requirements of a claim are not
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`found in a single prior art reference, the claim is not patentable if the differences
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`between the subject matter in the prior art and the subject matter in the claim, would
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`have been obvious to a person of ordinary skill in the art at the time of the alleged
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`invention.
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`I understand that the following factors must be evaluated to determine
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`whether the claimed subject matter is obvious: (1) the scope and content of the prior
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`art; (2) the difference or differences, if any, between each claim of the patent and the
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`prior art; and (3) the level of ordinary skill in the art at the time the patent was filed.
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`I have been informed and understand that the teachings of two or more
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`references may be combined if such a combination would have been obvious to one
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`having ordinary skill in the art. In determining whether a combination based on
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`multiple references would have been obvious, it is appropriate to consider, among
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`other factors: (1) whether the teachings of the prior art references disclose known
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`concepts combined in familiar ways, and when combined, would yield predictable
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`results; (2) whether a person of ordinary skill in the art could implement such a
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`combination, and would see the benefit of doing so; (3) whether the claimed
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`elements represent one of a limited number of known design choices, and would
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`have a reasonable expectation of success by those skilled in the art; (4) whether a
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`person of ordinary skill would have recognized a reason to combine known elements
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`in the manner described in the claim; (5) whether there is some teaching or
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`suggestion in the prior art to make the modification or combination of elements
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`claimed in the patent; and (6) whether the claimed invention applies a known
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`technique that had been used to improve a similar device or method in a similar way.
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`I have been informed and understand that one of ordinary skill in the
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`art has ordinary creativity, and is not an automaton.
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` I have been informed and understand that in considering obviousness,
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`it is important not to determine obviousness using the benefit of hindsight derived
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`from the patent being considered.
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` THE ’918 PATENT
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` The ’918 patent generally relates to memory modules. In one preferred
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`embodiment, the memory system 1010 comprises a PCB 1020 having DRAM
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`(volatile) memory subsystem 1030 and NAND (nonvolatile) memory subsystem
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`1040, both of which may be operatively coupled to a controller unit 1062. See, e.g.,
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`EX1001, Fig. 12 (reproduced below); see also id., 21:14-23.
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` As shown in the embodiment of FIG. 12, the controller 1062 includes
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`a microcontroller unit (MCU) 1060 and a logic element (comprising a field-
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`programmable gate array (FPGA)) 1070. See id., 23:1-22, 24:35-37. However, in
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`other embodiments the FPGA 1070 may be integrated with the microcontroller 1060.
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`See id., 29:43-44, 29:49-50, 32:50-51, 32:56-57, Fig. 14. The ’054 patent explains
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`that the microcontroller 1060 provides memory management and controls data
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`transfer between the non-volatile memory 1040 and volatile memory 1030. See id.,
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`24:38-41. The FPGA logic element 1070 provides signal level translation and
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`address translation between the volatile memory and non-volatile memory. “The
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`logic element 1070 can provide signal level translation between the volatile memory
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`elements 1032 (e.g., 1.8V SSTL-2 for DDR2 SDRAM elements) and the non-
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`volatile memory elements 1042 (e.g., 3V TTL for NAND flash memory elements),”
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`and also “address/address translation between the volatile memory subsystem 1030
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`and the non-volatile memory subsystem 1040.” Id., 24:48-56.
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` The ’054 patent further discloses that a switch 1052 can selectively
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`couple or decouple the volatile memory subsystem from the controller in response
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`to control signals from the controller. See id., 21:20-23, 23:28-37, 23:44-50, 24:60-
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`25:3. The switch 1052 may also “selectively operatively couple[] and decouple[] the
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`volatile memory subsystem 1030 and the host system.” Id., 23:37-40. In response to
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`a power interruption (e.g., a second state), switch 1052 may operatively couple the
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`volatile memory with the controller and the non-volatile memory so that data in the
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`volatile memory may be transferred to the non-volatile memory. See id., 24:60-25:7.
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`When the system is operating normally (e.g., a first state), switch 1052 operatively
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`decouples the volatile memory from the controller and the non-volatile memory. See
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`id.
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` The ’054 patent further discloses that the PCB includes a DIMM
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`interface 1022, which comprises edge connections via which it provides “power
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`voltage as well as data, address and control signals between the memory system 1010
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`and [a] host system.” Id., 22:1-6. The power from the host system powers the
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`memory module in the first state. See id., 25:54-58 (“Power may be supplied to the
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`volatile memory subsystem 1030 from a first power supply (e.g., a system power
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`supply) when the memory system 1010 is in the first state and from a second power
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`supply 1080 when the memory system 1010 is in the second state.”).
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` The ’054 patent also discloses a voltage monitor 1050 on the PCB that
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`“monitors the voltage supplied by the host system via the [DIMM] interface 1022.”
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`Id., 25:8-10, Fig. 12. Upon detecting an abnormal condition, “the voltage monitor
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`circuit 1050 may transmit a signal to the controller 1062 indicative of the detected
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`condition.” Id., 25:11-14. The controller 1062 may in turn transmit a signal to switch
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`1052 for it to operatively couple the volatile memory and the non-volatile memory,
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`thereby effecting a transition from the first state to the second state. See id., 25:15-
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`20. In certain embodiments, the voltage monitor circuit 1050 may be part of the
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`controller 1062. See id., 25:27-31.
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` The ’918 patent discloses that, in preferred embodiments, “[p]ower
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`may be supplied to the volatile memory subsystem 1030 from a first power supply
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`(e.g., a system power supply) when the memory system 1010 is in the first state ….”
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`Id., 25:54-56. In the second state, power is supplied from a “second power supply
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`1080.” Id., 25:56-58, Fig. 12. The second power supply includes a capacitor bank
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`(e.g., capacitor bank 1086), as well as step-up and step-down transformers (voltage
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`regulators). See id., 26:9-13, FIG. 12.
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` The second power supply 1080 may be selectively coupled or
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`decoupled to the controller and the memory via a switch 1090. Specifically, the ’054
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`patent teaches that switch 1090 “switches power provided to the controller 1062, the
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`volatile memory subsystem 1030, and the non-volatile memory subsystem 1040,
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`between the power from the second power supply 1080 and the power from the first
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`power supply (e.g., system power) received via the interface 1022. For example, the
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`switch 1090 may switch from the first power supply to the second power supply
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`1080 when the voltage monitor 1050 detects a low voltage condition. The switch
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`1090 of certain embodiments advantageously ensures that the volatile memory
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`elements 1032 and non-volatile memory elements 1042 are powered long enough
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`for the data to be transferred from the volatile memory elements 1032 and stored in
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`the non-volatile memory elements 1042.” See id., 26:43-59.
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` The memory subsystem may also include a third state in which power
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`is supplied to the volatile memory subsystem 1030 from a third power supply. See
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`id., 25:62-26:3.
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` With reference to Figure 16, reproduced and annotated below, the ’054
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`patent also teaches a power module comprising three power supplies:
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`(1) power from system (color orange to match Samsung’s color for DIMM
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`interface) for a first state;
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`(2) “second power element” 1140 (colored blue to match Samsung’s color
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`scheme for power supply 1080) for a third state (e.g., when there is a power
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`interruption); and
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`(3) “first power element” 1130 (colored purple) for a second state (e.g., when
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`detecting a power failure is likely to occur).1
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`See id., 28:3-25, 28:39-47, 28:53-58.
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`1 In describing FIGs. 16-17, the ’918 patent refers to the condition in which a
`trigger event is likely to occur as the “second” condition/state and the condition in
`which the trigger event has occurred as the “third” condition/state. See id., 30:16-
`18, 30:39-45, 28:39-47.
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` The ’918 patent further disclosed a conversion element 1120 (colored
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`darker blue on the right) which further includes several sub-blocks 1122, 1124 and
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`1126, each of which receives power from a power source and outputs one or more
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`
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`regulated voltages 1102-1107. See id., 29:18-54, Fig. 16.
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` SKILL LEVEL OF A POSITA
`
` The Petition states that a person having ordinary skill in the art
`
`(“POSITA”) in the field of the ’918 patent in 2008 would have been someone with
`
`an advanced degree in electrical or computer engineering, or a related field, and two
`
`years working or studying in the field of design or development of memory systems,
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`or a bachelor’s degree in such engineering disciplines and at least three years of work
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`experience in the field. See Petition, 8-9.
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` For purposes of the opinions I set forth herein, and to simplify the
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`issues, I have adopted that understanding as to the level of skill in the relevant field
`
`at the time of the invention, noting that none of the opinions I express herein would
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`change if a somewhat higher or somewhat lower level of skill were adopted.
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`However, I reserve the right to separately analyze the appropriate level of skill at the
`
`time of the invention, and to propose a different ordinary level of skill in the art
`
`based on that analysis.
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` THE PRIOR ART
`
` The Petition challenges the claims of the ’918 patent based primarily
`
`on U.S. Patent Publication No. 2006/0174140 (“Harris”), certain JEDEC published
`
`standards for Fully Buffered DIMM (FBDIMM) memory modules (EX1027 and
`
`EX1028), U.S. Patent No. 7,724,604 (“Amidi”), U.S. Patent Publication No.
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`2006/0080515 (“Spiers”).2 Below I provide a brief overview of those references.
`
`
`2 The Petition also cites to U.S. Patent No. 6,856,556 (“Hajeck”) for allegedly
`disclosing a limitation found only in dependent claim 6. See Petition, 75-76, 128.
`However, I have not been asked to express any separate opinions with respect to
`Hajeck.
`
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`A. Harris (EX1023)
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` Harris discloses a “memory assembly module including an on-board
`
`voltage regulator for converting an externally supplied voltage into appropriate
`
`voltage levels for powering memory devices of the memory assembly module.”
`
`EX1023, Abstract, FIG. 1A.
`
`
`
` Harris describes that conventional memory modules, such as industry
`
`standard Dual In-line Memory Modules (DIMM), “are provided with power supply
`
`rails (on a relatively large number of pins) that are powered from system board or
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`main board voltage sources, and are specific to the memory technology.” Id., [0002].
`
`In contrast, Harris aims to “provide[] a technology-independent voltage distribution
`
`scheme for memory devices wherein system board power supply and associated
`
`voltage plane(s) are eliminated.” Id., [0019]. Using a fully-buffered DIMM as an
`
`example, Harris achieves its goal by “replacing the[] power supply interface pins
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`with … +12V pins (from an external power source), with local conversion to Vdd
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`(to DRAM) and Vcc (to buffer/logic) being added.” Id., [0012].
`
` As such, Harris’s memory module does not obtain power from the host
`
`via edge connections of a slot connector corresponding to power supply interface
`
`pins. Instead, Harris’s memory module derives its power from an external power
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`source that is subsequently converted to the appropriate voltage levels depending on
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`the particular design. See id., [0012]; [0016] (“voltage is supplied to a memory board
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`assembly from an external source, e.g., an unregulated source generating fairly high
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`voltages (illustratively, at +12V) with a wide tolerance. The voltage distribution
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`method then involves locally converting the supply voltage using an on-board VRM
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`to generate appropriate levels of voltage for powering on-board memory devices. …
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`[T]he local voltage levels preferably depend on the application….”).
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` Harris further describes an alternative embodiment in which more than
`
`one voltage source may be provided “wherein each VRM is operable with an
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`independent voltage supply path for locally converting an external supply voltage
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`into appropriate local voltage levels.” Id., [0014]. The embodiment utilizes multiple
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`VRMs “120-1 through 120-K, [which] refer to K supply voltage paths which may
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`be coupled to various voltage sources provided within the electronic system (e.g., a
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`computer system).” Id. In this case, a “logic module 124 is provided for selecting
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`among the plurality of like voltage outputs from the VRMs 122-K in order to
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`energize the Vdd and Vcc paths 108, 106, respectively.” Id., [0015].
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`
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`B.
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`FBDIMM Standard (EX1027 & EX1028)
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`
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`“JESD205” (EX1028) is the JEDEC specification that “defines the
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`electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-
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`6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-
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`Line Memory Modules (DDR2 SDRAM FB-DIMMs).” EX1028, 9. JESD205
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`includes reference design examples which provide an initial basis for Fully Buffered
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`DIMM designs. See id.
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`
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`“JESD82-20” (EX1027) is the JEDEC specification for the Advanced
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`Memory Buffer (AMB) of a fully-buffered DIMM module (FBDIMM). JESD82-20
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`provides a reference design for the AMB that complies with the FB-DIMM
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`
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`Architecture and Protocol Specification, and which supports DDR2 SDRAM main
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`memory. EX1027, 1.
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`C. Amidi (EX1024)
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` Amidi describes a system for clock and power fault detection for a
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`memory module. EX1024, Abstract. The system includes a battery, battery
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`regulation circuitry, volatile memory, memory control state machine, controller,
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`clock detection circuit and voltage detection circuit, all collectively included in a
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`unitary memory module. See id. When system voltage drops below a reference
`
`voltage, a signal is generated that switches to battery power for the memory voltage
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`supply. See id., 4:44-52.
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`D.
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`Spiers (EX1025)
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` Spiers relates to “Non-Volatile Memory Backup for Network Storage
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`System.” EX1025, p. 1 (title). Spiers discloses that “[i]n many applications, a key
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`measure of performance is the amount of time [a] storage system takes to store data
`
`sent to it from a host computer” in response to a write command issued by the host.
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`Id., [0003]. According to Spiers, the “host computer generally keeps the write
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`command open … until the storage system reports that the data has been stored ….”
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`Id. Until the write command is closed, the host retains the data to be written so as
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`to keep the data secure, and to be ready to reissue the write command if an error
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`occurs. See id.
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`In order to retain the data, Spiers discloses that the host “dedicates a
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`portion of memory to the data
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