UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD., MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS LLC,†
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`EXHIBIT 1079:
`Petitioner’s Demonstratives for Oral Argument on September 11, 2023
`
`† Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron
`Technology Texas LLC filed a motion for joinder and a petition in IPR2023-00406
`and have been joined as petitioners in this proceeding.
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD., MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS LLC,†
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`EXHIBIT 1079:
`Petitioner’s Demonstratives for Oral Argument on September 11, 2023
`
`† Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron
`Technology Texas LLC filed a motion for joinder and a petition in IPR2023-00406
`and have been joined as petitioners in this proceeding.
`
`
`
`Petitioner Samsung Electronics Co., Ltd.’s
`Oral Argument for PTAB Hearing
`Samsung Electronics Co., Ltd. v. Netlist, Inc.,
`
`IPR2022-00996 and IPR2022-00999 (U.S. Patent Nos. 11,016,918 and 11,232,054)
`
`September 11, 2023
`
`© Copyright Baker Botts 2023. All Rights Reserved.
`
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`
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`Table of Contents
`
`Overview of the Patents and Grounds
`
`Grounds 1-3 involving Harris
`
`Grounds 4-5 involving Spiers
`
`01
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`02
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`03
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`Petitioner’s Motion to Exclude
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`04
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`2
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`01
`OVERVIEW ¢ st
`
`OVERVIEW
`
`OVERVIEW OF 918 AND ‘054 PATENTS,
`OVERVIEW OF ’918 AND ’054 PATENTS,
`AND INSTITUTED GROUNDS
`AND INSTITUTED GROUNDS
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` BAKER BOTTS
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`‘918 AND (054 PATENTS
`‘918 AND ‘054 PATENTS
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`’918 Patent
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`1. A memory module comprising:
`
`a printed circuit board (BCB) having an interface configured to fit not a
`corresponding slot connector of a host system, the interface including a plurality of edge
`connections configured to couple power, data, address and control signals between the
`memory module and the host system;
`
`a first buck converter configured to provide a first regulated voltage
`having a first voltage amplitude;
`
`a second buck converter configured to provide a second regulated
`voltage having a second voltage amplitude;
`
`a third buck converter configured to provide a third regulated voltage
`having a third voltage amplitude;
`
`a converter circuit configured to provide a fourth regulated voltage
`having a fourth voltage amplitude; and
`
`a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to one or more regulated voltages of the first, second, third
`and fourth regulated voltages, the plurality of components comprising:
`
`a plurality of synchronous dynamic random access memory (SDRAM) devices
`coupled to the first regulated voltage, and
`
`[1] at least one circuit coupled between a first portion of the plurality of
`edge connections and the plurality of SDRAM devices,
`
`[2] the at least one circuit operable to (i) receive a first plurality of address
`and control signals via the first portion of the plurality of edge connections, and (ii) output a
`second plurality of address and control signals to the plurality of SDRAM devices,
`
`[3] the at least one circuit coupled to both the second regulated voltage and
`the fourth regulated voltage,
`
`[4] wherein a first one of the second and fourth voltage amplitudes is less
`than a second one of the second and fourth voltage amplitudes.
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`918: EX1001 (‘918 Patent) at Claim 1
`
`5
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`
`
`’054 Patent
`
`1. A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into a
`corresponding slot connector of a host system, the interface including a plurality of
`edge connections configured to couple power, data, address and control signals
`between the memory module and the host system;
`
`a voltage conversion circuit coupled to the PCB and configured to
`provide at least three regulated voltages, wherein the voltage conversion circuit
`includes at least three buck converters each of which is configured to produce a
`regulated voltage of the at least three regulated voltages;
`
`[1] a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to at least one regulated voltage of the at least three
`regulated voltages,
`
`[2] the plurality of components including a plurality of synchronous
`dynamic random access memory (SDRAM) devices and
`
`[3] a first circuit that is coupled to the plurality of SDRAM devices and to
`a first set of edge connections of the plurality of edge connections,
`
`[4] wherein the first circuit is coupled to first and second regulated
`voltages of the at least three regulated voltages, and
`
`[5] wherein the plurality of SDRAM devices are coupled to the first
`regulated voltage of the at least three regulated voltages.
`
`054: EX1001 (‘054 Patent) at Claim 1
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`6
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`‘918 and ‘054 Patent Overview
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`7
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`‘918: EX1001 (918 Patent) at Fig. 12, 21:14-23, 25:54-58, 22:1-6; Paper 1 (Pet.) at 5-7; EX1003 at ¶¶68-81
`‘054: EX1001 (054 Patent) at Fig. 12, 21:14-23, 25:54-58, 22:1-6; Paper 1 (Pet.) at 4-6; EX1003 at ¶¶62-75
`
`
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`‘918 and ‘054 Patent Overview
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`BAKER BOTTS
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`‘918: EX1001 at Fig. 16, 29:18-31, 29: 39-54; Paper 1 (Pet.) at 5-7; EX1003 at ¶¶68-81
`‘054: EX1001 at Fig. 16, 29:18-31, 29:39-54; Paper 1 (Pet.) at 4-6; EX1003 at ¶¶62-75
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`8
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`
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`INSTITUTED GROUNDS &
`PRIOR ART
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`
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`Instituted Grounds
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`Grounds
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`’918 Claims
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`’054 Claims
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`Prior art
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`1
`
`2
`
`3
`
`4
`
`5
`
`Claims 1-3, 8, 14-
`15, 23
`
`Claims 1-3, 15
`
`Harris + FBDIMM Standards
`
`Claims 1-30
`
`Claims 1-30
`
`Ground 1 + Amidi
`
`Claims 1-30
`
`Claims 1-30
`
`Ground 2 + Hajeck
`
`Claims 1-30
`
`Claims 1-30
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`Spiers + Amidi
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`Claims 1-30
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`Claims 1-30
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`Ground 4 + Hajeck
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`‘918: Paper 1 (Pet.) at 3-4; Paper 10 (ID) at 8, 55
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`‘054: Paper 1 (Pet.) at 3; Paper 11 (ID) at 8, 54
`
`10
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`
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`Prior Art: Harris (U.S. Patent Pub. No. 2006/0174140) [EX1023]
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`EX1023 (Harris)
`’918: Paper 1 (Pet.) at 10; Paper 25 (Reply) at 2-7
`’054: Paper 1 (Pet.) at 9-10; Paper 26 (Reply) at 2-8
`
`11
`
`
`
`Prior Art: FBDIMM Standards [EX1027, EX1028]
`
`Exhibit
`
`Description
`
`Exemplary Teachings
`
`“JESD82-20” – FBDIMM:
`Advanced Memory Buffer
`(AMB) standard, published in
`March of 2007 by JEDEC
`
`Voltages for the “AMB buffer” on the FBDIMM memory module:
`
`EX1027
`
`EX1028
`
`Voltages for other components on the FBDIMM memory module:
`
`EX1027 at p. 83
`
`“JESD205” – DDR2 SDRAM
`Fully Buffered DIMM (FBDIMM)
`Design Specification, published
`in March of 2007 by JEDEC
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`12
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`EX1028 at p. 9
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`EX1027-EX1028 (FBDIMM Standards)
`
`‘918: Paper 1 (Pet.) at 11; Paper 25 (Reply) at 9, 15-16, 19
`
`‘054: Paper 1 (Pet.) at 10-11; Paper 26 (Reply) at 10, 16-17, 20
`
`
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`Prior Art: Amidi (U.S. Patent No. 7,724,604) [EX1024]
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`13
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`’918: Paper 1 (Pet.) at 12, 62; Paper 25 (Reply) at 18-20
`
`’054: Paper 1 (Pet.) at 11-12, 56, 60; Paper 26 (Reply) at 19-21
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`EX1024 (Amidi)
`
`
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`Prior Art: Hajeck (U.S. Patent No. 6,856,556) [EX1038]
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`’054: Paper (Pet.) at 12-13; Paper 26 (Reply) at 21-22, 35
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`14
`
`’918: Paper 1 (Pet.) at 12-13; Paper 25 (Reply) at 22, 35-37
`
`EX1038 (Hajeck), 3:30-:43 & Fig. 1
`
`
`
`Prior Art: Spiers (U.S. Patent Pub. No. 2006/0080515) [EX1025]
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`EX1025 (Spiers), Figs. 3, 5, 14
`’918: Paper 1 (Pet.) at 13-14, 114; Paper 25 (Reply) at 23-27
`’054: Paper 1 (Pet.) at 13-14, 102; Paper 26 (Reply) at 24-27
`
`15
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`
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`GROUNDS 1-3 (HARRIS) 02
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`
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`SUMMARY OF COMBINATIONS
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`Ground 1: Harris + JEDEC’s FBDIMM Standards
`
`Harris
`- One or more Voltage Regulator Modules on the
`memory module with buck converters to convert
`from 12V to lower voltages for various components
`
`- Memory module can be “Fully buffered DIMM”
`(i.e., FBDIMM)
`
`FBDIMM Standards
`- Specify particular voltages for various
`components on an FBDIMM
`
`054 Mappings
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`918 Mappings
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`‘918: Paper 1 (Pet.) at 14-19
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`‘054: Paper 1 (Pet.) at 14-19
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`18
`
`
`
`Ground 1: Harris + JEDEC’s FBDIMM Standards
`
`“Where a prior art patent discloses a range of values, showing a
`claimed value falls within that range meets a party’s burden of
`establishing the narrower claim would have been obvious where
`there is no reason to think the result would be unpredictable.”
`
`Gen. Hosp. Corp. v. Sienna Biopharms., Inc., 888 F.3d 1368, 1373 (Fed. Cir. 2018); see also,
`e.g., Iron Grip Barbell Co. v. USA Sports, Inc., 392 F.3d 1317, 1320-23 (Fed. Cir. 2004)
`(claim to three grips obvious in light of prior art teaching one, two, and four grips)
`
`054 Mappings
`
`918 Mappings
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`‘918: Paper 1 (Pet.) at 27-28
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`‘054: Paper 1 (Pet.) at 27
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`19
`
`
`
`Ground 2: adds Amidi
`
`Amidi
`- Adds battery backup and “logic” for detecting
`power faults
`
`- Also uses buck converters
`
`054 Mappings
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`918 Mappings
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`20
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`‘918: Paper 1 (Pet.) at 52-56; Paper 25 (Reply) at 18-20
`
`‘054: Paper 1 (Pet.) at 41-45; Paper 26 (Reply) at 19-21
`
`
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`Ground 3: adds Hajeck
`
`Hajeck
`- Teaches voltage detection circuit
`
`- Specifically includes monitoring both
`overvoltage and undervoltage conditions
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`‘918: Paper 1 (Pet.) at 12-13, 52-56, 75-76
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`‘054: Paper 1 (Pet.) at 12-13, 41-45, 70-71
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`21
`
`
`
`EDGE CONNECTIONS RECEIVE
`POWER FROM HOST
`
`GROUND 1
`(HARRIS + FBDIMM STANDARDS)
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`
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`The Institution Decision correctly found that Ground 1 teaches
`“edge connections configured to couple power…signals”
`
`Patent Owner argues that Petitioner has not made a prima facie
`case that Harris discloses a memory module having a PCB
`interface that receives power from the host system. Prelim.
`Resp. 14-20. Harris states, however, that DRAM devices may be
`“powered from system board or main board voltage sources.”
`Ex. 1023 ¶ 2. Harris also discloses that “external voltage sources
`may comprise any combination of known or heretofore
`unknown voltage supplies, either regulated or unregulated, and
`even including variable voltages.” Ex. 1023 ¶ 14 (emphasis
`added). Patent Owner does not argue that voltage supplied by
`a host system is not a “known” voltage supply as referenced by
`Harris. Furthermore, Petitioner indicates that the FBDIMM
`Standards show that the buffer AMB may be connected to a
`host, suggesting that the FBDIMM may derive its power from
`the host. Pet. 24 (showing figure at Ex. 1027, 4). These facts
`point to the conclusion that Harris’s external voltage source
`may be the host system notwithstanding Patent Owner’s
`arguments to the contrary.
`
`EX1023, Fig. 3
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`‘918: ID at 19-20
`See also ‘054: ID at 19-20 (similar)
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`23
`
`
`
`Harris teaches replacing standard “power supply interface pins”
`with fewer 12V pins
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`EX1023 (Harris), [0002], [0010], [0012], [0014], Fig. 3
`’918: Paper 1 (Pet.) at 10; Paper 25 (Reply) at 2-7
`’054: Paper 1 (Pet.) at 9-10; Paper 26 (Reply) at 2-8
`
`24
`
`
`
`Supplying power via edge connections was “standard”
`
`FBDIMM:
`
`Harris (FBDIMM):
`
`EX1075 (Mangione-Smith) at 163:16-22
`
`EX1028 (JEDEC’s FBDIMM Standards), p.38
`
`EX1023 (Harris) at Fig. 3
`
`’918: Paper 1 (Pet.) at 16-21; Paper 25 (Reply) at 2-7
`’054: Paper 1 (Pet.) at 16-21; Paper 26 (Reply) at 2-8
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`25
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`
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`Harris teaches supplying power from the host via edge connections
`
`EX1075 (Mangione-Smith) at 167:23-168:1
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`’918: Paper 25 (Reply) at 3-4
`’054: Paper 26 (Reply) at 3-5
`
`26
`
`EX1023 [0017], Fig. 3 (annotated)
`
`
`
`Harris’s reference to removing the “keyway” confirms industry
`standard practice of supplying power using edge connections
`
`EX1023 at [0013], Fig. 3
`
`EX2016 at 6-7; see also EX2030/2060, 117:7-:21; EX2101, 21-22; EX1075, 171:21-175:20
`
`’918: Paper 25 (Reply) at 5-6
`’054: Paper 26 (Reply) at 6-7
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`27
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`
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`Harris’s “external” voltage just needs to be external to the module
`
`EX2030/EX2060 (Wolfe) at 66:7-19
`
`EX1023 (Harris) at Fig. 1A
`
`’918: Paper 21 (POR) at 5; Paper 25 (Reply) at 2-7
`’054: Paper 22 (POR) at 7; Paper 26 (Reply) at 2-8
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`28
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`
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`Harris’s “external” voltage can come from the host computer
`
`EX2030/EX2060 (Wolfe) at 91:22-92:7; see also id. 129:24-130:17
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`EX2030/EX2060 (Wolfe) at 67:20-68:21
`
`29
`
`’054: Paper 26 (Reply) at 3
`’918: Paper 25 (Reply) at 2
`
`
`
`Harris [0019] proposes eliminating board-specific power supply in favor of a
`“technology-independent” 12V supply, not eliminating all power from the host
`
`BAKER BOTTS
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`EX1023 at [0019-0020]
`‘918: Pet. 19; EX1003, ¶221
`‘054: Pet. 19; EX1003, ¶222
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`30
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`‘918: Paper 25 (Reply) at 4-5
`‘054: Paper 26 (Reply) at 5-6
`
`
`
`Netlist’s expert admits that it was known to use a side connector to
`a battery, and an edge connector to the host, making both obvious
`
`EX2035, 39
`
`“[J]ust because ‘better alternatives’
`may exist in the prior art ‘does not
`mean that an inferior combination
`is inapt for obviousness purposes.’”
`
`Dome Pat. L.P. v. Lee,
`799 F.3d 1372, 1381 (Fed. Cir. 2015)
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`31
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`EX1075 (Mangione-Smith) at 165:10-166:12
`
`’918: Paper 25 (Reply) at 2-7
`’054: Paper 26 (Reply) at 2-8
`
`
`
`DATA, ADDRESS, AND CONTROL
`SIGNALS FROM THE HOST
`
`GROUND 1
`(HARRIS + FBDIMM STANDARDS)
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`The Institution Decision correctly found that Ground 1 teaches “data, address and
`
`control signals between the memory module and the host system”
`
`Petitioner further contends that Harris, consistent with the FBDIMM
`Standards, discloses that the edge connections are “configured to couple
`power, data, address and control signals between the memory module and
`the host system.” Pet. 21–25. Petitioner contends that the power signal
`corresponds to Harris’s voltage 104 in Figure 1A. Id. at 21 (citing Ex. 1023 ¶¶
`10, 12, 19). Petitioner contends that Harris’s buffer 112 in Figure 1A is called
`“AMB” (Advanced Memory Buffer) in the FBDIMM Standards. Pet. 23–24.
`Petitioner indicates that Harris’s buffer 112 receives data, address, and
`control signals via memory controller interface 114 and transmits these
`signals to DRAMs 110-1 to 110-N in Figure 1A. Pet. 22–25 (citing Ex. 1023 ¶
`9 (“buffer/logic component 112 is provided for buffering command/address
`(C/A) space as well as data space at least for a portion of memory devices
`110-1 through 110-N”). In addition, Petitioner argues that the FBDIMM
`Standards indicate that buffer AMB receives data signals DQ0–DQ63;
`address signals A0–A15; and control signals RAS, CAS, WE, CS, etc. Pet. 22–
`23 (citing Ex. 1028, 13).
`
`. . . .
`
`Based on our review and consideration of the current record, we determine
`that Petitioner has adequately shown that the combination of Harris and
`the FBDIMM Standards teaches this limitation for purposes of institution.
`
`EX1023, Fig. 1A
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`‘918: ID at 18-20 (emphasis added)
`See also ‘054: ID at 18-20 (similar)
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`33
`
`
`
`The AMB Buffer in an FBDIMM (like Harris) receives data,
`address, and control signals from the host
`
`EX1077 at 9
`
`EX1075 (Mangione-Smith) at 156:4-:23; see also id. at 219:2-:11 (“signals”)
`
`’054: Paper 26 (Reply) at 8-9
`’918: Paper 25 (Reply) at 7-8
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`34
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`
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`The AMB Buffer in an FBDIMM (like Harris) receives data,
`address, and control signals from the host
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`EX1023 (Harris), Fig. 3
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`EX1027 at pp. 1, 81-82
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`35
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`EX1028 at p. 13
`
`’918: Pet. at 22-25; Paper 25 (Reply) at 7-8
`’054: Pet. at 22-25; Paper 26 (Reply) at 8-9
`
`
`
`The claims require “signals,” not “dedicated pins”
`
`The claims require “signals” . . . .
`
`. . . . not “dedicated pins”
`
`[‘918 claim 1] A memory module comprising: a
`printed circuit board (PCB) having an interface
`configured to fit into a corresponding slot
`connector of a host system, the interface including
`a plurality of edge connections configured to
`couple power, data, address and control signals
`between the memory module and the host system;
`
`[‘054 claim 1] 1. A memory module comprising: a
`printed circuit board (PCB) having an interface
`configured to fit into a corresponding slot
`connector of a host system, the interface including
`a plurality of edge connections configured to
`couple power, data, address and control signals
`between the memory module and the host system;
`
`BY [NETLIST] ATTORNEY LINDSAY:
`
`Q. Are there any pins that are dedicated to data
`signals shown in the table in -- that you just
`described?
`
`THE WITNESS: No, I don't believe so.
`
`Q. Are there any dedicated address pins in the
`table that you just described?
`
`THE WITNESS: No. There are no dedicated
`address signal pins shown in this table.
`
`Q. And are there any dedicated control signal
`pins shown in the table?
`
`THE WITNESS: No, there are no dedicated control
`signal pins shown in this table.
`EX1075 (Mangione-Smith) at 214:24-215:20 (objections omitted)
`
`’054: Paper 26 (Reply) at 8-9
`’918: Paper 25 (Reply) at 7-8
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`36
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`
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`Netlist’s theory would exclude FBDIMMs, contrary to the
`preferred embodiment of the ’918 and ’054 Patents
`
`’918 and ’054 Patents
`
`“A claim construction that excludes a
`preferred embodiment is rarely, if ever
`correct and would require highly
`persuasive evidentiary support.”
`
`Kaufman v. Microsoft Corp.,
`34 F.4th 1360, 1372 (Fed. Cir. 2022)
`(emphasis added)
`
`918: EX1001 at 21:46-51
`054: EX1001 at 21:46-51
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`’054: Paper 26 (Reply) at 9-10
`’918: Paper 25 (Reply) at 8-9
`
`37
`
`
`
`OBVIOUS TO USE THREE (054) OR
`OBVIOUS TO USE THREE (’054) OR
`FOUR (918) BUCK CONVERTERS
`FOUR (’918) BUCK CONVERTERS
`
`GROUND 1
`GROUND1
`(HARRIS + FBDIMM STANDARDS)
`(HARRIS + FBDIMM STANDARDS)
`
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`
`
`The Institution Decision correctly found that Ground 1
`renders obvious the use of four buck converters
`
`Patent Owner argues that Harris requires at most two or three
`buck converters to provide the voltages needed and thus, does
`not disclose the four claimed converters. Prelim. Resp. 20-25.
`Specifically, Patent Owner contends that Harris discloses a single
`converter generating two regulated voltages, so Harris does not
`disclose four converters as claimed. Prelim. Resp. 21-22.
`Petitioner showed sufficiently that the FBDIMM Standards
`mentioned in Harris call for at least four voltages, and that given
`Harris’s teaching of a converter, it would have been obvious to
`one of ordinary skill in the art to use multiple converters,
`including well-known buck converters, to generate the four
`voltages needed. Pet. 26-31. . . .
`
`Patent Owner contends that Petitioner did not make the case that
`a person of ordinary skill in the art would have used a third buck
`converter, as opposed to a linear regulator, to provide termination
`voltage VTT. Prelim. Resp. 29–33. Petitioner explained sufficiently
`that “buck converters” were well-known as a highly-efficient way
`to step down voltages without generating excess heat or
`requiring large cooling devices, providing further motivation to
`use buck converters. Pet. 29–30.
`
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`‘918: ID at 22-24
`See also ‘054: ID at 20-23 (similar, 3 converters)
`
`39
`
`
`
`Obvious to use buck converters to provide lower, regulated voltages
`
`EX1023 (Harris) at [0010]
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`40
`
`EX1024 (Amidi) at Fig. 6
`
`EX1058 at p. 5; see also EX1075 (Mangione-Smith) at 103:21-111:17
`
`‘918: Paper 1 (Pet.) at 29-30 and 90-91; Paper 25 (Reply) at 10, 18 and 29-30
`
`‘054: Paper 1 (Pet.) at 29-30 and 85-86; Paper 26 (Reply) at 11, 19 and 30-31
`
`
`
`Obvious to use buck converters to provide lower, regulated voltages
`
`EX1075 (Mangione-Smith) at 104:23-105:2
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`41
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`EX2030/EX2060 (Wolfe) at 140:15-24
`
`‘918: Paper 1 (Pet.) at 29-30 and 90-91; Paper 25 (Reply) at 10, 18 and 29-30
`
`‘054: Paper 1 (Pet.) at 29-30 and 85-86; Paper 26 (Reply) at 11, 19 and 30-31
`
`918: Pet. at 29-30
`
`054: Pet. at 29 (similar)
`
`
`
`Obvious to use buck converters to provide lower, regulated voltages
`
`“[J]ust because ‘better alternatives’
`may exist in the prior art ‘does not
`mean that an inferior combination
`is inapt for obviousness purposes.’”
`
`Dome Pat. L.P. v. Lee,
`799 F.3d 1372, 1381 (Fed. Cir. 2015)
`
`"[I]t's not necessary to show that
`a combination is the best option,
`only that it be a suitable
`option."
`
`Intel Corp. v. PACT XPP Schweiz AG,
`61 F.4th 1373, 1380-81 (Fed. Cir. 2023)
`(reversing Board)
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`42
`
`‘054: Paper 1 (Pet.) at 29-30 and 85-86; Paper 26 (Reply) at 19 and 30-32
`
`‘918: Paper 25 (Reply) at 18 and 29-30
`
`
`
`1. Harris is not limited to one buck converter
`
`Netlist argues Harris is limited to
`one buck converter…
`
`…but Harris teaches “at least one”…
`
`Harris expressly discloses using a
`single converter to provide at least
`two of the voltages in each of
`Petitioner’s voltage mappings.
`EX2031, ¶¶75-79. Specifically,
`Harris discloses “a high-frequency
`switching voltage converter capable
`of generating tightly-controlled
`voltage levels.” EX1023, FIG. 1A,
`[0010]
`
`[0010] In accordance with the teachings of the present patent disclosure, at
`least one on-board voltage regulator module (VRM) is provided as part of
`the memory board assembly module 100A…. Preferably, a high-frequency
`switching voltage converter capable of generating tightly-controlled voltage
`levels may be implemented as the on-board VRM 102 for purposes of the
`present patent disclosure. . . .
`
`What is claimed is: 1. A memory board assembling, comprising: . . . at
`least one voltage regulator module.
`
`… and “a” is interpreted as “one or more”
`
`“[T]his court has repeatedly emphasized that an indefinite article
`‘a’ or ‘an’ in patent parlance carries the meaning of ‘one or
`more’ in open-ended claims containing the transitional phrase
`‘comprising.’ ” That “a” or “an” can mean “one or more” is best
`described as a rule, rather than merely as a presumption or even
`a convention.
`
`’918: Paper 21 (POR) at 18-19
`’054: Paper 22 (POR) at 20-21
`
`Baldwin Graphic Sys., Inc. v. Siebert, Inc.,
`512 F.3d 1338, 1342-43 (Fed. Cir. 2008)
`
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`’918: Paper 25 (Reply) at 10-13
`’054: Paper 26 (Reply) at 11-14
`
`43
`
`
`
`1. Harris is not limited to one buck converter — Figure 1A
`shows multiple buck converters
`What Netlist calls one converter
`(with two outputs)…
`
`…is two converters according to the 918/054 Patent…
`
`Harris expressly discloses using a
`single converter to provide at least
`two of the voltages in each of
`Petitioner’s voltage mappings.
`EX2031, ¶¶75-79. Specifically,
`Harris discloses “a high-frequency
`switching voltage converter capable
`of generating tightly-controlled
`voltage levels.” EX1023, FIG. 1A,
`[0010]
`
`’918: Paper 21 (POR) at 18-19
`’054: Paper 22 (POR) at 20-21
`
`2. The memory module of
`claim 1, wherein the first
`and third buck converters
`are further configured to
`operate as a dual buck
`converter.
`
`See also EX1075 (Mangione-Smith) at 117:25-118:16
`
`… and has been construed as two converters (given the two outputs)
`
`EX1023 (Harris) at Fig. 1A
`
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`EX1075, 124:22-125:8, 126:9-:18; EX2030, 97:13-98:3
`
`EX2032, 34; see also id. 18-21;
`
`’918: Paper 25 (Reply) at 10-13
`’054: Paper 26 (Reply) at 11-14
`
`44
`
`
`
`1. Harris is not limited to one buck converter — it was common
`for a single chip to have multiple buck converters
`
`EX1048 at 2
`
`EX1075 (Mangione-Smith) at 129:13-:24
`
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`45
`
`’918: Paper 25 (Reply) at 10-13
`’054: Paper 26 (Reply) at 11-14
`
`
`
`1. Harris is not limited to one buck converter — it was common
`for a single chip to have multiple buck converters
`
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`46
`
`’918: Pet. at 38-40
`’054: Pet. at 38-40
`
`
`
`1. Harris is not limited to one buck converter — it was common
`to use multiple buck converters for multiple outputs
`
`EX1062, 15; see also EX1075, 134:22-141:23; EX1078, 1 (ADP1821 datasheet)
`
`EX2030/EX2060 (Wolfe) at 53:16-:25
`
`’918: Paper 25 (Reply) at 10-13
`’054: Paper 26 (Reply) at 11-14
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`
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`1. Harris is not limited to one buck converter — and space is not
`disclosed as a problem in Harris or the 918/054 Patents
`
`EX1023 (Harris) at Fig. 1A, [0010], [0013]
`
`EX2030/EX2060 (Wolfe) at 89-1:15
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`48
`
`’918: Paper 25 (Reply) at 10-13
`’054: Paper 26 (Reply) at 11-14
`
`
`
`1. Harris is not limited to one buck converter — and chips can
`be stacked to save space
`
`EX1023 (Harris) at Fig. 3
`
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`49
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`EX1075 (Mangione-Smith) at EX1075, 74:22-75:25, 77:10-:17
`
`’918: Paper 25 (Reply) at 10-13, 19-20
`’054: Paper 26 (Reply) at 11-14, 20-21
`
`
`
`2. The Institution Decision correctly found it obvious to use
`different buck converters for different voltages (e.g., VDD vs. VDDL)
`
`Patent Owner further contends that Petitioner
`has not made out a case to use two or more
`buck converters to provide voltages having the
`same level. Prelim. Resp. 25-29. Petitioner
`explained sufficiently, however, that the FBDIMM
`Standards identify VDD, VDDQ and VDDL as well as
`VCC and VCCFBD as separate voltages of the same
`level with separate pins that can be turned on
`and off independently of one another. Pet. 30-
`31. Petitioner contends this provides
`independence for the power supplies with
`improved stability and flexibility for power
`management. Id. at 31. Petitioner also relies on
`voltage mapping C (Pet. 27) which has different
`voltage levels for the four voltages used, so
`Patent Owner’s argument, even if correct, would
`not negate Petitioner’s showing with respect to
`this voltage mapping.
`
`‘918: Paper 1 (Pet.) at 27
`
`‘054: Paper (Pet.) at 27
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`‘918: ID at 23
`See also ‘054: ID at 20-23
`
`50
`
`
`
`2. JEDEC teaches multiple converters for VDD, VDDL, and VDDQ,
`even though they are all 1.8V, to permit independent control
`
`First option: “single power
`converter” for all three
`voltages
`
`Second option: multiple
`converters to permit
`independent control
`
`EX1026 at 9 (DDR2); see also EX1046 at 15 (same for DDR3)
`
`EX1026 at 3
`
`Q. When would you use multiple regulators to generate multiple 1.8 volts output?
`
`A. It would be an ordinary design decision. One might do it when they want to sequence the power, one
`might want to do it when they turn the power on and off independently, or one may do it simply because
`it's more cost effective to use multiple small regulators than one large regulator. It's a design choice.
`
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`EX2030/EX2060 (Wolfe) at 39:2-:10
`
`‘918: Paper 1 (Pet.) at 30-31; Paper 25 (Reply) at 13-15
`
`‘054: Paper 1 (Pet.) at 29-30; Paper 26 (Reply) at 14-16
`
`
`
`2. There are known advantages to using multiple buck
`converters, even if they all output 1.8V
`
`EX2012, 73
`
`EX1062, 13
`
`918: Paper 25 (Reply) at 14
`054: Paper 26 (Reply) at 15
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`’918: Paper 1 (Pet.) at 30-31; Paper 25 (Reply) at 13-15
`’054: Paper 1 (Pet.) at 29-30; Paper 26 (Reply) at 14-16
`
`
`
`3. The Institution Decision correctly found that Harris teaches
`generating all FBDIMM voltages on the module, including VTT
`
`EX1023 at Fig. 1A
`
`Harris’s Figure 1A shows that the voltages Vcc and
`Vdd are generated on the module. On this record,
`we agree with Petitioner that it would logically
`follow to generate VTT on the module using the
`same voltage regulator module 102 as used to
`generate voltages Vcc and Vdd. See Pet. 15-19. In
`addition, “when there are a finite number of
`identified, predictable solutions, a person of
`ordinary skill has good reason to pursue the known
`options within his or her technical grasp.” KSR, 550
`U.S. at 421. Here, there are only two options –
`generate the voltage VTT on the module, as
`Petitioner indicates, or obtain the voltage VTT from
`interface pins. Petitioner’s choice of the former of
`the two options does not negate its showing of
`obviousness.
`
`‘918: ID at 24
`‘054: ID at 23
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`
`
`3. Harris teaches generating all FBDIMM voltages on the module,
`which would include VTT
`
`EX1028 at 15, 68
`
`EX1023 at [0012], Fig. 1A
`
`Q. So you think that when Harris is referring to the
`VDD pins, it includes both what the FB-DIMM
`specification calls the VTT and VDD pins?
`A. I think so because he says there's 28 of them . . .
`and the specification has 24 VDDs and 4 VTTs.
`
`EX2030/EX2060 (Wolfe) at 103:24-104:6
`
`EX1028 at 11
`
`’918: Paper 1 (Pet.) at 17-18; Paper 25 (Reply) at 15-17
`’054: Paper 1 (Pet.) at 17-18; Paper 26 (Reply) at 16-19
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`54
`
`
`
`3. Dual buck converters for VTT were common (to track VDDQ)
`
`Q. Okay. Any reason for not generating VTT locally on the DIMM board?
`A. I think if you read Harris and the FB-DIMM standard together, it's clear that it would be preferable to do it locally.
`Q. Any reason for not doing it locally?
`A. It would depend on particular circumstances. Because it has to track VDD in the standard, I think it would be preferable to do it locally.
`
`EX2030/EX2060 (Wolfe) at 72:22-73:7 (objection omitted); see also id. 196:3-197:7
`
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`’918: Paper 1 (Pet.) at 17-18, 39; Paper 25 (Reply) at 15-17
`’054: Paper 1 (Pet.) at 17-18, 39; Paper 26 (Reply) at 16-19
`
`EX1041 at 1, 9
`
`55
`
`EX1040 at 1, 11
`
`
`
`3. Dual buck converters for VTT were common (to track VDDQ) — and
`much more efficient than an LDO for converting 12V to 0.9V
`
`Q. And what were some of the trade-offs that were known at the
`time between using a buck converter and an LDO linear regulator?
`
`A. Well, in general, a buck converter might achieve what's referred
`to as higher efficiency, which is to say, all of these voltage
`regulators, voltage converters that we're talking about have some
`amount of electrical power that goes in, and a smaller amount of
`electrical power that's made available on the output. There's always
`entropy.· There's always loss.
`
`So in general, the -- it's understood that something like a switch
`regulator will have better efficiency than LDOs generally. . . .
`
`Q. Is there a way to calculate the rough efficiency of an LDO
`regulator if you know what the input voltage is and the output
`voltage is?
`
`A. If you know what the input voltage and current is, and the
`output voltage and current, you can calculate th
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