`
`
`
`Step-Down DC-to-DC Controller
`ADP1821
`
`
`FEATURES
`Wide power-input voltage range: 1 V to 24 V
`Chip supply voltage range: 3.7 V to 5.5 V
`Wide output voltage range: 0.6 V to 85% of input voltage
`1% accuracy, 0.6 V reference voltage
`All N-channel MOSFET design for low cost
`Fixed-frequency operation 300 kHz, 600 kHz, or
`synchronized operation up to 1.2 MHz
`No current sense resistor required
`Power-good output
`Programmable soft start with reverse current protection
`Soft start, thermal overload, current-limit protection
`Undervoltage lockout
`10 μA shutdown supply current
`Small, 16-lead QSOP
`APPLICATIONS
`Telecommunications and networking systems
`Set-top boxes
`Printers
`Servers
`Medical imaging systems
`Microprocessor and DSP core power supplies
`Mobile communication base stations
`
`
`GENERAL DESCRIPTION
`The ADP1821 is a versatile and inexpensive, synchronous,
`pulse-width-modulated (PWM), voltage-mode, step-down
`controller. It drives an all N-channel power stage to regulate an
`output voltage as low as 0.6 V. The ADP1821 can be configured
`to provide output voltages from 0.6 V to 85% of the input
`voltage and is sized to handle large MOSFETs for point-of-load
`regulators.
`The ADP1821 is well suited for a wide range of high power
`applications, such as DSP and processor core power in telecom-
`munications, medical imaging, high performance servers, and
`industrial applications. It operates from a 3.7 V to 5.5 V supply
`with a power input voltage ranging from 1.0 V to 24 V.
`The ADP1821 operates at a pin-selectable, fixed switching
`frequency of either 300 kHz or 600 kHz, minimizing external
`component size and cost. For noise sensitive applications, it
`can be synchronized to an external clock to achieve switching
`frequencies between 300 kHz and 1.2 MHz. The ADP1821
`includes soft start protection to limit the inrush current from
`the input supply during startup, reverse current protection
`during soft start for precharged outputs, as well as a unique
`adjustable lossless current-limit scheme utilizing external
`MOSFET sensing.
`The ADP1821 operates over the –40°C to +125°C junction
`temperature range and is available in a 16-lead QSOP.
`
`
`TA = 25°C
`FREQUENCY = 300kHz
`
`3.3V OUTPUT
`
`1.8V OUTPUT
`
`
`
`05310-002
`
`14
`
`16
`
`2
`
`4
`
`6
`8
`10
`LOAD CURRENT (A)
`Figure 2. Efficiency vs. Load Current, 5 V Input
`
`12
`
`97
`
`96
`
`95
`
`94
`
`93
`
`92
`
`91
`
`90
`
`89
`
`88
`
`87
`
`0
`
`EFFICIENCY (%)
`
`BIAS INPUT
`5V
`
`1µF
`
`10Ω
`
`1µF
`
`4.7kΩ
`
`100kΩ
`
`1.5nF
`
`PVCC
`VCC
`ADP1821
`BST
`DH
`SW
`CSL
`DL
`PGND
`FB
`
`SS
`
`GND
`
`SHDN
`FREQ
`SYNC
`PWGD
`COMP
`
`6.8nF
`
`100nF
`
`AGND
`
`D1
`
`0.47µF
`
`3.3kΩ
`
`POWER INPUT
`2.5V TO 20V
`+ CIN2
`2.2µF
`25V
`×2
`
`+ CIN1
`2.2µF
`25V
`
`M1
`
`L1 = 1µH
`
`M2
`
`M3
`
`OUTPUT
`1.8V, 20A
`
`300Ω
`
`10nF
`
`+
`
`COUT1
`10µF
`6.3V
`×2
`
`COUT2
`820µF
`2.5V
`×2
`
`2kΩ
`
`1kΩ
`
`
`
`05310-001
`
`fSW = 300kHz
`CIN1: MURATA, GRM31MR71E225k
`M1: IRLR7807Z
`CIN2: SANYO, OSCON 20SP180M
`M2, M3: IRFR3709Z
`COUT2: SANYO, OSCON 2R5SEPC820M
`D1: VISHAY BAT54
`L1: COILTRONICS, HC7-1R0
`Figure 1. Typical Operating Circuit
`
`Rev. C
`Information furnished by Analog Devices is believed to be accurate and reliable. However, no
`responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
`rights of third parties that may result from its use. Specifications subject to change without notice. No
`license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
`Trademarks and registered trademarks are the property of their respective owners.
`
`
`
`
`
`
`
`One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
`www.analog.com
`Tel: 781.329.4700
`Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
`
`Samsung Ex. 1078, p. 1
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`
`
`TABLE OF CONTENTS
`Features .............................................................................................. 1
`Applications....................................................................................... 1
`General Description ......................................................................... 1
`Revision History ............................................................................... 2
`Specifications..................................................................................... 3
`Absolute Maximum Ratings............................................................ 5
`ESD Caution.................................................................................. 5
`Simplified Block Diagram ........................................................... 5
`Pin Configuration and Function Descriptions............................. 6
`Typical Performance Characteristics ............................................. 7
`Theory of Operation ........................................................................ 9
`Soft Start ........................................................................................ 9
`Error Amplifier............................................................................. 9
`Current-Limit Scheme................................................................. 9
`MOSFET Drivers........................................................................ 10
`Input Voltage Range................................................................... 10
`Setting the Output Voltage........................................................ 10
`Switching Frequency Control and Synchronization.............. 10
`
`
`REVISION HISTORY
`4/07—Rev. B to Rev. C
`Changes to Specifications Section.................................................. 3
`Changes to Absolute Maximum Ratings Section......................... 5
`Changes to Current-Limit Scheme Section ................................ 10
`Changes to Setting the Current Limit Section............................ 14
`Added Figure 15.............................................................................. 14
`Changes to Compensating the Voltage Mode Buck
`Regulator Section............................................................................ 15
`Changes to Type II Compensator Section................................... 17
`Changes to Type III Compensator Section ................................. 18
`Changes to Application Circuits Section..................................... 21
`Changes to Figure 22...................................................................... 21
`Changes to Ordering Guide .......................................................... 23
`12/06—Rev. A to Rev. B
`Updated Format..................................................................Universal
`Changes to Features Section............................................................ 1
`Changes to Applications Section .................................................... 1
`Changes to General Description Section ...................................... 1
`Changes to Error Amplifier............................................................. 3
`Changes to PWM Controller .......................................................... 3
`Changes to Oscillator Frequency.................................................... 3
`
`
`
`
`
`
`Compensation............................................................................. 11
`Power-Good Indicator............................................................... 11
`Thermal Shutdown .................................................................... 11
`Shutdown Control...................................................................... 11
`Application Information................................................................ 12
`Selecting the Input Capacitor ................................................... 12
`Output LC Filter ......................................................................... 12
`Selecting the MOSFETs ............................................................. 13
`Setting the Current Limit .......................................................... 14
`Feedback Voltage Divider ......................................................... 14
`Compensating the Voltage Mode Buck Regulator................. 14
`Setting the Soft Start Period...................................................... 18
`PCB Layout Guideline ................................................................... 19
`Recommended Component Manufacturers........................... 20
`Application Circuits ....................................................................... 21
`Outline Dimensions....................................................................... 23
`Ordering Guide .......................................................................... 23
`
`Changes to Theory of Operation Section.......................................9
`Changes to Application Information Section............................. 12
`Added PCB Layout Section........................................................... 19
`Changes to Application Circuits Section..................................... 21
`Added Summary of Equations Section........................................ 23
`
`1/06—Rev. 0 to Rev. A
`Changes to Specifications Table ......................................................3
`Changes to Theory of Operation Section.................................... 10
`Changes to Input Voltage Range Section .................................... 11
`Added Equation 1........................................................................... 12
`Changes to Equation 7 and Equation 8 ....................................... 13
`Added Equation 9........................................................................... 13
`Changes to Equation 16................................................................. 14
`Changes to Figure 15...................................................................... 14
`Changes to Equation 21................................................................. 15
`Changes to Figure 16...................................................................... 15
`Changes to Equation 28................................................................. 15
`Updated Outline Dimensions....................................................... 18
`7/05—Revision 0: Initial Version
`
`Rev. C | Page 2 of 24
`
`Samsung Ex. 1078, p. 2
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`
`
`ADP1821
`
`
`
`SPECIFICATIONS
`VVCC = VPVCC = VSHDN = VFREQ = 5 V, SYNC = GND. All limits at temperature extremes are guaranteed via correlation using standard
`statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA=25°C.
`
`Table 1.
`Parameter
`POWER SUPPLY
`Input Voltage
`Undervoltage Lockout Threshold
`Undervoltage Lockout Threshold
`Undervoltage Lockout Hysteresis
`Quiescent Current
`Shutdown Current
`Power Stage Supply Voltage
`ERROR AMPLIFIER
`FB Regulation Voltage
`FB Regulation Voltage
`FB Input Bias Current
`Error Amplifier Open-Loop Voltage Gain
`COMP Output Sink Current
`COMP Output Source Current
`COMP Clamp High Voltage
`COMP Clamp Low Voltage
`PWM CONTROLLER
`PWM Peak Ramp Voltage
`DL Minimum On Time
`DL Minimum On-Time
`DH Maximum Duty Cycle
`DH Minimum Duty Cycle
`SOFT START
`SS Pull-Up Resistance
`SS Pull-Down Resistance
`OSCILLATOR
`Oscillator Frequency
`
`Synchronization Range
`
`SYNC Minimum Pulse Width
`CURRENT SENSE
`CSL Threshold Voltage
`CSL Output Current
`Current Sense Blanking Period
`GATE DRIVERS
`DH Rise Time
`DH Fall Time
`DL Rise Time
`DL Fall Time
`DL Low to DH High Dead Time
`DH Low to DL High Dead Time
`
`Min
`
`3.7
`2.4
`2.5
`
`
`
`1.0
`
`594
`588
`−100
`
`
`
`
`
`
`
`120
`140
`85
`
`
`
`1.65
`
`250
`470
`300
`600
`
`
`−30
`42
`
`
`
`
`
`
`
`
`
`Typ
`
`
`2.7
`2.7
`0.1
`1
`
`
`
`600
`600
`+1
`70
`600
`110
`2.4
`0.75
`
`1.25
`170
`170
`90
`1
`
`95
`2.5
`
`310
`570
`
`
`
`
`0
`50
`160
`
`16
`12
`19
`13
`33
`42
`
`Max
`
`5.5
`3.0
`2.9
`
`2
`10
`24
`
`606
`606
`+100
`
`
`
`
`
`
`
`220
`200
`
`3
`
`
`4.2
`
`375
`720
`600
`1200
`80
`
`+30
`54
`
`
`
`
`
`
`
`
`
`Unit
`
`V
`V
`V
`V
`mA
`μA
`V
`
`mV
`mV
`nA
`dB
`μA
`μA
`V
`V
`
`V
`ns
`ns
`%
`%
`
`kΩ
`kΩ
`
`kHz
`kHz
`kHz
`kHz
`ns
`
`mV
`μA
`ns
`
`ns
`ns
`ns
`ns
`ns
`ns
`
`Conditions
`
`
`
`
`VVCC rising, TJ = −40°C to +125°C
`VVCC rising, TA = 25°C
`VVCC
`IVCC + IVCC, not switching
`SHDN = GND
`
`
`TJ = −40°C to +85°C
`TJ = −40°C to +125°C
`
`
`
`
`
`
`
`
`FREQ = VCC (300 kHz)
`FREQ = VCC (300 kHz), TA = 25°C
`FREQ = GND (300 kHz)
`FREQ = GND (300 kHz)
`
`SS = GND
`VSS = 0.6 V
`
`FREQ = GND
`FREQ = VCC
`FREQ = GND
`FREQ = VCC
`
`
`Relative to PGND
`VCSL = 0 V
`
`
`CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
`CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V
`CGATE = 3 nF, VDL = VIN
`CGATE = 3 nF, VDL = 0 V
`
`
`
`Rev. C | Page 3 of 24
`
`Samsung Ex. 1078, p. 3
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`
`Parameter
`LOGIC THRESHOLDS (SHDN, SYNC, FREQ)
`SHDN, SYNC, FREQ Input High Voltage
`SHDN, SYNC, FREQ Input Low Voltage
`SYNC, FREQ Input Leakage Current
`SHDN Pull-Down Resistance
`THERMAL SHUTDOWN
`Thermal Shutdown Threshold
`Thermal Shutdown Hysteresis
`PWGD OUTPUT
`FB Overvoltage Threshold
`FB Overvoltage Hysteresis
`FB Undervoltage Threshold
`FB Undervoltage Hysteresis
`PWGD Off Current
`PWGD Low Voltage
`
`
`
`
`Conditions
`
`VVCC = 3.7 V to 5.5 V
`VVCC = 3.7 V to 5.5 V
`SYNC = FREQ = GND
`
`
`
`
`
`VFB rising
`
`VFB rising
`
`VPWGD = 5 V
`IPWGD = 10 mA
`
`
`
`Unit
`
`V
`V
`μA
`kΩ
`
`°C
`°C
`
`mV
`mV
`mV
`mV
`μA
`mV
`
`Min
`
`2.0
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Typ
`
`
`
`0.1
`100
`
`145
`10
`
`750
`35
`550
`35
`
`150
`
`Max
`
`
`0.8
`1
`
`
`
`
`
`
`
`
`
`1
`500
`
`Rev. C | Page 4 of 24
`
`Samsung Ex. 1078, p. 4
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`
`
`ADP1821
`
`
`
`ABSOLUTE MAXIMUM RATINGS
`Table 2.
`Parameter
`VCC, SHDN, SYNC, FREQ, COMP, SS, FB to
`GND, PVCC to PGND, BST to SW
`BST to GND
`CSL to GND
`DH to GND
`
`Rating
`−0.3 V to +6 V
`
`−0.3 V to +30 V
`−1 V to +30 V
`(VSW − 0.3 V) to
`(VBST + 0.3 V)
`−0.3 V to
`(VPVCC + 0.3 V)
`−2 V to +30 V
`±2 V
`150°C/W
`105°C/W
`−40°C to +85°C
`−55°C to +125°C
`−65°C to +150°C
`260°C
`
`DL to PGND
`
`SW to GND
`PGND to GND
`θJA, 2-Layer (SEMI Standard Board)
`θJA, 4-Layer (JEDEC Standard Board)
`Operating Ambient Temperature Range
`Operating Junction Temperature Range
`Storage Temperature Range
`Maximum Soldering Lead Temperature
`
`
`
`SIMPLIFIED BLOCK DIAGRAM
`
`Stresses above those listed under Absolute Maximum Ratings
`may cause permanent damage to the device. This is a stress
`rating only; functional operation of the device at these or any
`other conditions above those indicated in the operational
`section of this specification is not implied. Exposure to absolute
`maximum rating conditions for extended periods may affect
`device reliability.
`Absolute maximum ratings apply individually only, not in
`combination. Unless otherwise specified, all other voltages
`are referenced to GND.
`
`ESD CAUTION
`
`
`
`
`BST
`
`DH
`
`SW
`
`PVCC
`
`DL
`
`PGND
`
`CSL
`
`
`
`05310-003
`
`PWGD
`
`ADP1821
`
`
`
`
`
`LOGIC
`
`FAULT
`
`S
`
`R
`
`Q
`
`Q
`
`PWM
`
`VCC
`
`UVLO
`
`THERMAL
`SHUTDOWN
`
`OSCILLATOR
`
`SHDN
`
`VCC
`
`GND
`
`FREQ
`SYNC
`COMP
`
`FB
`
`SS
`
`
`
`100kΩ
`
`2.5kΩ
`
`REFERENCE
`
`OV
`
`UV
`
`0.6V
`
`0.8V
`
`FAULT
`
`UVLO
`THSD
`
`Figure 3. Simplified Block Diagram
`
`Rev. C | Page 5 of 24
`
`Samsung Ex. 1078, p. 5
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`
`
`PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
`
`
`
`
`
`
`05310-004
`
`16
`
`15
`
`14
`
`13
`
`12
`
`11
`
`10
`
`9
`
`PVCC
`DL
`PGND
`CSL
`VCC
`COMP
`FB
`SS
`
`ADP1821
`TOP VIEW
`(Not to Scale)
`
`1 2 3 4 5 6 7 8
`
`BST
`DH
`SW
`SYNC
`FREQ
`SHDN
`PWGD
`GND
`
`Figure 4. Pin Configuration
`
`Table 3. Pin Function Descriptions
`Pin No. Mnemonic Description
`1
`BST
`High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver, DH.
`The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 μF or greater
`ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate driver.
`High-Side Gate Driver Output. Connect DH to the gate of the external high-side, N-channel MOSFET switch. DH is
`powered from the capacitor between SW and BST, and its voltage swings between VSW and VBST.
`Power Switch Node. Connect the source of the high-side, N-channel MOSFET switch and the drain of the low-side,
`N-channel MOSFET synchronous rectifier to SW. SW powers the output through the output LC filter.
`Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the converter
`switching frequency to the applied signal. The maximum SYNC frequency is limited to 2 times the nominal internal
`frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND.
`Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or high
`to select 600 kHz. Do not leave FREQ unconnected.
`Active Low, DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter and low to turn it off. Connect
`SHDN to VCC for automatic startup.
`Open-Drain, Power-Good Output. PWGD sinks current to GND when the output voltage is above or below the
`regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator.
`Analog Ground. Connect GND to PGND at a single point as close as possible to the internal circuitry (IC).
`Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded,
`SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF capacitor to a 1 μF
`capacitor from SS to GND to set the soft start period. See the Soft Start section.
`Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage. See
`the Setting the Output Voltage section.
`Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation control
`system. See the Compensation section.
`Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with a 0.1 μF or greater
`capacitor connected as close as possible to the IC.
`Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit. See the Setting the
`Current Limit section.
`Power Ground. Connect GND to PGND at a single point as close as possible to the IC.
`Low-Side Gate Driver Output. Connect DL to the gate of the low-side, N-channel MOSFET synchronous rectifier. The
`DL voltage swings between PGND and PVCC.
`Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver, DL. Bypass PVCC to PGND with a
`1 μF or greater capacitor connected as close as possible to the IC.
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`15
`
`16
`
`DH
`
`SW
`
`SYNC
`
`FREQ
`
`SHDN
`
`PWGD
`
`GND
`SS
`
`FB
`
`COMP
`
`VCC
`
`CSL
`
`PGND
`DL
`
`PVCC
`
`
`
`
`Rev. C | Page 6 of 24
`
`Samsung Ex. 1078, p. 6
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`
`
`
`
`TYPICAL PERFORMANCE CHARACTERISTICS
`
`ADP1821
`
`0.6003
`
`0.6002
`
`0.6001
`
`0.6000
`
`0.5999
`
`0.5998
`
`0.5997
`
`FEEDBACK VOLTAGE (V)
`
`TA = 25°C
`FREQUENCY = 300kHz
`
`3.3V OUTPUT
`
`1.8V OUTPUT
`
`
`
`05310-008
`
`10
`30
`50
`TEMPERATURE (°C)
`
`70
`
`90
`
`110
`
`0.5996
`–50
`
`–30
`
`–10
`
`
`
`05310-005
`
`12
`
`14
`
`16
`
`6
`8
`10
`LOAD CURRENT (A)
`
`0
`
`2
`
`4
`
`97
`
`96
`
`95
`
`94
`
`93
`
`92
`
`91
`
`90
`
`89
`
`88
`
`87
`
`EFFICIENCY (%)
`
`Figure 5. Efficiency vs. Load Current, VIN = 5 V, VOUT = 3.3 V, 1.8 V
`
`Figure 8. FB Regulation Voltage vs. Temperature
`
`94
`
`92
`
`90
`
`TA = 25°C
`FREQUENCY = 300kHz
`
`3.3V OUTPUT
`
`700
`
`600
`
`500
`
`600kHz
`
`300kHz
`
`
`
`05310-009
`
`100
`
`0
`50
`TEMPERATURE (°C)
`
`400
`
`300
`
`200
`
`100
`
`0–
`
`50
`
`SWITCHING FREQUENCY (kHz)
`
`1.8V OUTPUT
`
`
`
`05310-006
`
`12
`
`14
`
`16
`
`2
`
`4
`
`6
`8
`10
`LOAD CURRENT (A)
`
`88
`
`86
`
`84
`
`82
`
`80
`
`0
`
`EFFICIENCY (%)
`
`Figure 6. Efficiency vs. Load Current, VIN = 12 V, VOUT = 3.3 V, 1.8 V
`
`Figure 9. Switching Frequency vs. Temperature
`
`OUTPUT VOLTAGE
`(20mV/DIV)
`
`LOAD CURRENT
`(5A/DIV)
`
`1400
`
`1200
`
`1000
`
`800
`
`600
`
`400
`
`200
`
`VCC CURRENT (µA)
`
`
`
`05310-010
`
`
`
`05310-007
`
`6
`
`2
`
`3
`VCC VOLTAGE (V)
`
`4
`
`5
`
`0
`
`0
`
`1
`
`Figure 7. VCC Supply Current vs. VCC Voltage
`
`Figure 10. Load Transient Response, 1.5 A to 15 A
`
`Rev. C | Page 7 of 24
`
`Samsung Ex. 1078, p. 7
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`
`
`OUTPUT VOLTAGE
`(50mV/DIV)
`
`INPUT VOLTAGE
`(5V/DIV)
`
`OUTPUT VOLTAGE
`(1V/DIV)
`
`SHDN (5V/DIV)
`
`PWGD (5V/DIV)
`
`
`
`05310-013
`
`
`
`05310-014
`
`
`
`05310-011
`
`Figure 11. Line Transient Response, 10 V to 16 V
`
`Figure 13. Power-On Response, Prebiased Output
`
`OUTPUT VOLTAGE
`(1V/DIV)
`
`SHDN (5V/DIV)
`
`PWGD (5V/DIV)
`
`OUTPUT VOLTAGE
`(1V/DIV)
`
`LOAD CURRENT
`(10A/DIV)
`
`
`
`05310-012
`
`Figure 12. Power-On Response
`
`Figure 14. Output Short-Circuit Response and Recovery
`
`
`
`
`
`Rev. C | Page 8 of 24
`
`Samsung Ex. 1078, p. 8
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`
`
`ADP1821
`
`
`
`THEORY OF OPERATION
`The ADP1821 is a versatile, economical, synchronous-rectified,
`fixed-frequency, PWM, voltage mode step-down controller
`capable of generating an output voltage as low as 0.6 V. It is ideal
`for a wide range of high power applications, such as DSP power
`and processor core power in telecommunications, medical
`imaging, and industrial applications. The ADP1821 controller
`operates from a 3.7 V to 5.5 V supply with a power input voltage
`ranging from 1.0 V to 24 V.
`The ADP1821 operates at a fixed, internally set 300 kHz or
`600 kHz switching frequency that is controlled by the state of
`the FREQ input. The high frequency reduces external compo-
`nent size and cost while maintaining high efficiency. For noise
`sensitive applications where the switching frequency needs to be
`more tightly controlled, synchronize the ADP1821 to an external
`signal whose frequency is between 300 kHz and 1.2 MHz.
`The ADP1821 includes adjustable soft start with output reverse-
`current protection, and a unique adjustable, lossless current
`limit. It operates over the −40°C to +125°C temperature range
`and is available in a space-saving, 16-lead QSOP.
`SOFT START
`When powering up or resuming operation after shutdown, over-
`load, or short-circuit conditions, the ADP1821 employs an
`adjustable soft start feature that reduces input current transients
`and prevents output voltage overshoot at start-up and overload
`conditions. The soft start period is set by the value of the soft
`start capacitor, CSS, between SS and GND.
`When starting the ADP1821, CSS is initially discharged. It is
`enabled when SHDN is high and VCC is above the undervoltage
`lockout threshold. CSS begins charging to 0.8 V through an
`internal 100 kΩ resistor. As CSS charges, the regulation voltage at
`FB is limited to the lesser of either the voltage at SS or the internal
`0.6 V reference voltage. As the voltage at SS rises, the output
`voltage rises proportionally until the voltage at SS exceeds 0.6 V. At
`this time, the output voltage is regulated to the desired voltage.
`If the output voltage is precharged prior to turn-on, the ADP1821
`limits reverse inductor current, which would discharge the output
`voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage,
`the reverse current is re-enabled to allow the output voltage
`regulation to be independent of load current.
`ERROR AMPLIFIER
`The ADP1821 error amplifier is an operational amplifier. The
`ADP1821 senses the output voltages through an external
`resistor divider at the FB pin. The FB pin is the inverting input
`to the error amplifier. The error amplifier compares this feed-
`back voltage to the internal 0.6 V reference, and the output of
`the error amplifier appears at the COMP pin. The COMP pin
`voltage then directly controls the duty cycle of the switching
`converter.
`A series/parallel RC network is tied between the FB pin and the
`COMP pin to provide the compensation for the buck converter
`Rev. C | Page 9 of 24
`
`control loop. A detailed design procedure for compensating the
`system is provided in the Compensating the Voltage Mode Buck
`Regulator section.
`The error amplifier output is clamped between a lower limit of
`about 0.7 V and a higher limit of about 2.4 V. When the COMP pin
`is low, the switching duty cycle goes to 0%, and when the COMP
`pin is high, the switching duty cycle goes to the maximum.
`The SS pin is an auxiliary positive input to the error amplifier.
`Whichever voltage is lowest, SS or the internal 0.6 V reference,
`controls the FB pin voltage and thus the output. As a conse-
`quence, if two of these inputs are close to each other, a small
`offset is imposed on the error amplifier.
`CURRENT-LIMIT SCHEME
`The ADP1821 employs a unique, programmable, cycle-by-cycle,
`lossless current-limit circuit that uses an ordinary, inexpensive
`resistor to set the threshold. Every switching cycle, the synchronous
`rectifier turns on for a minimum time and the voltage drop across
`the MOSFET RDSON is measured to determine if the current is
`too high.
`This measurement is done by an internal current limit com-
`parator and an external current-limit set resistor. The resistor
`is connected between the switch node (that is the drain of the
`rectifier MOSFET) and the CSL pin. The CSL pin, which is the
`inverting input of the comparator, forces 50 μA through the
`resistor to create an offset voltage drop across it.
`When the inductor current is flowing in the MOSFET rectifier,
`its drain is forced below PGND by the voltage drop across its
`RDSON. If the RDSON voltage drop exceeds the preset drop on the
`current-limit set resistor, the inverting comparator input is
`similarly forced below PGND and an overcurrent fault is flagged.
`The normal transient ringing on the switch node is ignored
`for 100 ns after the synchronous rectifier turns on, therefore,
`the over current condition must also persist for 100 ns for a
`fault to be flagged.
`When the ADP1821 senses an overcurrent condition, the next
`switching cycle is suppressed, the soft start capacitor is discharged
`through an internal 2.5 kΩ resistor, and the error amplifier
`output voltage is pulled down. The output behaves like a
`constant current source around the preset current limit when
`the overcurrent condition exists. The ADP1821 remains in this
`mode for as long as the overcurrent condition persists. In the
`event of a short circuit, the short-circuit output current is the
`current limit set by the RCL resistor and is monitored cycle by
`cycle. When the overcurrent condition is removed, operation
`resumes in soft start mode.
`The ADP1821 also offers a technique for implementing a
`current-limit foldback in the event of a short circuit with the
`use of an additional resistor. See the Setting the Current Limit
`section for more information.
`
`Samsung Ex. 1078, p. 9
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`
`MOSFET DRIVERS
`The DH pin drives the high-side switch MOSFET. This is a
`boosted 5 V gate driver that is powered by a bootstrap capacitor
`circuit. This configuration allows the high-side, N-channel
`MOSFET gate to be driven above the input voltage, allowing full
`enhancement and a low voltage drop across the MOSFET. The
`bootstrap capacitor is connected from the SW pin to the BST
`pin. A bootstrap Schottky diode connected from the PVCC pin
`to the BST pin recharges the bootstrap capacitor every time the
`SW node goes low. Use a bootstrap capacitor value greater than
`100× the high-side MOSFET input capacitance.
`In practice, the switch node can run up to 24 V of input voltage,
`and the boost nodes can operate more than 5 V above this to
`allow full gate drive. The power input voltage can be run from
`1 V to 24 V.
`The switching cycle is initiated by the internal clock signal. The
`high-side MOSFET is turned on by the DH driver, and the SW
`node goes high, pulling up on the inductor. When the internally
`generated ramp signal crosses the COMP pin voltage, the switch
`MOSFET is turned off and the low-side synchronous rectifier
`MOSFET is turned on by the DL driver. Active break-before-
`make circuitry as well as a supplemental fixed dead time are
`used to prevent cross-conduction in the switches.
`The DL pin provides the gate drive for the low-side MOSFET
`synchronous rectifier. Internal circuitry monitors the external
`MOSFETs to ensure break-before-make switching to prevent
`cross-conduction. An active dead-time reduction circuit
`reduces the break-before-make time of the switching to limit
`the losses due to current flowing through the synchronous
`rectifier body diode.
`The PVCC pin provides power to the low-side drivers. It is
`limited to 5.5 V maximum input and should have a local
`decoupling capacitor to PGND.
`The synchronous rectifier is turned on for a minimum time
`of about 200 ns on every switching cycle in order to sense the
`current. This and the nonoverlap dead time put a limit on the
`maximum high-side switch duty cycle based on the selected
`switching frequency. Typically, this is about 90% at 300 kHz
`switching, and at 1 MHz switching, it reduces to about 70%
`maximum duty cycle.
`INPUT VOLTAGE RANGE
`The ADP1821 takes its internal power from the VCC and PVCC
`inputs. PVCC powers the low-side MOSFET gate drive (DL),
`and VCC powers the internal control circuitry. Both of these
`inputs are limited to between 3.7 V and 5.5 V. Bypass PVCC to
`PGND with a 1 μF or greater capacitor. Bypass VCC to GND
`with a 0.1 μF or greater capacitor.
`The power input to the dc-to-dc converter can range between
`1.2× the output voltage and 24 V. Bypass the power input to
`PGND with a suitably large capacitor. See the Selecting the
`Input Capacitor section.
`
`
`
`SETTING THE OUTPUT VOLTAGE
`The output voltage is set using a resistive voltage divider from
`the output to FB. The voltage divider drops the output voltage
`to the 0.6 V FB regulation voltage to set the regulation output
`voltage. The output voltage is set to voltages as low as 0.6 V and
`as high as 85% of the minimum power input voltage (see the
`Feedback Voltage Divider section).
`SWITCHING FREQUENCY CONTROL AND
`SYNCHRONIZATION
`The ADP1821 has a logic-controlled frequency select input (FREQ)
`which sets the switching frequency to 300 kHz or 600 kHz. Drive
`FREQ low for 300 kHz and high for 600 kHz.
`The SYNC input is used to synchronize the converter switching
`frequency to an external signal. The converter switching can be
`synchronized to an external signal. This allows multiple ADP1821
`converters to be operated at the same frequency to prevent
`frequency beating or other interactions.
`To synchronize the ADP1821 switching to an external signal,
`drive the SYNC input with a synchronizing signal. The ADP1821
`can only synchronize up to 2× the nominal oscillator frequency.
`If the frequency is set to 300 kHz (FREQ connected to GND),
`then the synchronization frequency needs to be in between
`300 kHz and 600 kHz. Since the 300 kHz setting has a mini-
`mum specification (see Table 1) of 250 kHz and a maximum
`of 375 kHz over the specified temperature range, the recom-
`mended synchronization frequency range is between 375 kHz
`and 500 kHz to cover the whole range of part-to-part variation
`and over the operating temperature range. If the frequency is set
`to 600 kHz (FREQ connected to VCC), then the synchronization
`frequency needs to be in between 600 kHz and 1.2 MHz. Since
`the 600 kHz setting has a minimum specification (see Table 1)
`of 470 kHz and a maximum of 720 kHz over the specified tem-
`perature range, the recommended synchronization frequency
`range is between 720 kHz and 940 kHz to cover the whole range
`of part-to-part variation and over the operating temperature
`range. Driving SYNC faster than recommended for the FREQ
`setting results in a small ramp signal, which could affect the
`signal-to-noise ratio and the modulator gain and stability.
`When an external clock is detected at the first SYNC edge,
`the internal oscillator is reset and clock control shifts to SYNC.
`The SYNC edges then trigger subsequent clocking of the PWM
`outputs. The DH rising edges appear about 320 ns after the cor-
`responding SYNC edge, and the frequency is locked to the
`external signal. If the external SYNC signal disappears during
`operation, the ADP1821 reverts to its internal oscillator and
`experiences a delay of no more than a single cycle of the
`internal oscillator.
`
`Rev. C | Page 10 of 24
`
`Samsung Ex. 1078, p. 10
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`

`

`ADP1821
`
`THERMAL SHUTDOWN
`The ADP1821 controller does not generate much heat under
`normal conditions, even when driving a relatively large MOSFET.
`However, the surrounding power components or other circuits
`on the same PCB could heat up the PCB to an unsafe operating
`temperature. The ADP1821 controller goes into shutdown and
`sh