`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`
`
`
`
`___________________
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`
`PATENT OWNER RESPONSE
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`11204497
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`TABLE OF CONTENTS
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`
`Page
`
`I.
`
`B.
`
`C.
`
`PETITIONER IMPROPERLY INCORPORATES BY
`REFERENCE ............................................................................................... 1
`SKILL LEVEL OF A POSITA .................................................................... 1
`II.
`III. CLAIM CONSTRUCTION ......................................................................... 1
`IV. THE CLAIMS ARE NOT OBVIOUS UNDER GROUNDS 1-3 ................ 3
`A. Harris Does Not Disclose or Suggest a Memory Module
`Having a PCB Interface that Receives Voltage/Power from a
`Host System ........................................................................................ 3
`Grounds 1-3 Do Not Disclose Elements 1(b), 16(b), 23(b)
`and 1(i)(2), claims 8, 14 and 21 ....................................................... 11
`A POSITA Would Not Have Modified Harris’ Memory
`Module to Have Four Converters as Petitioner Asserts ................... 15
`1.
`A POSITA Would not have Used Four Converters ............... 17
`2.
`A POSITA Would Not Have Used Separate
`Converters to Generate VDD/VDDQ/VDDL or
`VCC/VCCFBD ...................................................................... 21
`Petitioner Fails to Establish a Motivation for Using a
`Third Buck Converter to Provide VTT .................................... 27
`POSITAs Would Not Use a Buck Converter to Provide
`VDDSPD .................................................................................... 30
`D. A POSITA Would Not Have Substituted Amidi’s Battery
`Backup Power in Place of Harris’ Redundant Power Supplies
`(Grounds 2 and 3) ............................................................................. 31
`Grounds 1-3 Do Not Disclose or Suggest Recited “Pre-
`Regulated Input Voltage” (Claims 16-22, 30) ................................. 38
`Petitioner Failed To Establish That Claims 5-7, 9-13, 16-22,
`and 24-27 are Obvious ..................................................................... 38
`
`3.
`
`4.
`
`E.
`
`F.
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`Page
`
`
`
`V.
`
`2.
`
`C.
`
`Claims 5, 16, 24 and dependent claims ................................. 38
`1.
`Claims 10-11, 15, 22 .............................................................. 43
`2.
`Claims 11-12, 18-19, 25-26 ................................................... 43
`3.
`THE CLAIMS ARE NOT OBVIOUS UNDER GROUNDS 4-5 .............. 44
`A.
`Spiers’ PCI card is not a memory module ....................................... 44
`B.
`Petitioner Failed to Establish that Spiers, Alone or in
`Combination, Renders Obvious the Requirement for Four
`Regulated Voltages ........................................................................... 48
`1.
`Spiers’ Volatile Memory Devices in the Backup
`Device are SDR SDRAMs ..................................................... 48
`The Petition Does Not Explain Why a POSITA Would
`Have Replaced Spiers’ SDRAMs with DDR2 or
`DDR3 ..................................................................................... 53
`A POSITA Would Not Have Modified Spiers Using Four
`Buck Converters on the Memory Module ........................................ 60
`1.
`No reasons were given for using a buck converter for
`VTT (Mappings A-B) .............................................................. 60
`No reason is provided for equipping Spiers with
`multiple 1.8V regulators (Mappings B-C) ............................. 63
`No reason is provided for equipping Spiers with two
`buck converters for generating 1.5V and 1.8V output
`(mapping A) ........................................................................... 64
`No reasons were provided for why Spiers’ 5V-to-3.3V
`regulator 184 is a buck converter (all mappings) .................. 65
`D. Grounds 4-5 Do Not Disclose or Suggest Recited “Pre-
`Regulated Input Voltage” (Claims 16-22, 30) ................................. 69
`
`2.
`
`3.
`
`4.
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`Page
`
`E.
`
`F.
`G.
`
`Petitioner Has Presented No Competent Evidence for Claim
`23 ...................................................................................................... 71
`Grounds 4-5 Do Not Disclose Claim 13 Limitation ........................ 72
`Petitioner Failed To Establish That Claims 5-7, 9-13, 16-22,
`and 24-27 are Obvious ..................................................................... 73
`H. Grounds 4 and 5 Do Not Disclose Registered First Plurality
`of C/A Signals (Claims 8, 14) .......................................................... 75
`VI. CONCLUSION ........................................................................................... 76
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`Case No. IPR2022-00996
`Patent No. 11,016,918
`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Cisco Systems, Inc. v. C-Cation Techs., LLC,
`IPR2014-00454 (PTAB Aug. 29, 2014) ........................................................... 1, 2
`In re Enhanced Security Research, LLC,
`739 F.3d 1347 (Fed. Cir. 2014) .................................................................... 20, 21
`Raytheon Techs. Corp. v. General Electric. Co.,
`993 F.3d 1374 (Fed. Cir. 2021) ...................................................................... 9, 10
`South-Tek Sys., LLC v. Engineered Corrosion Sols., LLC,
`748 F. App’x. 1003 (Fed. Cir. 2018) .................................................................. 33
`TQ Delta, LLC v. Cisco Systems, Inc.,
`942 F.3d 1352 (Fed. Cir. 2019) .................................................................... 53, 69
`In re Van Os,
`844 F.3d 1359 (Fed. Cir. 2017) .......................................................................... 28
`Other Authorities
`37 C.F.R. § 42.6(a)(3) ............................................................................................ 1, 2
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`Case No. IPR2022-00996
` Patent No. 11,016,918
`
`EXHIBIT LIST
`
`Document
`Declaration of Dr. Sunil P. Khatri
`U.S. 8,301,833
`Belloni, M. et al., A 4-Output Single-Inductor DC-DC Buck
`Converter with Self-Boosted Switch Drivers and 1.2A Total
`Output Current, ISSCC 2008, Session 24.6
`Ma, Dongsheng et al., Single-Inductor Multiple-Output
`Switching Converters With Time-Multiplexing Control in
`Discontinuous Conduction Mode, IEEE J. of Solid-State
`Circuits, 38(1) (Jan. 2003)
`U.S. 6,067,2451
`Micron Technical Note, TN-47-05 DDR2 Power Solutions for
`Notebooks Overview (2004)
`Texas Instruments, LP29996-N, LP2296A DDR Termination
`Regulator (Nov. 2002-Revised Dec. 2016)
`National Semiconductor, LP2996 DDR Termination Regulator
`(June 2006), downloaded from
`https://datasheet.octopart.com/LP2996MR-NOPB-Texas-
`Instruments-datasheet-7837571.pdf (last visited 09/08/2022)
`National Semiconductor, LP2997 DDR-II Termination Regulator
`(June 2006), downloaded from
`https://www.jameco.com/Jameco/Products/ProdDS/843930.pdf
`(last visited 09/08/2022)
`National Semiconductor, LP2998 DDR-II and DDR-I
`Termination Regulator (Dec. 12, 2007), downloaded from
`https://www.semiee.com/file/backup/INTERSIL-LP2998.pdf
`(last visited 09/08/2022)
`Bergveld, H. J., Battery Management Systems Design by
`Modeling, Royal Philips Electronics N.V. (2001)
`
`- v -
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`
`
`Exhibit No.
`EX2001
`EX2002
`EX2003
`
`EX2004
`
`EX2005
`EX2006
`
`EX2007
`
`EX2008
`
`EX2009
`
`EX2010
`
`EX2011
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`

`

`Case No. IPR2022-00996
` Patent No. 11,016,918
`
`
`
`Document
`Romo, Joaquin, DDR Memories: Comparison and overview,
`NXP technical note, downloaded from
`https://www.nxp.com/docs/en/supporting-
`information/BeyondBits2article17.pdf (last access 09/08/2022).
`As downloaded the file shows the following meta data:
`
`
`JEDEC Standard No. 21-C, PC133 SDRAM Unbuffered SO-
`DIMM Reference Design Specification Rev. 1.02 (2001)
`Qimonda HYB39SC256[80/16]0FE, HYI39SC256[80/16]OFF
`datasheet (June 2007), downloaded from
`https://pdf.dzsc.com/200810211/200809251204372352.pdf (last
`visited 09/08/2022)
`Siemens HYS64/72V2200GU-8/-10, HYS64/72V4220GU-8/-10
`datasheet (June 1998), downloaded from
`https://cdn.datasheetspdf.com/pdf-down/P/C/6/PC66-222-
`920_SiemensSemiconductorGroup.pdf (last visited 09/08/2022)
`EURESYS, PCI Bus Variation Technical Note (2006),
`downloaded from PCI Bus Variation - Technology Note
`(euresys.com) (last accessed 09/08/2022)
`Qimonda HY[B/I]39S256[40/80/16]0FT(L) etc. datasheet
`(September 2007), downloaded from
`https://cms.nacsemi.com/content/AuthDatasheets/QMDAS00628
`-1.pdf (last visited 09/08/2022)
`Transcend, What is the difference between SDRAM, DDR1,
`DDR2, DDR3 and DDR4? Downloaded from
`https://www.transcend-info.com/support/faq-296#:~:text=DDR3
`(last visited 09/08/2022)
`Transcend company profile, https://us.transcend-
`info.com/about/company (last visited 09/08/2022)
`Brown, M., Power Supply Cookbook, Newnes (2d.) (2001)
`
`- vi -
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`
`
`Exhibit No.
`EX2012
`
`EX2013
`
`EX2014
`
`EX2015
`
`EX2016
`
`EX2017
`
`EX2018
`
`EX2019
`
`EX2020
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`

`EX2022
`
`EX2023
`
`EX2024
`
`EX2025
`
`EX2026
`
`
`
`Exhibit No.
`EX2021
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`Case No. IPR2022-00996
` Patent No. 11,016,918
`
`
`
`Document
`Texas Instruments, Low Dropout Operation in a Buck Converter
`(SLUA928A, December 2018 — revised March. 2019),
`downloaded from Low Dropout Operation in a Buck Converter
`(Rev. A) (last visited 09/08/2022)
`Electronic Design, Simple Soft-Start Circuitry Provides Long
`Startup Times (June 22, 1998), downloaded from
`https://www.electronicdesign.com/power-
`management/article/21801244/simple-softstart-circuitry-
`provides-long-startup-times (last visited 09/08/2022)
`Micron Technical Note, TN-04-30, Various Methods of DRAM
`Refresh (1999), downloaded from DT30 (reactivemicro.com)
`(last visited 09/08/2022)
`Schmid, Patrick, Understanding Hard Drive Performance
`(March 5, 2007), downloaded from
`https://www.tomshardware.com/reviews/understanding-hard-
`drive-performance,1557-5.html (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded
`from https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/256mb_sdr.pdf (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded
`from https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/64mb_x4x8x16_sdram.pdf (last visited 09/08/2022)
`Transcend, DDR2 SO-DIMM datasheet
`EX2027
`EX2028 Micron Technical Note TN-41-13, DDR3 Point-to-Point Design
`Support Introduction (2013), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/technical-
`note/dram/tn4113_ddr3_point_to_point_design.pdf (last visited
`09/08/2022)
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`Case No. IPR2022-00996
` Patent No. 11,016,918
`
`
`
`Document
`PCI Technology Overview (Feb. 2003)
`downloaded from
`https://web.archive.org/web/20040721012143/http://www.cs.unc
`.edu/Research/stc/FAQs/pci-overview.pdf (Wayback Machine
`(archive.org)) (last visited 09/08/2022)
`Deposition transcripts of Dr. Andrew Wolfe with errata (March
`16-17, 2023)
`Declaration of Dr. William Henry Mangione-Smith
`Markman Order, Netlist, Inc. v. Samsung Electronics Co., Ltd.,
`Civ. Action 2:21-cv-00463-JRG, Dkt. 114 (E.D. Tex. filed Dec.
`14, 2022)
`Samsung’s Objections to Claim Construction Memorandum
`Order, Netlist, Inc. v. Samsung Electronics Co., Ltd., Civ. Action
`2:21-cv-00463-JRG, Dkt. 136 (E.D. Tex. filed Dec. 29, 2022)
`Bruce Jacob et al., Memory Systems: Cache, DRAM, Disk
`(2008)
`Netlist Presentation (excerpt)
`AgigA Tech et al., “NVDIMM Hands on Lab,” Flash Memory
`Summit 2014 (Aug. 5-6, 2014), downloaded from
`https://www.snia.org/sites/default/files/FMS%20NVDIMM%20
`Demo%20SIG%20HOL%20Aug'14%20final.pdf.
`Intel, Power Supply Design Guide for Desktop Platform Form
`Factors, Rev. 1.1 (March, 2007), downloaded from
`https://web.archive.org/web/20100601215705/http://www.formf
`actors.org/developer%5Cspecs%5CPSU_DG_rev_1_1.pdf
`Intel, ATX12V, Power Supply Design Guide, Version 2.2 (March
`2005), downloaded from
`https://web.archive.org/web/20070403181612/http://www.formf
`actors.org/developer/specs/ATX12V_PSDG_2_2_public_br2.pdf
`IDT, IDTAMB0480 Product Brief (“Advanced Memory Buffer
`for Fully Buffered DIMM Modules) (April 2006), downloaded
`from https://pdf1.alldatasheet.com/datasheet-
`pdf/view/199557/IDT/IDTAMB0480.html
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`
`
`Exhibit No.
`EX2029
`
`EX2030
`
`EX2031
`EX2032
`
`EX2033
`
`EX2034
`
`EX2035
`EX2036
`
`EX2037
`
`EX2038
`
`EX2039
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`Case No. IPR2022-00996
` Patent No. 11,016,918
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`
`
`Document
`Ganesh, B. et. al., Fully-Buffer DIMM Memory Architectures:
`Understanding Mechanisms, Overheads and Scaling,
`HPCA2007
`Chang, K. K. et al., Understanding Reduced-Voltage Operation
`in Modern DRAM Chips: Characterization, Analysis, and
`Mechanisms, arXiv:1705.10292v1 [cs.AR] (May 29, 2017)
`Kingston Technology, KVR667D2D4F5/2G FBDIMM datasheet
`(4/14/06), downloaded from
`https://www.kingston.com/dataSheets/KVR667D2D4F5_2G.pdf.
`Samsung, Samsung Unveils New Power Management Solutions
`for DDR5 Modules, downloaded from
`https://semiconductor.samsung.com/newsroom/news/samsung-
`unveils-new-power-management-solutions-for-ddr5-modules/
`Micron, 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2
`SDRAM RDIMM Features (2003), downloaded from
`https://media-www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/modules/rdimm/htf9c32_64_128x72.pdf?rev=ca2587e210f
`14889ad6fe88e3511e938
`Micron, 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM
`SODIMM Features (2008), downloaded from https://media-
`www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/modules/sodimm/htf16c128_256_512x64hz.pdf?rev=2b5a
`707721a24f4facccd8c86aaddfc7
`JEDEC Standard No. 21C, 4.20.11 – 200-Pin DDR2 SDRAM
`Unbuffered SO-DIMM Design Specification, Rev. 2.5 (Release
`18)
`Smart Modular Technologies, SG5127FBD225652-SA
`FBDIMM Datasheet (March 20, 2007), downloaded from
`https://datasheet.ciiva.com/8371/sg5127fbd225652-sa-
`8371204.pdf
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`
`
`Exhibit No.
`EX2040
`
`EX2041
`
`EX2042
`
`EX2043
`
`EX2044
`
`EX2045
`
`EX2046
`
`EX2047
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`Case No. IPR2022-00996
` Patent No. 11,016,918
`
`
`
`Document
`Micron, 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB
`x72) Features (2005), downloaded from
`https://datasheet.octopart.com/MT18HTF12872FDY-667B5E3-
`Micron-datasheet-20608.pdf
`Samsung Electronics, DDR2 Fully Buffered DIMM, 240pin
`FBDIMMs based on 1Gb C-Die, Rev. 1.52 (April 2008),
`downloaded from
`https://www.compuram.biz/documents/datasheet/143851ds_ddr2
`_1gb_c-die_based_fbdimm_rev152.pdf
`Texas Instruments, TPS51116 Datasheet (2008)
`Texas Instruments, Serial Presence Detect (1998), downloaded
`from http://www.ti.com/lit/pdf/smmu001
`Mikhaylov, K., Evaluation of Power Efficiency for Digital Serial
`Interfaces of Microcontrollers, 2012 5th Int’l Conference on New
`Technologies, Mobility and Security (NTMS)
`Dell Perc H700 G5V20 SAS PCIe x8 RAID Controller 1GB NV
`Cache Adapter (image)
`“TI ATI unveils next-generation 3-A DDR termination
`regulator,” downloaded from
`https://www.electronicproducts.com/ti-unveils-next-generation-
`3-a-ddr-termination-regulatorlinear-regulator-supports-ddr3-
`power-requirements-for/
`JEDEC, TG401_1, VR on DIMM TG Report (Dec. 2011)
`Deposition transcripts of Dr. Andrew Wolfe with errata (March
`January 4, 2023)
`Micron DDR5: Key Module Features, downloaded from
`https://media-www.micron.com/-
`/media/client/global/documents/products/technical-marketing-
`brief/ddr5_key_module_features_tech_brief.pdf?la=zh-
`tw&rev=f3ca96bed7d9427ba72b4c192dfacb56
`EPA, Report to Congress on Server and Data Center Energy
`Efficiency (Aug. 2, 2007), downloadable from
`https://www.osti.gov/servlets/purl/929723-4d6s1A/
`
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`Exhibit No.
`EX2048
`
`EX2049
`
`EX2050
`EX2051
`
`EX2052
`
`EX2053
`
`EX2054
`
`EX2055
`EX2056
`
`EX2057
`
`EX2058
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`Case No. IPR2022-00996
` Patent No. 11,016,918
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`
`
`Exhibit No.
`EX2059
`
`Document
`Intel, Fully Buffered DIMM Server Memory Architecture:
`Capacity, Performance, Reliability and Longevity (Feb. 18,
`2004), downloaded from
`https://www.bestor.spb.ru/v3/Content/pdf/OSA_S008_FB-
`DIMM-Arch.pdf
`EX2101 Wolfe Deposition exhibit, FB-DIMM Design Considerations
`(Feb. 18, 2004), downloaded from
`https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&do
`i=e1c8e931ff9f54dc673973af4b1044daec6883e8
`EX2102 Wolfe Deposition exhibit, Linear Technology PCI Express
`Power and Mini Card Solutions
`
`
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`STATEMENT OF MATERIAL FACTS IN DISPUTE
`Petitioner did not submit a statement of material facts in this Petition.
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`Accordingly, no response is due pursuant to 37 C.F.R. § 42.23(a), and no facts are
`
`admitted.
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`For reasons stated below, the Board should uphold the challenged claims.1
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`
`
`I.
`
`PETITIONER IMPROPERLY INCORPORATES BY REFERENCE
`For claims 16-30, the Petition alleges that the limitations are “substantially
`
`identical to earlier limitations” and then lists, without explanation, various
`
`paragraphs from its expert’s testimony in a series of tables. Pet. 50-51, 70-73, 123-
`
`127. In other places, Petitioner cites dozens, even hundreds of paragraphs from its
`
`expert declaration. E.g., Pet. 26 (over 50 paragraphs cited), 33 (14 paragraphs cited),
`
`35 (20 paragraphs), 42 (17 paragraphs), 52 (10 paragraphs), 56 (nearly 200
`
`paragraphs), 67-68 (12 paragraphs), 78 (19 paragraphs), 86 (citing ¶¶655-700) etc.
`
`The Board should not consider those incorporated arguments. See Cisco Systems,
`
`Inc. v. C-Cation Techs., LLC, IPR2014-00454 (PTAB Aug. 29, 2014) (Paper 12)
`
`(informative); 37 C.F.R. § 42.6(a)(3).
`
`II.
`
`SKILL LEVEL OF A POSITA
`For the purposes of this POR, Patent Owner is applying the level of ordinary
`
`skill in the art proposed by Petitioner. See Pet. 8-9.
`
`III. CLAIM CONSTRUCTION
`The term “memory module” appears in the preamble of the independent
`
`claims, which provides antecedent basis for the same term in the body of the text.
`
`
`1 All emphasis added unless otherwise noted.
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`Case No. IPR2022-00996
`Patent No. 11,016,918
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`The preamble is thus limiting as the District Court found after reviewing the
`
`specification in detail. EX2032, 28. The Court further explained that “a skilled
`
`artisan would understand a ‘memory module’ is distinct from, and has essential
`
`structural requirements not necessarily found in, other modular computer
`
`accessories. That includes the structure necessary to connect to a memory
`
`controller.” Id.; EX2034, 319. The court’s ruling is consistent with the specification
`
`which states in the Overview section that the invention is particularly “couplable to
`
`a memory controller of a host system.” EX1001, 3:66–67; see also id., 1:66–67
`
`(“[t]he present disclosure relates generally to computer memory devices”). Samsung
`
`objected to the court’s finding that the memory module is limiting, but does not
`
`dispute the Court’ finding on what a “memory module” means to a POSITA.
`
`EX2033, 4.
`
`The Court’s finding accords with testimony by Samsung’s expert that the term
`
`memory modules typically refers to “main memory modules,” which “are designed
`
`to connect to the primary memory controller for the purpose of the holding general
`
`purpose code and data in a computer system.” EX2030, 123:14-25; EX2056, 100:15-
`
`101:8 (by 2004-2005, a memory module “was intended to go into a dedicated
`
`memory slot and not a general-purpose IO slot”). The ’918 patent’s usage of
`
`“memory module” is consistent with that general understanding. The Board should
`
`thus adopt the District Court’s claim construction, including that the claimed
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`Case No. IPR2022-00996
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`“memory module” includes structures necessary to connect to a memory controller.
`
`EX2031, ¶¶51-53.
`
`IV. THE CLAIMS ARE NOT OBVIOUS UNDER GROUNDS 1-3
`A. Harris Does Not Disclose or Suggest a Memory Module Having a
`PCB Interface that Receives Voltage/Power from a Host System
`All challenged claims require a memory module that includes “a printed
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`circuit Board (PCB) having an interface … including a plurality of edge connections
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`configured to couple power … between the memory module and the host system.”
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`Pet. xi (1.b), xiii (16.b), xv (23.b); see also Pet. xiv (16.f) (reciting “a voltage monitor
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`circuit configured to monitor an input voltage received via a first portion of the
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`plurality of edge connections”). Thus, all challenged claims require that the memory
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`module includes a PCB interface that receives voltage/power from the host system.
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`Grounds 1-3 rely exclusively on Harris for allegedly disclosing this feature. Pet. 21-
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`22, 50-51, 71, 75-77. Harris does not disclose such a memory module.
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`Harris purportedly addresses the problems caused by increasing difficulty “for
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`the system board sources to provide tightly regulated power for the DRAM cores as
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`well as input/output (I/0) interface buffers” and the difficulty “to mix memory
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`technologies on a system board, or provide upgrades to next generation DRAM
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`technology in a cost-effective manner.” EX1023, [0002]. Against that backdrop,
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`Harris suggests an on-DIMM voltage regulator “for converting an externally
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`supplied voltage level available on external source path 104 into appropriate local
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`voltage levels ….” EX1023, [0010].
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`Harris’ modification, shown in FIG. 1A, is described as a “voltage-
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`independent FBD [Fully Buffer DIMM] design” which “replac[es] the[] power
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`supply interface pins with as few as six +12V pins (from an external power
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`source).” Id., [0012]; see also id., [0016] (“voltage is supplied to a memory board
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`assembly from an external source, e.g., an unregulated source generating fairly
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`high voltages (illustratively, at +12V) with a wide tolerance”). An external power
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`source is one provided outside the system board. EX2031, ¶56. Accordingly, Harris
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`supposedly provides a “technology-independent voltage distribution scheme for
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`memory devices wherein system board power supply and associated voltage
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`plane(s) are eliminated.” EX1023, [0019]; see id., (“elimination of system-board-
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`Case No. IPR2022-00996
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`specific power supply or regulator output ….”). In this way, Harris effectively
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`decouples the host system’s voltage supply from the memory module. EX2031, ¶58.
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`In Figure 1A, the DIMM is shown to exchange control information with the
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`memory controller and the next DIMM via the edge connections (see illustration
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`below), but receives the external voltage source from the side instead of the edge.
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`Supplying power to a DIMM from its side or its top was known.
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`See, e.g., EX2035 (backup battery connection not via edge connections); see also
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`EX2036, pp. 41-42 (super-capacitors connected via side or top); EX2031, ¶59
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`(unregulated DC voltage from batteries in e.g., an uninterrupted power supply unit
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`could be used to power the DIMMs).
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`Petitioner argues that Harris, [0012] suggests replacing the power pins in a
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`standard FBDIMM with 12V pins in the same DIMM connector, via which power
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`is supplied. Cf., EX2030, 130:3-9. But the relevant disclosures state, “replacing these
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`power supply interface pins with … +12V pins (from an external voltage source).”
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`EX1023, [0012]. Notably, Harris does not describe the +12V pins as “interface”
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`pins. And if Harris continued to supply power to the DIMM from the host as before,
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`it would be odd for Harris to observe that the +12V pins are associated with “an
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`external voltage source.” EX2031, ¶¶60-64. Consequently, a POSITA would
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`interpret the disclosure as placing the +12V pins at locations away from the interface
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`for connection to an external voltage source that is not from the system board. Id.
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`This interpretation comports with Petitioner’s acknowledgement that Harris’
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`“external supply voltage may be ‘unregulated.’” Pet. 74. Petitioner does not assert
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`that host systems designed to work with standard FBDIMMs would supply
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`unregulated voltages to DIMMs via corresponding memory slots. In fact, “[a]ll the
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`ones [that Dr. Wolfe is] familiar with supply regulated voltages.” EX2030, 62:21-
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`25; see also 92:9-95:8. Dr. Wolfe further confirms that in his experience, “[i]n the
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`kinds of computer systems that would use a FB-DIMM … those are regulated
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`voltages coming out of the power supply unit [PSU].” Id., 63:1-8; EX2037, p.22,
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`Table 15 (PSU output rail including 12V, 5V and 3.3V); EX2038, p.13, Table 2
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`(same).
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`Because a host computer would supply regulated voltages to DIMMs via
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`memory slots to DIMM interfaces, a POSITA would not have associated Harris’
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`12V unregulated voltage source with power sourced from a computer system or
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`supplied via memory slots. EX2031, ¶65. Furthermore, supplying unregulated
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`voltages or 12V via a memory slot would require modifications to the motherboard
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`because standard motherboards do not have such voltage rails going to the FBDIMM
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`connector, but Petitioner does not suggest such modifications. EX2030, 95:9-15; see
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`also EX1028, 9 (tightly regulated supply voltages from a host).
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`Consequently, a POSITA would understand that Harris’ 12V unregulated
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`voltage was not from the host or otherwise via the module interface. EX2031, ¶¶65-
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`66. They would also understand that distributing unregulated voltages via
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`motherboard to a memory slot would be unadvisable because “the non-trivial ripple
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`voltage associated with unregulated voltages could cause random noise patterns and
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`degrade signal integrity.” Id. And because Harris does not disclose that it used
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`different connection methods for regulated versus unregulated voltage sources, a
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`POSITA would also understand that even with regulated voltage sources, the voltage
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`was not supplied via the DIMM interface. EX2031, ¶66.
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`The Institution Decision notes that Harris discloses “that DRAM devices may
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`be ‘powered from system board or main board voltage sources’.” ID, 19. That
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`disclosure, however, is from Harris’ Background and represents the power
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`distribution approach of the prior art which Harris seeks to modify and improve on.
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`EX1023, [0002], [0020]. The modified FBDIMM upon which the challenge is based,
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`however, is powered from an external power “wherein system board power supply
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`and associated voltage plane(s) are eliminated.” See EX1023, [0010], [0012],
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`[0019]. Figure 3 of Harris does not show otherwise, because indisputably “a supply
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`voltage” is “not explicitly shown in this FIGURE.” EX1023, [0017]; EX2030,
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`130:19-23 (Dr. Wolfe: “Figure 3 is a block diagram and it does not show the power
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`supplies”). That is, Figure 3 does not indicate using edge connections to couple
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`“power … signals between the memory module and the host system.” EX2031, ¶60.
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`While Harris states that “[i]n one arrangement, the supply voltage may be
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`sourced from the memory controller 302 ….” (EX1023, [0017]), Dr. Wolfe testified
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`that, despite his 40 years’ experience in memory, he was not aware of any memory
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`controllers that supplied power supply voltages to DIMMs (EX2030, 130:19-
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`131:10). Dr. Mangione-Smith is also not aware of memory controllers that also
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`supply power to DIMMs. EX2031, ¶67. Dr. Wolfe also “does not suggest any
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`modifications to the host computer or to the host computer memory controller.” Id.,
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`95:9-15. Petitioner provides no evidence that a POSITA would have known how to
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`design a memory controller that supplied power to DIMMs. Raytheon Techs. Corp.
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`v. General Electric. Co., 993 F.3d 1374, 1381 (Fed. Cir. 2021) (requiring evidence
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`that the disclosure for a limitation is enabled).
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`Harris also states in passing that the external voltage can be any “known or
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`heretofore unknown voltage supplies.” EX1023, [0014]. As Dr. Mangione-Smith
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`explains, “a POSITA would not understand that omnibus statement to sweep in the
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`very type of voltage supply, i.e., system board voltage (an internal voltage source),
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`that Harris explains should be eliminated in order to achieve its specifically touted
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`benefits of improved upgradeability and extensibility, as well as with lower costs.”
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`EX2031, ¶68. Similarly, a POSITA would understand Harris’ statement that “120-1
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`through 120-K refer to K supply voltage paths which may be coupled to various
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`voltage sources provided within the electronic system (e.g., a computer system)”
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`(EX1023, [0014]) to mean that the voltage paths are external to the system board but
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`may be coupled to power sources, such as PSUs, in the electronic system. EX2031,
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`¶69.2 In any case, nothing suggests that the voltage paths are via the memory slot to
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`the interface edge connections. Id.
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`(Annotated Fig. 1B illustrating location of edge connections)
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`Otherwise, different edge pins would be needed for different voltage sources
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`that are independently distributed through the motherboard, increasing, rather than
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`decreasing, the cost for power distribution in the motherboard and pin count on the
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`DIMM connector to the motherboard. Contra, EX1023, [0013], [0019]-[0020];
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`EX2031, ¶70.
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`In sum, Harris teaches eliminating system board power distribution to the
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`DIMM slot to achieve its alleged benefits—a feature which Petitioner does not
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`2 For instance, power from PSU can be coupled to the DIMM via a connector on
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`the side of the DIMM.
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`propose to modify. As a result, Harris does not couple power between the memory
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`module and the host system, and therefore does not disclose elements 1.b, 16.b, 23.b
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`and 16.f. In fact, Harris expressly teaches that specific benefits can be achieved by
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`decoupling power between the memory module and supplied via the motherboard’s
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`power planes. EX1023, [0019]-[0020]; EX2031, ¶¶26, 58, 70.
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`For this same reason, Grounds 1-3 also do not disclose or suggest claim 13
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`(dependent from claim 5), because there is no power input voltage “received via a
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`… portion of the plurality of edge connections” that is coupled to the buck converters
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`and the converter circuit. See EX1001, 39:37-39 (“the power input voltage” has its
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`antecedent basis in “a power input voltage” in 38:62-64). Instead, in the modified
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`Harris, the power is received from connectors other than the edge connections.
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`B. Grounds 1-3 Do Not Disclose Elements 1(b), 16(b), 23(b) and
`1(i)(2), claims 8, 14 and 21
`Contrary to the Petition’s assertion, the DIMM and the AMB do not receive
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`
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`identified data signals (DQ0-DQ63) or address and control signals (A0-A15, RAS,
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`CAS, WE) from the host. Pet. 22-25. Instead, those are signals generated by the
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`AMB based on PS[9:0] and PS_bar_[9:0] of the “FB-DIMM Channel Signals”
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`received from the host. EX2031, ¶72; EX1027, p.4 (below); EX1028, p.29 (no
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`alleged data, address and control signals listed under FB-DIMM Channel Signals);
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`EX2039, p.2 (PS[9:0] & complement are deserialized and decoded); EX1027, p.3
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`(same); EX2101, p.4 (information in southbound frames deserialized and decoded
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`to generate C/A and data signals for SDRAMs); EX2040, p.1 (“FBDIMMs adopts a
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`packet-based protocol that bundles commands and data into frames that are
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`transmitted on the channel and then converted to the DDRx protocol by the AMB.”).
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